JPS59193070U - splice circuit - Google Patents

splice circuit

Info

Publication number
JPS59193070U
JPS59193070U JP8553283U JP8553283U JPS59193070U JP S59193070 U JPS59193070 U JP S59193070U JP 8553283 U JP8553283 U JP 8553283U JP 8553283 U JP8553283 U JP 8553283U JP S59193070 U JPS59193070 U JP S59193070U
Authority
JP
Japan
Prior art keywords
playback
delay
control signal
amount
signal during
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8553283U
Other languages
Japanese (ja)
Other versions
JPS6342760Y2 (en
Inventor
修一 飛田
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP8553283U priority Critical patent/JPS59193070U/en
Publication of JPS59193070U publication Critical patent/JPS59193070U/en
Application granted granted Critical
Publication of JPS6342760Y2 publication Critical patent/JPS6342760Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は記録時と再生時の走査跡を示す説明図、第２図
はつなぎ撮りにおける同じく説明図、第３図は本考案−
実施例の回路ブロック図、第４図イ。 口は要部波形図である。 主な図番の説明、３，４・・・・・・モノマルチ、４・
・・・・・時定数（遅延量）切換回路。Fig. 1 is an explanatory diagram showing scanning traces during recording and playback, Fig. 2 is an explanatory diagram showing the same in continuous shooting, and Fig. 3 is an explanatory diagram showing the scanning traces during recording and playback.
Circuit block diagram of the embodiment, FIG. 4A. The figure below shows the main part waveform diagram. Explanation of main drawing numbers, 3, 4...Mono multi, 4.
...Time constant (delay amount) switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ビデオテープレコーダのショートリワインド方式つなぎ
撮り回路において、つなぎ撮り再生における再生コント
ロール信号の遅延量を通常再生における前記再生コント
ロール信号の遅延量と異ならしめる時定数切換回路を備
えることを特徴とするつなぎ撮り回路。A short rewind splicing circuit for a video tape recorder, comprising a time constant switching circuit that makes the amount of delay of a playback control signal during spliced playback different from the amount of delay of the playback control signal during normal playback. .
JP8553283U 1983-06-03 1983-06-03 splice circuit Granted JPS59193070U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8553283U JPS59193070U (en) 1983-06-03 1983-06-03 splice circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8553283U JPS59193070U (en) 1983-06-03 1983-06-03 splice circuit

Publications (2)

Publication Number Publication Date
JPS59193070U true JPS59193070U (en) 1984-12-21
JPS6342760Y2 JPS6342760Y2 (en) 1988-11-09

Family

ID=30215497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8553283U Granted JPS59193070U (en) 1983-06-03 1983-06-03 splice circuit

Country Status (1)

Country Link
JP (1) JPS59193070U (en)

Also Published As

Publication number Publication date
JPS6342760Y2 (en) 1988-11-09

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