JPS59191956A - Line test system - Google Patents

Abstract

PURPOSE:To perform the test of a line without giving any disturbance to other lines by connecting a node having a frame buffer memory (FBM) to a loop transmission line and comparing the test signal sent from the FBM with the test signal received via a loop transmission line. CONSTITUTION:A central end office device 1 transmits the address of an address register 7 to an address bus L1 and at the same time transmits the channel number allotted to its own node to a data bus L2. In addition, the device 1 transmits the address of a transmission data register 2 to the bus L1 as well as the test data to the bus L2. Then the writing/reading is prepared for an FBM 4 corresponding to the time slot of the line to be tested with all lines set in an on- line state respectively excepting for the test line. In a test mode a certain pattern is written to the FBM 4, and this pattern is compared by comparators 10 and 11 with a pattern which is written to the FBM 4 after having one round trip of a highway.

Description

Detailed Description of the Invention (al) Technical Field of the Invention The present invention relates to a line test method for testing a loop-shaped transmission line in a node of a system in which a node having a frame buffer memory is connected to the loop-shaped transmission line. In particular,
The present invention relates to a line test method that allows testing of a single line without affecting other nodes.

BACKGROUND OF THE INVENTION In recent years, in the field of data communications, there is a data highway system in which a plurality of nodes each having a plurality of terminals are connected to a loop-shaped transmission line as a data communication system that is often used.

This data highway system will be explained below using diagrams.

FIG. 1 is a configuration diagram of an embodiment of a data highway system. In the figure, N1 to N8 are nodes, and L is a loop-shaped transmission line.

FIG. 2 is a diagram showing signal formants on a loop transmission path.

As shown in FIG. 1, the data highway system connects nodes N1 to N8 in a loop through a loop-shaped transmission path. In such a system, nodes N1 to N
A channel is assigned to each of the 8 channels. That is, the channel CHI shown in FIG. 2 is the node Nl, the channel CH2 is the node N2, and the channel C
H8 is assigned to each node N8. For example, when transmitting data from node N1, the data is placed on the channel CHI and transmitted. Note that each of the nodes N1 to N8 has a frame buffer memory in order to match the speed of the transmission data to the loop-shaped transmission path.

In such data highway system.

From the point of view of system maintenance, each node N1 to N8.

Tests were conducted on loop-shaped transmission lines to determine whether there were any faults in the loop-shaped transmission lines.

(C1 Conventional technology and problems An example of a conventional line test method will be described with reference to the drawings.

FIG. 3 is a configuration diagram of an embodiment of a node used in a conventional line test method. In the figure, 1 is a central control unit, 2 is a transmission data register, 3 is a selector, 4 is a frame buffer memory, 5 is a reception data register, 6 is a channel board, DRI and DR2 are drivers, LL is an address bus 1
L2 is a data bus, G is a gate, IN is an input terminal, O
UT is an output terminal. Note that the input terminal IN and the output terminal OUT'T are connected to a loop-shaped transmission path.

First, a case in which normal data transmission is performed will be explained.

In this case, the central control device 1 controls the selector 3 so that the data shown in FIG. 2 input from the input terminal IN is input to the frame buffer memory 4. Therefore, data from the loop-shaped transmission line inputted via the input terminal IN is inputted via the selector 3 from the input terminal IN of the frame buffer memory 4. Also, in this case,
Since the channel board 6 is controlled so that the driver DR2 is open, data from the loop-shaped transmission path input via the input terminal IN is taken into the channel board 6.

Thereafter, the data written as described above is outputted from the frame buffer memory 4 to the output terminal OUT via the gate G. At this time, if there is data to be transmitted on the channel board 6, the gate G is controlled to output the data on the channel assigned to its own node.

Next, a case where a two-line test is performed will be explained. In this case, the central controller connects address bus L1 to send data register 2.
At the same time, the test data is sent to the data bus L2. Therefore, such test data is written into the transmission data register 2. Also, in this case,
Since the central controller 1 controls the output of the transmission data register 2 to be input to the frame buffer memory 4, all data from the loop-shaped transmission line input via the input terminal IN is canted. Transmission data register 2
The output of is written to the frame buffer memory 4.

The test data written in the frame buffer memory 4 is then sent to the loop-shaped transmission path via the gate G and the output terminal OUT.

Thereafter, the test data received after going around the loop-shaped transmission path is inputted from the input terminal IN, written to the received data register 5, and then outputted.

At this time, since the central control device 1 controls the driver DRI to be open, the output of the reception data register 5 is input to the central control device 1 via the data bus L2.

Thereby, the central control device 1 compares the transmitted test data with the test data received after going around the loop-shaped transmission path, and detects the state of the loop-shaped transmission path.

However, such conventional line testing methods.

It had the following drawbacks. In other words, in the conventional line test method, all received data is cut within the node and the test data is sent out, so a 5-line test can only be performed with all lines offline, which is inefficient. There was a drawback.

(d) Purpose of the Invention In view of the drawbacks of the conventional line testing methods, the present invention aims to provide a line testing method that allows efficient testing of a single line without affecting other nodes. This is the purpose.

(el) Structure of the Invention In order to achieve the above object, the present invention provides a line test method in which a loop-shaped transmission line is tested at a node of a system in which a node having a frame buffer memory is connected to the loop-shaped transmission line. In.

The node is provided with means for controlling the test signal to be stored in the frame buffer memory address corresponding to the position of the channel assigned to the node, and the test signal sent from the frame buffer memory and the frame buffer This method is characterized in that the loop-shaped transmission path is tested by comparing test signals sent from the memory and received via the loop-shaped transmission path.

(fl Embodiment of the Invention Two embodiments of the line test method of the present invention will be described in detail below with reference to FIG. 4.

FIG. 4 is a configuration diagram of an embodiment of a node used in the line test method of the present invention. In the figure, the same numbers as in Figure 3 indicate the same parts, 7 is the address register,
8 is a reception counter, 9 is a transmission counter, and 10 and 11 are comparators.

First, a case in which normal data transmission is performed will be described.

In this case, no address is stored in the address register 7 from the central control unit 1. Therefore, the output of the comparator 10 always controls the gate G1 so that the data input from the input terminal IN is input to the frame buffer memory 4.

Therefore, the data 12 is written into the frame buffer memory 4 in accordance with the output of the data 12 input from the input terminal IN. In this case, the reception counter 8 is connected to the clock input terminal CL.
The clock input from K is counted. Gate G
2 selects the output of the reception counter 8 based on the write signal W from the central control device 1.

Thereafter, the data written in the frame buffer memory 4 is read out according to the output of the data G2, and
It is output to the output terminal OUT via. In this case,
The transmission counter 9 receives a clock input from the clock input terminal CLK. Further, the gate G selects the output of the transmission counter 9 based on the read signal R from the central control device 1.

At this time, it should be sent out on the channel board 6.

If there is data, it controls the gate G and outputs the data on the channel assigned to its own node.

Next, a case in which a 9-line test is performed will be explained. In this case, the central terminal device 1 connects the address register 7 to the address bus L1.
At the same time, the node sends the channel number assigned to its own node to the data bus L2.

Therefore, the channel number is written into the address register 7.

Further, in this case, the central terminal device 1 sends the address of the transmission data register 2 to the address register L1, and also sends the test data to the inverter bus L2. Therefore, such test data is written into the transmission data register 2.

Suppose now that data is input from the input terminal 1 as shown in FIG. Such data is written into the frame buffer memory 4 in response to the outputs of the games 1-G2. However, in this case, when a match between the output of the reception counter 8 and the output of the address register 7 is detected in the comparator 10, the comparator 10 controls the gate G1 to select the output of the transmission data register 2. do. That is, the data of the channel assigned to its own node is replaced with test data and written into the frame buffer memory 4. In this case, the reception counter 8 counts the clock input from the clock input terminal CLK. Further, the gate G2 is activated by the write signal W from the central control device 1.

The output of the reception counter 8 is selected.

Thereafter, the data written in the frame buffer memory 4 is read out in accordance with the output of the game controller G2.

It is outputted to the output terminal OUT via the gate G.

In this case, the transmission counter 9 has a clock input terminal C.
The clock input from LK is input.

Furthermore, the gate G selects the output of the transmission counter 9 in response to a read signal R from the central control device.

After that, the data received after going around the loop-shaped transmission path is manually inputted from the input terminal IN. and.

At this time, when the count output of the transmission counter 9 and the output of the address register 7 match, the data is written to the reception data register 5 and then output. i.e. 5
Among the received data, the data of the channel assigned to the own node will be written to the received data register 5. At this time, the central control device 1 controls the driver DPI
Since the output of the reception data register 5 is controlled to be open, the output of the reception data register 5 is input to the central control unit 1 via the data bus L2.

As a result, the central controller can transmit the transmitted test data and
The state of the loop-shaped transmission path is detected by comparing the test data received while going around the loop-shaped transmission path.

That is, as explained above, in the line testing method of the present invention, writing to and reading from the frame buffer memory corresponding to the time slot of the line to be tested is performed while all lines other than the line to be tested are kept online. Let's do it.

During the test, a certain pattern is written into the frame buffer memory, and after going around the three highways with that pattern,
Seven lines are tested by comparing the patterns written in the frame buffer memory again.

(g) Effects of the Invention As explained in detail above, according to the line testing method of the present invention, it is possible to test a line without interfering with the communication of other lines. This has the effect of allowing tests to be carried out.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of an embodiment of a data highway system.
Fig. 2 is a diagram showing signal formants on loop transmission, Fig. 3 is a configuration diagram of an embodiment of a node used in the conventional line test method, and Fig. 4 is an implementation example of a node used in the line test method of the present invention. It is an example block diagram. In the figure, Nl to N8 are nodes, -L is a loop-shaped transmission line,
1 is a central control unit, 2 is a transmission data register, 3 is a selector, and 4 is a frame buffer memory. 5 is a reception data register, 6 is a channel board, 7 is an address register, 8 is a reception counter, 9 is a transmission counter, 1
0 and 11 are comparators.

Claims (1)

[Claims] A node of a system in which a node having a frame buffer memory is connected to a roof-like transmission path. In the line test method for testing the loop-shaped transmission line,
The node is provided with means for controlling the test signal to be stored in the frame buffer memory address corresponding to the position of the channel assigned to the node, and the test signal sent from the frame buffer memory and the frame buffer A line test method characterized in that a loop-shaped transmission line is tested by comparing test signals sent from a memory and received via the loop-shaped transmission line.