JPS59189752A - Digital optical receiver - Google Patents

Digital optical receiver

Info

Publication number
JPS59189752A
JPS59189752A JP58064004A JP6400483A JPS59189752A JP S59189752 A JPS59189752 A JP S59189752A JP 58064004 A JP58064004 A JP 58064004A JP 6400483 A JP6400483 A JP 6400483A JP S59189752 A JPS59189752 A JP S59189752A
Authority
JP
Japan
Prior art keywords
coupling amplifier
output
comparator
signal
feedback circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58064004A
Other languages
Japanese (ja)
Inventor
Tadayoshi Kitayama
北山 忠義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58064004A priority Critical patent/JPS59189752A/en
Publication of JPS59189752A publication Critical patent/JPS59189752A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B10/00Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60Receivers
    • H04B10/66Non-coherent receivers, e.g. using direct detection
    • H04B10/69Electrical arrangements in the receiver
    • H04B10/695Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control

Abstract

PURPOSE:To operate stably a digital optical receiver for an optional binary code system even in a high bit rate by using an AC coupling amplifier and a comparator provided with a positive feedback circuit which has the same time constant of response as that of base level variance due to DC cut-off of the AC coupling amplifier. CONSTITUTION:If reception is started when the level for no signal of an AC coupling amplifier 12 and an average level of high and low level outputs of an inverting gate 7 are equal to each other, the base level of an output 12a of the AC coupling amplifier 12 starts falling; but since a discrimination threshold 6a falls with the same time constant, a well received and reproduced comparator output 4a is obtained. A feedback circuit 14 does not require quick response and is operated normally even in a high bit rate. Even if a waveform distortion is generated in a transmission line or the AC coupling amplifier, it is difficult that receiving and reproducing errors are generated because waveform conversion such as differentiation or the like is not performed. Even if receiving and reproducing errors are generated, the influence of these errors upon another bit can be ignored unless they continue for a long time of the approximate time constant of the feedback circuit 14.

Description

【発明の詳細な説明】 この発明は、2値ディジタル光他号を受信再生ずるディ
ジタル光受信装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital optical receiver that receives and reproduces binary digital optical signals.

第1図は従来のディジタル光速受信装置の構成図を示す
、、第1図において、(11は受光素子、(21はi+
:4:流結合増幅器、(31は微分回路、(4)は比較
器、(51は信号入力端子、(6)は判定しきい値浴子
、(71は反転ゲート、(約は卸還回路、(9)および
(101は抵抗、(11+は基準電圧徐である。第2図
は従来の光送受4″3装置Iの各部波形図である。、(
la)は受信)しイこ号、  (2a)は増幅器出力1
5号、  (3g)は微分波形、  (4a)は比へ結
果信号、  (6a)は判定しきいI同信号、  (7
a)は反転ゲート出力信号、’ (Ila)は基準電圧
源電圧信号ケ示す。
FIG. 1 shows a configuration diagram of a conventional digital light-speed receiver. In FIG. 1, (11 is a light receiving element, (21 is an i+
:4: Current coupling amplifier, (31 is a differentiating circuit, (4) is a comparator, (51 is a signal input terminal, (6) is a judgment threshold value, (71 is an inverting gate, (approx. is a wholesaler circuit) , (9) and (101 are resistors, and (11+ is a reference voltage.
la) is the reception) symbol, (2a) is the amplifier output 1
No. 5, (3g) is the differential waveform, (4a) is the ratio result signal, (6a) is the judgment threshold I signal, (7
a) shows the inverted gate output signal, and '(Ila) shows the reference voltage source voltage signal.

受光素子(11は受信光信号(lN)を光電変換り、て
The light receiving element (11 photoelectrically converts the received optical signal (IN).

直流結合増幅器(21へ出力する。直流増幅器+21は
受光素子(11からの入力を増幅して微分回路+31へ
信号(2a) ’e小出力る。信号(2a)は直流結合
増幅器(21の帯域が有限であるため、波形は鈍る。微
分回路(31は1自流増幅器(21から入力されるイ(
号(2a)を微分【。
The DC amplifier +21 amplifies the input from the light receiving element (11) and outputs a small signal (2a) to the differential circuit +31.The signal (2a) is output to the DC coupled amplifier (21). is finite, so the waveform becomes dull.The differential circuit (31 is a single current amplifier (21)
Differentiate No. (2a) [.

微分波形(3a)を比軟器(4)の信号入力端子(51
へ出力する。
The differential waveform (3a) is input to the signal input terminal (51) of the converter (4).
Output to.

比軟器(41は微分回路(31から入力される信号(3
a)と1判定し久い仮端子(61へ入力さnる?I’(
J定しき(ハ1直信号(6a)と全比較し、比較結果イ
を号(4a)を出力する。比較結果信号(4a)は反転
ゲート(7)により反ナムさi廟11還回路(β)へ入
力される。帰還回路(βlVi抵抗(9)および叫と、
11(準電圧源(111から構成され9反転ゲート(7
1の出力を分圧して比較器判定しAい値端子+61へ出
力する。ここでは* l!t1単のために微分回路(3
1の1i!t jt号時のレベルと1反転ゲート(7)
の高レベル出力Vl+と低レベル出力V1.の平均レベ
ルとが等[、い場合について説明する。基準電圧源(1
11の電圧(lla) k T(VII+VL)に設定
し、抵抗(9)および曲)の4よ(抗値R1,112は
微分回路(31の出力信号の中央VC−r11定し鳶い
値信号(6a)が一致するように。
Ratio softener (41 is a differential circuit (signal input from 31)
a) and the temporary terminal that has been judged as 1 for a long time (input to 61?I'(
The comparison result signal (4a) is outputted as the comparison result signal (4a). β).Feedback circuit (βlVi resistor (9) and
11 (quasi-voltage source (111) consisting of 9 inverting gates (7
The output of 1 is divided into voltages, judged by a comparator, and output to the A value terminal +61. Here *l! Differential circuit (3
1 of 1i! t jt level and 1 inversion gate (7)
High level output Vl+ and low level output V1. Let us explain the case where the average level of is equal to [,. Reference voltage source (1
Voltage (lla) of 11 is set to k T (VII + VL), resistor (9) and resistance value R1 of 4 (resistance value R1, 112 is the center VC-r11 of the output signal of 31) So that (6a) matches.

を肖足する値trc設定−1−る。ただしvo、は微分
1!:11路(31の零−ビーク値である。このとき、
シ愉還回路(81による帰還により比較器(41にはヒ
ステリシス特性が生じる。このヒステリシス特性により
弔2図に示すようにディジタル光受信装置k、11よ良
好に受イ片再生を行うことができる。捷だ、この動作は
信号のイ、j号形式を問わず動作させることができる。
Set the value trc to add -1. However, vo is differential 1! : 11 road (zero-beak value of 31. At this time,
Feedback by the signal feedback circuit (81) causes a hysteresis characteristic in the comparator (41).As shown in Figure 2, this hysteresis characteristic allows for better signal regeneration than in the digital optical receivers k and 11. .This operation can be performed regardless of the A or J format of the signal.

l、かじ、従来の光送受信製麹でに、微分回路(3)を
用いているため、受信4M号(]II)K歪みがある場
合や、@流結合増幅器(21において希みが生じる場合
、微分出力(3a)の像幅が変動し、符号量干渉が発生
する等の原因で受信再生誤りが生じゃすい欠点があった
。高ビットレートになるとこの欠点は著しくなる。
Since the conventional optical transmitter/receiver uses a differentiating circuit (3), there may be cases where there is K distortion in the receiving 4M (]II) or where distortion occurs in the @flow coupling amplifier (21). , the image width of the differential output (3a) fluctuates, and there is a drawback that reception and reproduction errors are likely to occur due to the occurrence of code amount interference, etc. This drawback becomes more noticeable as the bit rate becomes higher.

また、比較器(4)1反転グー[71,帰還回路(81
における帰Mは1ビット以内に帰還される必要があシ高
速のビットレートでは高速の帰還回路容が必要になる。
In addition, comparator (4) 1 inverting goo [71, feedback circuit (81
The feedback M must be fed back within one bit, and a high bit rate requires a high speed feedback circuit.

また、受信再生眠りが発生した場合。You can also receive playbacks if you fall asleep.

誤った帰返がかかるので、受信再生誤りが他のビットに
波及する恐れがある等の欠点があった。
Since erroneous feedback is applied, there is a drawback that reception and reproduction errors may spread to other bits.

この発明はこれ等の欠点を除去するため、微分回路の代
わりに交流結合増幅器を用いるとともに。
In order to eliminate these drawbacks, the present invention uses an AC coupled amplifier instead of a differentiating circuit.

比較器出力を帰還する帰還回路に時定数を与え。Give a time constant to the feedback circuit that feeds back the comparator output.

その時定数全交流結合増幅器の1自流遮断による信号基
底レベル変動時定数と等しくしたもので、以下図面につ
いて詳細に説明する。
The time constant is set to be equal to the signal base level fluctuation time constant due to one current cutoff of the fully AC coupled amplifier, and will be described in detail with reference to the drawings below.

回路である。It is a circuit.

受光卒子(1)は受信信号(1a)金光電俊換して、に
流111合増’1liii器(121へ出力する。交流
結合増幅器021は。
The light receiver (1) converts the received signal (1a) into a light beam and outputs it to the 111-amplifier (121).

受光素子(11からの入力信号を増幅して比較器(4)
へ44号(12a)を出力する。比1奴器(4)は信号
人力遍)子(51へ入力される信号(12a)と判定し
きいイ11端子(61へ入力される判定しきい値信号(
6a)117比較し、比較結果信号(4a)を出力する
。反転ゲート(71は比1灰器(4)の比較結果(M号
(4a)k反転し0反転出力(7a)を抵抗(91、(
llJl、 :yンデンザ+131 、基準゛電圧源0
1)で構成される帰還回路(14iへ出力される。判定
しきい値(6a)は、一端が反転ゲート(71に接続さ
れfc抵抗(91と、一端が基準電圧源(11)に接続
された抵抗(101と。
Amplify the input signal from the light receiving element (11) and convert it to a comparator (4)
Output No. 44 (12a) to. The ratio 1 terminal (4) is the signal (12a) input to the signal input terminal (51) and the determination threshold signal (12a) input to the terminal 11 (61).
6a) 117 comparison and outputs a comparison result signal (4a). The inversion gate (71 is the comparison result of the ratio 1 ash unit (4)
llJl, :ydenza+131, reference voltage source 0
1) is output to the feedback circuit (14i).The judgment threshold (6a) has one end connected to the inverting gate (71) and the fc resistor (91), and one end connected to the reference voltage source (11). resistance (101).

一端が接地されたコンデンサ(131の共通接続点と比
較器(4)の判定しきい111J、端子161 ’k 
接続して得られる。
A capacitor with one end grounded (common connection point of 131 and judgment threshold 111J of comparator (4), terminal 161'k
Get connected.

ここでは、簡単のfcめに交流結合増幅器(121の無
信号時のレベルと反転ゲート(71の高レベル出力Vl
、と低レベル出力v1.の平均レベルとが等しい場合に
ついて説明する。
Here, for a simple fc, the level of the AC coupled amplifier (121 when no signal is present) and the inverting gate (high level output Vl of 71)
, and low level output v1. The case where the average level of is equal to the average level will be explained.

従来と同様、電源Qllの電圧は+(VH+VL)  
に設定し、抵抗(9)および(101の抵抗値R1+ 
R2は(11式を満足するように設定する。捷り、コン
デンサ(1j1の容量は、交流結合増幅回路(91の直
流連断による信号の基底レベル変動時定数τが、帰還回
路用;の時定数と一致するように k n&B足する値に設定している。受信を開始すると
As before, the voltage of power supply Qll is +(VH+VL)
and the resistance value R1+ of resistors (9) and (101)
R2 is set to satisfy Equation 11.The capacitance of the capacitor (1j1 is set when the base level fluctuation time constant τ of the signal due to the DC connection of 91 is for the feedback circuit; The value is set to k n & B plus to match the constant. When reception starts.

第4図に示すように交流結合増幅器u’lJの出力(1
2a)の基底レベルは下りはじめるが、判定しきい値(
6a)も同じ時定数で下るので良好に受イμ再生した比
較器出力(4a) k得ることができる。また、この動
作は任意の符号形式の信号に対して動作させることがで
きる。帰還回路東は速い応答は不必要であり、高ビット
レートに対しても正常に動作する。
As shown in Fig. 4, the output (1
The base level of 2a) begins to fall, but the judgment threshold (
6a) also falls with the same time constant, so it is possible to obtain the comparator output (4a)k which has been well regenerated. Further, this operation can be performed on signals of any code format. Feedback circuit east does not require a fast response and works well even for high bit rates.

また、伝送路や交流結合増幅器において波形歪みが生じ
ても、微分専の波形変換をしないので受信再生誤りは発
生しにくい。また、受イ1書生誤りが生じても、#還回
路(!41の時定数程度の長時間続かなけれは他のビッ
トへの誤り波及は無視できる。
Furthermore, even if waveform distortion occurs in the transmission line or AC coupling amplifier, reception and reproduction errors are less likely to occur because differential-only waveform conversion is not performed. Furthermore, even if a receiver error occurs, the spread of the error to other bits can be ignored unless it continues for a long time, about the time constant of the # return circuit (!41).

なお2以上は交流結合増幅器(I21の無個号時出力レ
ベルと反転ゲート(71の出力の平均レベルが等しいと
して説明1〜だが、他の場合についても抵抗(91゜t
llllの抵抗値および基準電圧源(11)の電源車圧
金俊えることにより同様の動作をさせることができる。
Note that 2 or more is an AC coupled amplifier (1) assuming that the output level when no signal of I21 is equal to the average level of the output of the inverting gate (71), but in other cases, the resistance (91°t
A similar operation can be achieved by adjusting the resistance value of llll and the power supply voltage of the reference voltage source (11).

捷た。正相および逆相出力端子を有する比吸器では1反
転グー) +71は使用せず逆相出力を帰還回路へ接続
しても同様の動作音させることができる。
I cut it. In a specific absorber having positive-phase and negative-phase output terminals, the same operating noise can be obtained even if +71 is not used and the negative-phase output is connected to the feedback circuit.

以上のように、この発明に係るディジタル光受信装置で
は、交流結合増幅器と交流結合増幅器の血流離断による
基底レベル変動時定数と等しい応答時定数の正帰還回路
を有する比較器を用いることにより高ビットレートにお
いても、任意の2仮着号形式に対して安定に動作させる
ことができる利点がある。
As described above, the digital optical receiver according to the present invention uses an AC coupled amplifier and a comparator having a positive feedback circuit with a response time constant equal to the base level fluctuation time constant caused by blood flow transection in the AC coupled amplifier. Even at high bit rates, it has the advantage of being able to operate stably for any two provisional encoding formats.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のディジタル光受信装置の措成図。 第2図は従来のディジタル光受信装置の各部波形図、第
3因は本発明による光受信装置一実施例の4’?4成図
、第4図は本発明による光受信装置の各部波形図である
。 図中、(4)は比較器、(7)は反転ゲート、計・は交
流結合増幅器、 fliは!Ifl還回路である。なお
1図中。 同一あるいは相轟部分には同一符号を付して示しである
。 代理人大岩増ハ1 第1図 第2図 13図 訝 第4図
FIG. 1 is a schematic diagram of a conventional digital optical receiver. FIG. 2 is a waveform diagram of each part of a conventional digital optical receiver, and the third factor is 4'? of an embodiment of the optical receiver according to the present invention. FIG. 4 is a waveform diagram of each part of the optical receiver according to the present invention. In the figure, (4) is a comparator, (7) is an inverting gate, total is an AC coupling amplifier, and fli is! This is an Ifl return circuit. Also in Figure 1. Identical or similar parts are designated by the same reference numerals. Agent Masu Oiwa 1 Figure 1 Figure 2 Figure 13 Diagram 4

Claims (1)

【特許請求の範囲】[Claims] 2 (1i1−ディジタル光信号を受信するディジタル
光受信装置において、受光素子出力端子に接続された交
流結合増幅器および前記交流結合増幅器出力を判定しき
い値と比軟して2 ’ It+ディジタル信号を再生す
る比較器および前記比較器出力を反転する反転ゲートお
よび前記反転ゲート出力を−nr1;rピ交流結合増幅
器の直流連断による信号基底レベル装動時定数と等しい
応答111定数で回器比較器判定しきい値入力へ帰還す
る帰還回路とで構成されたことを特徴とするディジタル
先受イΔ装置。
2 (1i1- In a digital optical receiver that receives a digital optical signal, an AC coupling amplifier connected to a light receiving element output terminal and the output of the AC coupling amplifier are compared with a determination threshold value to reproduce a 2' It+ digital signal. A comparator that inverts the output of the comparator, an inversion gate that inverts the output of the comparator, and a response 111 that is equal to the signal base level installation time constant due to the DC connection of the AC coupling amplifier, and the circuit comparator is determined by -nr1; What is claimed is: 1. A digital pre-reception A Δ device comprising a feedback circuit that feeds back to a threshold input.
JP58064004A 1983-04-12 1983-04-12 Digital optical receiver Pending JPS59189752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58064004A JPS59189752A (en) 1983-04-12 1983-04-12 Digital optical receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58064004A JPS59189752A (en) 1983-04-12 1983-04-12 Digital optical receiver

Publications (1)

Publication Number Publication Date
JPS59189752A true JPS59189752A (en) 1984-10-27

Family

ID=13245614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58064004A Pending JPS59189752A (en) 1983-04-12 1983-04-12 Digital optical receiver

Country Status (1)

Country Link
JP (1) JPS59189752A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07193546A (en) * 1993-12-27 1995-07-28 Nec Corp Light-receiving circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07193546A (en) * 1993-12-27 1995-07-28 Nec Corp Light-receiving circuit

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