JPS59185092A - Voltage changeover circuit - Google Patents

Abstract

PURPOSE:To offer a voltage changeover circuit switching and outputting two voltages in response to an input signal by constituting a circuit among a voltage output terminal and two voltage applying terminal by means of a specific circuit using three depletion MOS transistor (TRs). CONSTITUTION:A voltage VH is selected as VC (5V) at an information read and 30V at write. Since a node N3 is at a low level at first when a row line Ri is not selected, an output of an inverter I3 goes to a high level and an MOSTRT15 is turned on. In selecting gm ratio of the MOSTRT15 and an MOSTRT16 sufficiently large, an MOSTRT12 is cut off. On the other hand, when the row line Ri is selected and goes to a high level, an output of the inverter I3 goes to a low level and the T15 is cut off. When the VH reaches 30V in this case, the voltage VH is given to the row line Ri via the T12 and T16. That is, a write circuit 106i is the voltage changeover circuit switching and outputting any of the VH and VC in response to the signal of the node N3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a voltage switching circuit used in a nonvolatile semiconductor memory device with improved information writing characteristics.

[Technical background of the invention and its problems]

A double dart type MOS transistor with a floating dart structure is used as a memory cell, and a high voltage is applied to the control dart provided on the floating dart and the drain, and the source is set to almost ground potential to generate inno-reactive ionization. A non-volatile device in which information can be written electrically, which stores information by capturing electrons from the electron-hole pairs generated at this time in floating darts and changing the threshold voltage. KPROM is a semiconductor memory device.
(Erasable Programmable ROM
) is well known as.

FIG. 1 is a circuit diagram showing an example of a conventional EPROM. In the figure, R, ~Rm are row lines, and Dl~Dn are column lines), and each intersection of these row lines R□~Rm and column lines D1~Dn is made up of the double dart type MOS transistors. Memory cells TM11 to TMmn are provided, and these memory cells TMI 1 = TMmn (7) Control a'l
- drains are connected to each row line R1-Rm, and drains are connected to each column line D1-D.
n, respectively, and all memory cells T
The sources of MII to TMmn are connected to ground potential. The row lines 81-8m, column lines D1-Dn and memory cells TM11-TMmn constitute a memory cell section 10.

The row lines R1 to R= are information read and write control signals R
Each MO8) transistor of depression type (hereinafter abbreviated as type) with /W as dart input
+ to the row decoder 20. This row decoder 20 selects one row line according to the supplied row address signal, and outputs a high level signal from the output terminal corresponding to the selected row line.

The column line D1%Dn is connected to the encoder in the column line selection circuit 30.
MO for selecting each column line of the performance type (hereinafter referred to as E type)
8) Connected to signal detection node N1 via transistors TD, -TDn. The signal at the node N1 is detected by the sense amplifier 7°40, and this detection signal is further output to the outside via the output circuit 5θ. In addition, r- of the column line selection MOS transistors TD1 to TDrl
) are connected to the column selection lines Ct to Cn, and these column selection lines C1 to Cn are connected to the column decoder 60 via each D-type MO8) resistor TC1 to TCn which receives the signal R/W as a dart input. It is connected. This column decoder 60 selects one column selection line according to the supplied column address signal, and outputs a high level signal from the output terminal corresponding to the selected column selection line.

Further, the other ends of the row lines R1 to Rm and the column selection lines C1 to Cn are connected to a D-type MO whose drain is connected to the write voltage Vp application terminal in the write transistor circuit 70.
The sources and darts of S transistors WR, -WRm1WC1-WCn are connected.

Note that all write voltage application terminals in the write transistor circuit 7o are commonly connected to a write power supply terminal (not shown).

An E-type information writing MOS transistor T1 is connected between the signal detection node N and the other write voltage application terminal, and the output node of the write information input control circuit 8 is connected to the MOS transistor T1. A signal of N2 is supplied. This write information input control circuit 80 includes an internal information generating circuit 85 that receives external input information Din and generates internal information din according to this information, and a D-type circuit between the write voltage 2 application terminal and the ground potential. MOS) transistor T
2 and an E-type MOS) transistor T3 are inserted in series, and an inverter E1 is inserted between the output node N2 and the ground potential to invert the internal information din and provide it to the output node N2, and output the signal. It is composed of an E-type MOS transistor T4 whose R/W is a gate input.

In the conventional EFROM configured as described above, when information escapes, the signal R/W is at a high level ("1# level)," the voltage VP becomes 5 volts, and the MOS
) transistors TC1 to TCn, TRI “”-TR
9M08) turns on, transistor T4 turns on, and node N2 becomes low level ("o" level), turning off transistor T1 (9M08). 1- Each MO8) transistor wc in the transistor circuit zo for inclusion
Funductance gmii of 1~wcn2wR1~wRm
: Because it is set extremely small, the row lines R1 to Rm
Of the column selection lines C and -Cn, the one selected by the row decoder 2o or column decoder 6° is set to high level, and the others are set to low level. Memory cells located at the intersection are selectively driven. When the threshold voltage of this memory cell is low, it turns on and current flows between the drain and the source, so the signal detection node N1 becomes low level. On the other hand, information is written to this memory cell in advance. If the threshold voltage is high, this memory cell is turned off and the synode N1 becomes high level. Therefore, the signal at node N1 at this time is output to the outside via sense amplifier 40 and output circuit 50.

On the other hand, when writing information, the signal R/W becomes low level and VP rises to 25 volts. At this time, for example, the row line R
1 and the column selection line C1 are selected by the row decoder 20 and the column decoder 60, the MOS transistor T
RI p TCI is cut off and the row line R1 and column selection line themselves are connected to the MOS transistor WR in the write transistor circuit 70.

The outputs of the row decoder 2θ and column decoder 60 are at a low level, and the outputs of the row decoder 2θ and column decoder 60 are at low level for the other row lines and column selection lines. Since it turns on, it reaches a low level, that is, ground potential. At this time, if the external input information Din is at a low level, the internal information din is also at a low level, and 25 g is output to the node N2, so the MOS transistor T1 is turned on and the node N1 reaches the threshold It is charged at approximately 22 volts (voltage). Therefore, a voltage of 25 volts is applied to the control gate of the memory cell TMH selected by row line R1 and column line D1, and a voltage of 25 volts is applied to the drain of memory cell TMH selected by row line R1 and column line D1.
”'IH(TDl)(vTH(TI) ”TH(TDi)
) are respectively applied with a voltage of about 22 volts given by the threshold voltage of transistor T1 or TDl), and at this time information is written into this memory cell TM11 by the impact ionization.

If the external input information Din is at a high level, the MOS transistor T1 is cut-on, so that no voltage can be applied to the drain of the memory cell TM11, and the insertion is not performed. Furthermore, once a memory cell has been programmed, information is stored until it is erased, so the information remains non-volatile.

In the conventional EFROM described above, the input voltage (2) is fixed at 25 volts, so it usually takes 50 m5.5 to write information into one memory cell. There is a disadvantage that the time required to write information increases in a large-scale memory. For example, when writing information to all memory cells of a memory whose storage capacity is 4 words x 8 bits, 3
It will take nearly a minute.

By the way, Figures 2(a) to (c) show a MOS transistor with a floating dart structure and its characteristics. Figures 2(a) to 2(c) show a simple diagram of the MOS transistor, and Figure 2(b) ) is the drain voltage■. and the amount of change ΔvT in the threshold voltage with respect to the control dirt voltage vG when writing information with the writing time tP constant.
Figure 2 (c) is a characteristic diagram showing the control dart voltage ■.

Assuming that the drain voltage is constant,■.

FIG. 12 is a characteristic diagram showing the amount of change in threshold voltage ΔvTH with respect to the logarithm of write time 1P when information is written using as a parameter. In addition, Figure 2 (
c) Middle curve A is for when ■9 is large, and curve opening is for small. Figure 2 (b), (c)
As is clear from the above, the higher the control dart voltage VG is, the longer the writing time tP is, and when tP is relatively long, ΔVTH does not depend on ■9, but when tP is a furnace, VD The larger the value, the shorter the time needed to reach the predetermined Δ■TH. Therefore, in order to shorten the write time in the gFROM shown in FIG. 1, it is sufficient to increase the control dart voltage or drain voltage of each memory cell.

[Purpose of the invention]

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to
An object of the present invention is to provide a voltage switching circuit that switches and outputs two voltages.

[Summary of the invention]

According to the present invention, the first MOS transistor is of disolation type, one end of which is connected to the first voltage application terminal that receives a high voltage when writing information, and the dart is connected to the voltage output terminal. One end is connected to the second voltage application end to which is applied, and the other end is connected to the other end of the first MOS transistor, and a signal having the opposite phase to the signal set at the voltage output end is applied to the dart. a depletion type second MOS) transistor whose one end is connected to the other end connection point of the first and second MOS transistors, and whose other end and dart are connected to the voltage output terminal. A voltage switching circuit consisting of a third MOS transistor is provided.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, 20 is a row decoder and TI'H as in the conventional case.
has one end connected to the output end of this row decoder 20, and the other end connected to the row line R.
A D-type MOS transistor (however, 1
≦i≦m). A write control circuit 100 is provided at the other end of the row line Ri instead of the write transistor circuit 70, and the other end of the row line Ri is connected to one write circuit 105 in the write control circuit 100. Connected to output node N3.

The write circuit 105i is an E-type MOS transistor T5 inserted between the node N3 and the voltage vH application terminal boosted to 71 or more by the write voltage vP booster circuit, and the signal at the node N3. M of D type as input
OS) transistor T6 and E type MOS) E/D type inverter I2 consisting of transistor T7, the above MO
8) An E-type MOS inserted between the gate node N4 of the transistor T5 and the ground potential and having the output of the inverter 2 as a dirt input.) Transistor T8, this MOS
) An E-type MOS transistor T9 connected in parallel with the transistor T8 and receiving the signal R/W as a dirt input; a neutral type MOS transistor T9 whose threshold voltage is close to Q&Silt, which is inserted between the nodes N4 and N5; (hereinafter abbreviated as N type)
MOS transistor 'flO, an E-type MOS transistor T1 inserted between the above node N5 and the application terminal of the write voltage VP, and a capacitor CPI inserted between the above node N5 and the application terminal of the pulse signal O8C, which will be described later. It consists of Note that the dart of the MO3) rank star TIO is connected to the node N5, and the dart of the MOS transistor Tll is connected to the write voltage vP application terminal.

Next, the operation of the circuit configured as described above will be explained. First, when V reaches 25 volts when writing information, VH is boosted to about 30 volts.

At this time, when the row line Ri is selected by the row decoder 20 and the row line R1 and node N3 go high, the output of the inverter 2 goes low, so the MOS transistor T8 is cut off. Furthermore, since the signal R/W is at a low level, the MOS transistor T9 is also cut off. Therefore, node N4 is charged via VPKj via MOS transistor 'fll and T2O.

On the other hand, the pulse signal O given to one end of the capacitor CPI
Since 8C has an amplitude approximately between the ground potential and vP, the voltage 5 at the node N5 is, in principle, a voltage as shown in the following equation.

v5-(VP-vTH(T11))+vP″vTH(T
11) 2 Threshold voltage of MOS transistor T11■
P': The amplitude of the signal osc and the voltage v4 of the node N4 are lower than ■5 by the threshold voltage vTH (T10) of the MOS transistor TIO, so V4-(vp-vTn(rll)) ru(T
+o). Furthermore, in reality, there is a parasitic capacitance at the node N5, and the voltage v4 at the node N4 is equal to the capacitance CPI.
Since the voltage decreases slightly due to the capacitance division between the parasitic capacitance and the parasitic capacitance, approximately 35 volts can be obtained as (4). As a result, the Mos transistor T5 operates as a triode, and the node N
3, that is, the row line Ri is directly applied with a voltage □ whose value is approximately 30°. Therefore, in the memory cell whose control dart is connected to this row line IRi, the control dart voltage is about 5 volts higher than the conventional one, and it is clear from the characteristic diagram shown in FIG. You can also write information in a short time. In other words, it is possible to shorten the writing time.

FIG. 4 is a circuit configuration diagram of another embodiment of the present invention, which differs from the circuit of the above embodiment in a write circuit. That is, the write circuit 1061 in this embodiment circuit is inserted between the voltage ■□ application terminal and the node N6.
A D-type MOS whose input is the signal from the transistor T12 and the node N3.
) Ransistor T13 and E-type MOS) Run raster T1
An E/D type inverter consisting of 4 voltages is inserted between the 3.5 volt power supply voltage v0 application end and the node N6,
D-type M with the output of the above inverter ■3 as the dart input
OS transistor T15, the above node N6 and node N3
and the dart is connected to node N3.
It consists of a transistor T16 (MOS type).

In the above configuration, the voltage (1)8 is set to ve (5 volts) when reading information, and is set to 30 when writing information. When the current row line Ri is in a non-selected state, the node N3 is initially at a low level regardless of whether information is being read or written. Therefore, the output of the inverter 3 is at a high level, and the MOS transistor T15 is turned on. Now, if the gm ratio of the MOS transistors T15 and 716 is set sufficiently large, the node N6 becomes almost ■. In order to reach the voltage level, the MOS transistor T12 is cut off, and the voltage vH application end is separated from the node N3, that is, the row line R1. Therefore, no current flows out from vH. On the other hand, when the row line Ri is selected and becomes a high level, the output of the inverter 3 becomes a low level, and the MOS transistor T15 is cut off. At this time, VH is 3
0? If it is in the default state, the node N3 is charged with vH through the MOS transistors T12 and T16, and the voltage VH of 30 volts is applied to the row line R1. That is, the switching circuit 1064 is a voltage switching circuit that switches and outputs either one of the voltages vJ(, ①o) according to the signal at the node N3.

FIG. 5 is a circuit diagram showing an example of a voltage boosting circuit for obtaining the voltage vH and the pulse signal OSC. In the figure, 11θ is a ring oscillator RO8 consisting of three stages of inverters 111 to 113 whose power source is a voltage of 5 volts.
This is an oscillation circuit consisting of an E-type MOS synristor T17 for oscillation control which is inserted between the output node N7 of the ring oscillator RO8 and the ground potential and receives the signal R/W as a dart input. The signal at the output node N7 of this oscillation circuit 11θ is transmitted through D-type MOS transistors T18 and E
An E/D type inverter I4 consisting of a transistor T19 (MOS) transistor T19 changes the amplitude between the ground potential and
The /e pulse signal O8c is obtained. Further, the pulse signal O8C is applied to the node N8 via the capacitor CP2. This node N8 is connected to an E-type MO whose drain and dart are connected to the voltage vP application terminal.
S) The source and drain of transistor T20 are at voltage ■
. A D-type MOS connected to the application terminal and having the signal R/W as a dart input) and the source of the transistor T21 and the N
The drain and dart of transistor T22 are connected to each other. Also, above MO8) transistor T22
The source of is connected to the output node N9 for obtaining the voltage vH.

Furthermore, the drain and r-t of the node N9 have a voltage of
, an E-type MOS) transistor T2 connected to the applying end.
The source and drain of 3 are at voltage V. A D-type MOS transistor T24 which is connected to the application end and receives the signal R/w as a dart input is connected in parallel with the source of a transistor T24.

In the voltage booster circuit having the above configuration, the signal R/W is at a high level during careful reading, and the MOS in the oscillation circuit 110
) Since transistor T17 turns on, ring oscillator RO
8 does not oscillate. Also MOS) transistor T21. T
24 is also turned on, so both node N8 and node N9 reach vc(5?root).

On the other hand, when writing information, signal R/W is low level, VP=2
When the voltage reaches 5 delts, the oscillation circuit 110 operates, and the inverter 4 outputs the pulse signal osc. At this time, MOS) lunge state 2.

T24 is cut-on, and immediately after the oscillation circuit 110 starts oscillating, node N8 is a MOS) through Lannostar T20 to ■P-vTH (T20) (vTH (T20) is MOS) the threshold voltage of Lannostar T20). , node N9 is a MOS) through transistor T23, -
They are each charged to VTH(T23) (vTH(T23) is the threshold voltage of the MOS transistor T23). After the above-mentioned oscillation starts, the voltage of node N8 changes to
-Vrn(T0n) + Vp'(Vp' is the signal o
Since this voltage is rectified by the MOS transistor T22, the voltage at the node N9, ie, V, is finally given by the following equation.

■H-(■P-VTn(T2.o))+vp”TH(T
22) ■T, 1 (T□2) two MOS transistors T22
However, in reality, 8 changes depending on the capacitance ratio between the parasitic capacitance existing at the node N8 and the capacitance CP2, so by appropriately setting this ratio, the above 30
It can be made into a bolt.

FIG. 6 is a circuit diagram of still another embodiment of the present invention. In this embodiment circuit, write circuits 105 and 106 are provided at the other end of each of the column selection lines 01 to Cn as shown in FIG. Circuit 1 shown in Figure 4
It is equipped with a circuit similar to 06.

With such a configuration, column selection lines 01 to C
A voltage of approximately 30 ports is obtained even at node N1.
can be set to 1, so that approximately Vp can be obtained on the column line DI-Dn. That is, in this embodiment, a voltage of 30 volts is applied to the open side gate of the selected memory cell, or a voltage of 25 volts is applied to the drain of the selected memory cell.
Compared to the conventional model, the control gate voltage is increased by 5 delts, and the drain voltage is increased by 3 delts. Therefore, it is possible to effectively shorten the information writing time.

Note that the present invention is not limited to the embodiments described above; for example, the voltage booster circuit may not necessarily have the configuration shown in FIG. 5, and the boosted voltage vH may still be 3
It may be 0 volt or more.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide a voltage switching circuit that can switch and output two voltages according to an input signal.

[Brief explanation of drawings]

Figure 1 is a circuit configuration diagram showing an example of a conventional EFROM, and Figures 2 (,) to (c) are MOSs with a floating dart structure.
) shows a transistor and its characteristics; FIG. 2 (, ) is a Schindel diagram, FIG. 2 (b) and FIG. 2 (c) are characteristic diagrams, respectively, and FIG. 4 is a circuit diagram of another embodiment of the present invention; FIG. 5 is a circuit diagram showing an example of a voltage booster circuit used in the embodiment circuit shown in FIGS. 3 and 4; FIG. FIG. 6 is a circuit configuration diagram of still another embodiment of the invention. 10...Memory cell section, 20...Row decoder, 30
...Column line selection circuit, 40...Sense amplifier, 50.
... Output circuit, 60... Column decoder, 70... Write transistor circuit, 80... Write information input control circuit, 85... Internal information generation circuit, 1θ0... Write control circuit, 105, 106...Writing circuit, 110
...Oscillation circuit, 111-113...Inverter, T
Ml, ~TMmn ''Memory cells, TR1~TRm. TCI~TCn, WR, ~WRm, WC, ~WC,
, T2TT6 , T12 , T13 , T15
, T18, T21°T24...depression type MOS) transistor, TM, T, 9. T4. T
,5. T7. T8. 'I'l. T11. T14+T17. T19. T20゜T2C...
・Enhancement type MOS) transistor, T10
．． T22...intrinsic type MOS) transistor, ■1~I4...E/D type inverter, N1~
N9...Node, CF2. C20...Capacity.

Claims (2)

[Claims] (1) A depletion type first MOS having a voltage output terminal, a means for presetting a signal of the voltage output terminal, and one end connected to the first voltage application terminal and a dart connected to the voltage output terminal. A transistor, one end of which is connected to the second voltage application terminal, and the other end of which is connected to the other end of the first MOS transistor, is connected to the other end of the first MOS transistor, and a signal that is opposite in phase to the signal set at the voltage output terminal is output. A second depletion type MOS (MOS) transistor to which the voltage is applied, and one end of which is connected to the first MOS transistor. Second
A third depletion type MOS transistor connected to the other end connection point of the transistor (MOS) transistor, and a third depletion type MOS transistor whose other end and dart are connected to the voltage output end. (2) The voltage switching circuit according to claim 1, wherein the voltage applied to the first voltage application terminal is larger than the voltage applied to the second voltage application terminal.