JPS59178698A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To take out relief information from a chip itself easily by forming a regular memory cell and a stand-by memory cell so that correspondance relation between data and data output are different between these memory cells. CONSTITUTION:Connection relation between bit lines 71 and 72 of a row of regular memory cells and data input/output lines 41 and 42 are opposite to those between bit lines 73 and 74 of a row of stand-by memory cells and data input/ output lines 42 and 41. Therefore, when data are read out successively in the state where all cells are ''0'' by initialization, data output 111000- is obtained in accordance with memory cells 61-66 in the row of stand-by memory cells though regular data output 000111 should be obtained in accordance with memory cells 51-56 in the row of regular memory cells, and the regularity of data output from regular memory cells is disturbed. Thus, it can be discriminated that the row of regular memory cells is substituted with the row of stand-by memory cells and the substituted row can be discriminated by the address input where the substituted data output is generated. Consequently, the relief information is taken out from the chip itself by the normal read.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to a large-capacity semiconductor memory having a redundant circuit.

[Technical background of the invention]

Redundant circuit technology has become essential as semiconductor memory becomes thicker. Redundant circuits in semiconductor memory are:
A spare column or row of memory cells is added to a regular memory array, and a spare decoder is provided to select this spare column or row. By this, if a defective column, defective row, or defective bit exists in the regular memory array, the address corresponding to the defective column, defective row, or defective bit is programmed into the preliminary decoder by appropriate means. ,
By using a redundant circuit, it becomes possible to replace a defective row or a defective row with a spare column or row, thereby relieving a defective chip.

Such redundant circuits include 16 KSRAM (static random access memory), 64KdRAM (
Dynamic RAM) was introduced in earnest, and 64KS
For large-capacity memories such as RAM and 256 dRAM, this technology is considered essential for improving chip yield and reducing memory costs.

[Problems with background technology]

By the way, if we introduce redundant circuit technology as mentioned above,
When evaluating and testing memory, it is often necessary to know memory rescue information, i.e., whether redundant circuitry is used and, if so, which addresses in the regular memory array are defective columns or rows being replaced. happen.

Therefore, it is conceivable to store the above-mentioned relief information for each chip in a tester etc. at the stage of chip testing, but this is completely impractical when the number of test chips is extremely large, and it is difficult to save from the assembly process. is also close to impossible. In contrast, there is a technology that incorporates a special function into a memory chip and extracts rescue information from the chip itself, as described in "Nikkei Electronics J, 1,982, No. 8.2.
It is disclosed on pages 183-189. Here, 10-1 call function 1 is shown in which when +IOV is applied to the data input bin, the data output becomes 111 for the address input corresponding to the replaced defective column. The specific structure is unknown. However, in order to realize the above-mentioned special functions, it is assumed that a new special circuit for this function will be required within the chip, which will inevitably increase the chip area and make the circuit more complex. .

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and can be performed without applying a special control signal or high voltage from the outside.
In addition, without providing a special circuit for generating relief information inside the chip, the relief information (
The present invention provides a semiconductor memory device in which information such as whether a redundant circuit is used or not and which defective column or row has been repaired can be easily extracted from the chip itself.

[Summary of the invention]

That is, in the semiconductor memory device of the present invention, the read data from the memory cells after power is turned on and initialized has the regularity of the data output from the memory cell group belonging to the regular row or column to the spare column or column. In order to create a relationship in which data output from a memory cell group belonging to a row is disturbed, the correspondence relationship between data and data output from a memory cell group belonging to a spare column or row is changed to a normal relationship between data output from a memory cell group belonging to a spare column or row. This is characterized in that the correspondence between data and data output is made different.

Therefore, relief information can be easily generated from the chip itself by normal reading without applying special control signals or high voltages to the memory chip from the outside, and without providing a special circuit for generating relief information inside the chip. It is possible to take it out.

[Embodiments of the invention]

First, the operating principle of the present invention will be explained. A semiconductor memory having a redundant circuit is configured such that when the memory is initialized, approximately fixed data is stored in each memory cell.

An obvious example is a dRAM using a one-transistor, one-carrier, 1,000-shita type memory cell. Since the storage node of this memory cell always has a diffusion layer, before the power is turned on, it is at the substrate level, that is, all cells accumulate data I□W.
This does not change even if the power is turned on and initialized.

It should be noted here that the cell data and successive data output generally do not match. The relationship between cell data and data output has a certain correspondence determined by geometric factors such as the A' turn layout on the chip. therefore,
In the case where all cells in the above example have data "0", if data is read from all cells immediately after initialization, a regular data map determined from the correspondence relationship can be obtained.

In the present invention, the above-mentioned correspondence relationship is made different in the spare columns or rows than in the columns or rows of the well-known memory array. Spare columns or rows are connected differently from regular columns or rows, perhaps due to the relationship between cell data and data output. With this configuration, if reading is performed sequentially from the state where the gold cells are data W01 after initialization, the regularity of data output will be disrupted when an address corresponding to a defective column or row is input. Therefore, relief information can be easily obtained.

Hereinafter, as a first embodiment of the present invention, a part of a semiconductor memory having a memory cell group serving as a spare column for a regular memory array will be explained with reference to FIG. That is, in FIG. 1, 11 to 16 are word lines, 7 and 72 are a pair of bit lines in the regular memory array, and 51 to 56 are some memory cells in the regular memory array, and the word lines 11 and 72 are a pair of bit lines in the regular memory array. ~16 and bit lines 71.72. 21 is a sense amplifier connected to the bit line 71.72, 41 and 42 are a pair of data input/output (Ilo, fit reading/reading) lines, and B1 and B2 are the pair of data input/output lines 41.42. 31 between the pair of bits ff1171 and 72, respectively.
The 2H bit line selection transistor 31 is a regular column decoder for selecting the pair of bit lines 71 and 72, and its output is applied to the gates of the bit line selection transistors B, , B. .

On the other hand, 73 and 74 are bit lines υ that serve as spare columns.
6 to 66 are spare memory cells, which are connected to the word line 1.
1 to 16 and the above-mentioned spare bit lines 73 and 74. 22 is a spare sense amplifier connected to the spare bit line 73, 74, B3 and B4 are transistors for selecting a spare bit line, and 32 is a spare column decoder whose decoded output selects the spare bit line. The input signal is applied to the gates of the transistors B, . In this case, one bit line selection transistor B3 is connected between the spare bit line 73 and the data input/output line 42, and the other bit line selection transistor B,
is connected between the spare bit line 74 and the data input/output line 41. What should be considered here is the connection between the bit lines 71 and '72 of the regular column and the data input/output lines 41 and 42. Compared to the relationship, the connection relationship between the bit lines 73, 74 and the data input/output lines 42, 41 of the spare column is different (reversed), and this different part is indicated by the dotted line in the figure. It is shown enclosed.

In the memory shown in FIG. 1, if the data on the data input/output line 4 and the read data output D (or TJIT) are configured to match, for example, the data on one data input/output line 4 is “11”, the data output D
C) (When JT is 111 and the data on the other data input/output line 42 is oW, the data output D OUT becomes 01 forever.

Of the memory cells 51 to 56 in the regular column, the data in the memory cells 51 to 53 connected to the bit line 7 corresponding to the data input/output line 4 matches the data output DOUT at the time of reading, The data of the memory cells 54 to 56 connected to the bit line 72 corresponding to the data input/output line 42 is the inverse of the data output D OUT at the time of subsequent output. On the other hand, the connection relationship between the spare bit lines 73.74 and the data input/output lines 42.41 is reversed from the connection relationship in the normal column described above, so that Data and data output D when reading it
The correspondence relationship with OUT is reversed from the correspondence relationship with the normal sequence described above.

Also, in the example, if the normal memory cell 51 is defective,
The spare column decoder 3 decodes the address data of the column address corresponding to the defective column to which this defective cell belongs.
Assuming that the normal column has been replaced by programming 2, the spare memory cell 61 is selected in place of the defective cell when the address corresponding to the defective cell is input.

Therefore, when data is read out in order from a state where all cells have data of 10 degrees due to initialization, memory cells in regular columns...51, 52, 53, 54 degrees, 55, 56-
Corresponding to...Qi, WQW, fQW, lQ
f.

“1°,” “1” wlw, ... where there should be regular data output, memory cells in the spare column...61°6
2. Corresponding to 63, 64, 65.66...I
ll, Ill, IIF, IQI, IQ
This results in data outputs of I, WQI, . . . and disturbs the regularity of data output from normal memory cells. This makes it possible to determine which column has been replaced by a spare column and from the address input from which this replaced data output occurs.

Therefore, according to the semiconductor memory of the above embodiment, the spare column can be activated without applying a special control signal or high voltage from the outside to the memory chip, and without providing a special circuit for generating relief information inside the chip. By simply changing the connections between the bit lines and the data input/output lines compared to the regular columns, it becomes possible to easily extract relief information from the chip itself through normal reading.

Next, as a second embodiment of the present invention, a part of a semiconductor memory having a memory cell group serving as a spare row for a regular memory array will be described with reference to FIG. That is, in FIG. 2, 11 to 16 are normal row word lines, 71, 72,
75 and 76 are connected to pit lines 71 and word lines 11, 13.15, respectively, and memory cells 54 to 56 are connected to pit lines 72 and word lines 12, 14.16, respectively. Cells 81-83 are pit line 75 and word line 1
1, 13.15, respectively, and memory arrays 84-86 are connected to bit line 76 and word line 12, 14.16, respectively.
and are connected to each other correspondingly. A sense amplifier 23 connected to the pair of bit lines yx and v2 is a sense amplifier connected to the pair of pit lines 75 and 76. BI+B2+B5+B is a pit line selection transistor, and transistor B++B! are respectively connected between the pair of pit lines 71, 72 and the pair of data input/output lines 41, 42, and transistors B, , B are connected between the pair of bit lines 75, 76 and the data input/output lines 41, 42, respectively. line 41
．． 42, respectively. 31 is a column decoder for selecting the pair of transistors BI and B2; 33 is a column decoder for selecting the pair of transistors Bs and B2;
It is a column decoder for selecting a. 101-10
3 is a row decoder, W, to W6 are word line selection transistors, and the output terminal of the row decoder 101 and the word line z1. x2 and transistors W1 and W corresponding to each other.
2 are connected to the row decoder 102 and the word line 13.14.
Transistors W, . . . W4 are connected between the row decoder 103 and the word line 15.16, and transistors W, . . . W6 are connected between the row decoder 103 and the word line 15. Of the word line selection transistors W, to W6, the transistors w,,w,.

W, is selected by the row address signal Ao, and transistors W, , W, , W, are selected by the row address signal Ao.

On the other hand, 17 and 18 are word lines of 4 isi rows, 60
-70 are spare memory cells, and memory cell 67 is connected to word line 17 and pit line 71, and memory cell 67 is connected to word line 17 and pit line 71.
8 is connected to the word line 18 and the bit line 72, the memory cell 69 is connected to the word line 17 and the pit line 75,
Memory cell 0 is connected to word line 18 and bit line 76. Reference numeral 11 designates a spare row decoder whose output serves as a decoding inhibit input to the above-mentioned row decoders 101 to 103. W.

is connected between the output terminal of the spare row decoder 11 and the spare word line 17, and the row address signal A. A transistor W8 selected by the row address signal A is connected between the output terminal of the spare row decoder 111 and the spare word line 18. The transistor selected by What should be noted here is that word line 1 of the regular row
1, 13. Regular memory cells connected to 15 (5
1,81), (5,?, s 2), (5s,
g, 9) is connected to the pin F bag 71 + 75, but the same row address signal A as the upper N2 word line 11.13.15. The spare memory cells 6B and 70 connected to the word line 18 of the spare row selected by be. Similarly, pressurized memory cells (54, 84) are connected to the word lines 12, 14, 16 of the regular row.

(ss, as), (se, se) are bit lines 72
76, but the word line 12°14.
fB% 71 + 75 has been criticized.

Furthermore, 19 and 20 are dummy word lines, and 91
94 are dummy cells, and the dummy cell 91 is connected to the dummy word line 19 and the bit line 71.
2 is connected to the dummy word line 20 and the bit line 72,
Dummy cell 93 is connected to dummy word line 19 and bit line 75 , and dummy cell 94 is connected to dummy word line 20 and bit line 76 . Further, dummy word line selection circuits 112 and 113 each include an exclusive OR circuit, each of which receives the decoded output of the spare row decoder 111 as one input, and also receives the row address signal A correspondingly. , Ao are the other inputs.

Therefore, when the decoded output of the spare row decoder 111 is not generated, the row address signals Ao and Ao are used to respectively correspond to the dummy word line selection circuits 113 and 112.
is selected and the decoded output of the spare row decoder 111 is generated, contrary to the above, the row address signal A is generated.

,A.

Dummy word line selection circuit 113゜11 corresponding to each
Choice 2 is now prohibited. Therefore, positive return,
When one of the word lines 11 to 16 in the row is selected, the dummy cell connected to the bit line that pairs with the bit line to which the selected regular memory cell is connected is connected to the dummy word line selection circuit. 112 or 113. Similarly, the spare word line 17°18
If one of them is selected, the dummy word line selection circuit 112 or 113 selects the dummy cell connected to the bit line that is paired with the bit line to which the selected spare memory cell is connected. It looks like this.

Note that the portion surrounded by a dotted line in FIG. 2 has a different structure from that of a conventional memory.

For example, if the row belonging to the regular row decoder 101 is defective and has been replaced with a spare row, for example, when the spare memory cell 68 is selected instead of the regular memory cell 51, at the same time Dummy cell 9 is selected instead of dummy cell 92. Finally, when a regular row is replaced, the replaced regular memory cell and the selected spare memory cell are connected to opposite sides of the bit line pair.
In other words, the normal memory cell and the spare memory cell are reversely connected to the data input/output lines 41 and 42. Therefore, if data is read out in order from the state where the data of all cells is wol, the normal row memory cell 51゜54.81.84
Corresponding to IQI, 814, WQI.

"1' and where there should be regular data output, corresponding to memory cells 67.6B and 69.70 of the spare row, TE"
1'','``O'',``1'',``O'' tD cheater output does not disturb the data output from the normal memory cells, and the presence or absence of replacement and the replacement row address can be easily determined.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, in order to know whether or not a redundant circuit is used and the address of a replaced row or column, no special control signal or high voltage is required from the outside. Furthermore, no special control circuitry is required within the chip; all that is required is a simple connection change within the chip or the addition of a logic circuit, and relief information can be extracted from the chip itself through normal electrical tests. .

Therefore, it is extremely practical and extremely effective in evaluating and testing memories using redundant circuit technology.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a main part of one embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram showing a main part of another embodiment. 11-16...Word lines of regular rows, 17.18...
Pre(it# row word line, 19.20...dummy word line, 41.42...data input/output line, 51~56°81~86...regular memory cell, 61~66...・
Spare memory cell, 71, 72.75, 76... Regular bit line, 73.74... Spare bit line, 91~
94...Dummy cell, Bl~B,, W, ~W,...
transistor.

Claims (2)

[Claims] (1) There is a memory cell in a spare column or row for the regular memory array, and the correspondence between the data of the spare memory cell and the data output is different from the correspondence between the data of the regular memory cell and the data output. A semiconductor memory device characterized in that it is formed differently. (2) Compared to the connection relationship between the pit line pair connected to the regular memory cell and the pair of data output lines, the connection relationship between the bit line pair connected to the spare memory cell and the pair of data output lines is A patent arrangement characterized in that the connection relationship of is reversed.