JPS5917742A - Selective call receiving device - Google Patents

Abstract

PURPOSE:To make a high-efficiency call possible without changing all circuits, by inputting a frame control signal to collate all frames and switching the device so that only specific frames are collated when the frame control signal is absent. CONSTITUTION:An NRZ transmission signal is constituted with a timing signal (preamble signal PA), a signal (synchronizing signal b) for timing of frames, and frames (F1-F8), and a frame number is stored together with the individual number in a 3-bit register of a number storage circuit 20. When frames F1-F8 are selected, a timing signal P is generated from a number signal generating circuit 19 to the circuit 20, and a frame number signal corresponding to the frame to be selected is transmitted to a frame discriminating circuit 26. This frame number signal is applied to a frame number generating circuit 27, and a pulse corresponding to the frame number is applied to a frame bit timing circuit 12, and all frames F1-F8 are collated by a collating circuit 11, thus making the high-efficiency call possible.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a selective call receiving device with improved call efficiency.

Figure 1 shows an example of the configuration of a conventional NRZ transmission signal, in which a timing signal a (hereinafter referred to as a preamble signal) for adjusting the phase between the clock in the decoder and the transmission signal is 576 bits per frame. The timing signal B (hereinafter referred to as the synchronization signal) is 32 bits, the individual call signal and the message signal C are each 32 bits, and a total of 64 bits constitutes one frame number and eight frames. Send the repetition as a block. Taking this case as an example, a conventional decoder will be explained according to FIG.

In the figure, 5 is an antenna, 6 is a radio section, 7 is a bit synchronization circuit, 8 is an oscillation circuit, 9 is a frequency dividing circuit, and 10 is a tie ε
11 is a matching circuit, 12 is a frame phase adjustment circuit, and 12 is a frame phase adjustment circuit.
A bit timing circuit, 13 is a preamble generation circuit, 14 is a preamble flag circuit, 15 is a synchronization generation circuit, 16 is a timer, 17 is an AN
D circuit, 18 is a synchronization flag circuit, 19 is a number signal generation circuit, 20 is a number storage circuit, 21 is an AND circuit, 22 is a sound generation circuit, 23 is a speaker, 24 is a display control circuit, 25 is a display element, 26 is a frame identification circuit.

Next, the operation of this decoder will be explained.

The transmitted NRZ signal d shown in FIG. 1 is taken in by the radio unit 6 via the amplifier 6, converted and detected, and input to the hint synchronization circuit 7 manually. On the other hand, the clock e is inputted to the timing/phase adjustment circuit 10 through the oscillation circuit 82 and the frequency division (b) path 9. In the timing/phase adjustment circuit 10 and the H/1/synchronization circuit 7, the internal clock e in the decoder is
In order to adjust the phase of the NRZ signal d and the NRZ signal d, a correction pulse is output to correct the internal clock.

The bit-synchronized NRZ signals are sequentially sent to the matching circuit 11. The bit synchronized signal from the timing/phase adjustment circuit 10 is sent to the frame/bit timing circuit 1.
2, which drives the preamble signal generation circuit 13 and sends out a pattern identical to the transmission glial/glue signal pattern to the collation circuit 11. When the matching circuit 11 matches the green pattern, the preamble flag circuit 14 sends the HJ signal. , by driving the frame bit timing circuit 12, drives the synchronization signal generation U'v,l path 15 in which the same pattern as the transmission synchronization signal is stored, sends the pattern to the matching circuit 11, and also outputs the synchronization signal from the timer. Start timer 16. Timer 16 is
Preamplifier iris + (synchronization signal + 8 frames) x 2
After running the length of L-, reset the preamble flag circuit R i (No. 8, hereafter Preamble Noraku I!7) circuit becomes J' HJ and reset the preamble flag circuit from -C. (This is referred to as preamble holding.) The AND circuit 17 is a two-manual AND gate, and under the condition of preamble holding, the output of the AND circuit 17 becomes 1-H. If preamble retention has ended, subsequent verification d: is completely meaningless even if synchronous verification is performed. Next, when the output 1'-H of the AND circuit is input to the synchronization flag circuit 18, an "H" signal is output and latched. When the synchronization flag circuit 18 outputs [HJ, the frame bit timing circuit 12 is driven, thereby driving the number signal generation circuit 19.

When the number signal generation circuit 19 is driven, the number storage circuit 20 (for example, F
ROM) is driven, the call number is read out, and the call number is sent to the verification circuit 11. It's a moat, synchronization flag circuit 18 rH
The J output uses a timer circuit in the same way as preamble retention.
After counting the length of (synchronization signal→-8 frames) x2, the synchronization control circuit 18 is reset. (R2 (Word.

Hereinafter, the period from when the synchronization flag circuit becomes [HJ] to when the synchronization Noraku circuit is reset will be referred to as synchronization maintenance. ) When the calling number is verified, "H" is output to the AND2 circuit 21. The AND2 circuit 21 is a two-man powered AND gate, and under the condition of maintaining synchronization, the output of the AND2 circuit 21 or [HJ
This drives the sound generation circuit 22 and drives the sounding body 23 (for example, a speaker) with a predetermined sound pattern. On this occasion,
For example, in the case of a transmission method in which display data is provided in the latter 32 bits of each frame by providing a display control circuit 24 and a display element 25, etc., which are composed of a microcomputer, etc., the display element It is also possible to display the number by 25 (location number, menu). Which frame the calling number belongs to is stored in advance in a part of the number storage circuit 2o, and the number signal generation circuit 19 always drives a part of the number storage circuit 20, and this is stored in the frame identification circuit 26. It is read and sent to frame bit timing circuit 12 to determine which frame to power drive.

In other words, in the conventional (g-transmission method/decoding method), the frame position of the call is fixed, so if the same frame is suddenly flooded with calls, for example, if the frame is composed of 8 frames, one of the 8 frames Since the same frame can be used only once compared to the number of repetitions, there is a drawback that a large number of calls cannot be processed at once, resulting in a large amount of waiting time and poor call efficiency.

The present invention eliminates the above-mentioned drawbacks of the conventional art, and the present invention will now be described by way of an embodiment with reference to drawings. In FIG. 4, 27 is a frame number generation circuit, and 28 is an input terminal for a frame control signal whose voltage is pulled down by a resistor and inputted via a switch. The same reference numerals as in other FIG. 2 represent the same names.

Next, the operation of this embodiment will be explained. For example, when the frame is composed of eight frames (F1 to Fs) as shown in Figure 5A, the memory circuit 20 (usually FROM) stores the individual number as well as the frame number in a 3-bit register. It is stored. Therefore, for example, when selecting the individual number of the sixth frame F5, first, when the number signal generation circuit 19 issues the tying signal P to the number storage circuit 2Q, three hints corresponding to the frame F5 are selected. A frame number signal "1o1" q is sent to the frame identification (b) path 26. At this time, as shown in FIG. 6, the frame number signal A that has passed through the frame identification circuit 26 is outputted as a pulse to the frame bit timing circuit 12 only for frame F5 through the frame number generation circuit 27, as shown at the beginning of the figure. The input signal is accepted only at this timing. However, when the frame control terminal 28 is selected to the rHJ side, the frame number generation circuit 2
The output of 7 becomes "HJ" at all timings, and all frames are selected.

As explained above, according to the present invention, all frames can be fully verified by inputting a frame control signal, and in the absence of the frame control signal, it is possible to switch to verifying only a specific frame. Therefore, especially when used in a case where there are many paging trunks, it has the advantage of being able to perform highly efficient paging without changing the circuit, and its industrial value is significant.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the structure of a signal used in a conventional selective call receiving device, and FIG. 2 is a block diagram showing its circuit structure.
FIG. 3 is an explanatory diagram showing the structure of a signal used in a selective call receiving device according to an embodiment of the present invention, FIG. 4 is a block diagram showing its circuit structure, and FIGS. 5 and 6 are for explaining its operation. FIG. 2 is a signal configuration example and a waveform diagram. 12... Frame bit timing circuit, 20
...Number storage circuit, 26...Frame identification circuit, 27...Frame number generation circuit, 28...
・Frame control signal input terminal. Name of agent Patent attorney Toshio Nakao and 1 other person2

Claims (1)

[Claims] a decoder for receiving a selective calling signal consisting of a preamble signal, a synchronization signal, and individual signals of a plurality of frames;
a storage means for storing a frame number unique to the decoder; a room identification circuit for identifying the frame number when reading the frame number; and a room identification circuit for identifying the frame number when reading the frame number; and a frame number generation circuit that outputs a selection signal, and when a frame control signal is input to the frame number generation circuit,
A selective call receiving device characterized in that it selects all frames while ignoring its own frame number.