JPS5917669U - High-speed facsimile encoding device - Google Patents

High-speed facsimile encoding device

Info

Publication number
JPS5917669U
JPS5917669U JP11101182U JP11101182U JPS5917669U JP S5917669 U JPS5917669 U JP S5917669U JP 11101182 U JP11101182 U JP 11101182U JP 11101182 U JP11101182 U JP 11101182U JP S5917669 U JPS5917669 U JP S5917669U
Authority
JP
Japan
Prior art keywords
encoding device
speed facsimile
facsimile encoding
addresses
displaying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11101182U
Other languages
Japanese (ja)
Inventor
正明 滝沢
宏 吉木
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP11101182U priority Critical patent/JPS5917669U/en
Publication of JPS5917669U publication Critical patent/JPS5917669U/en
Pending legal-status Critical Current

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案の一実施例の高速ファクシミリの符号器のブ
ロック図である。 1・・・原稿、2・・・レンズ、3・・・センサ、4・
・・2直化回路、5・・・シリアル/パラレル変換回路
、6・・・汎用処理装置、7・・・DMAC,$・・・
ラインメモリ、9・・・リードオンリメモリ、10・・
・ランダムアクセスメモリ、11.12・・・8画素単
位変化点検出回路、13.14・・・8画素内変化点検
出回路、15゜16.23・・・■0ボート、17・・
・バッファメモリ、18・・・モデム、19・・・伝送
路、20.21・・・DFF、22・・・減算回路。
The figure is a block diagram of a high-speed facsimile encoder according to an embodiment of the present invention. 1... Original, 2... Lens, 3... Sensor, 4...
... 2-serial converter circuit, 5... Serial/parallel conversion circuit, 6... General-purpose processing device, 7... DMAC, $...
Line memory, 9... Read only memory, 10...
・Random access memory, 11.12... 8 pixel unit change point detection circuit, 13.14... 8 pixel internal change point detection circuit, 15° 16.23...■0 boat, 17...
- Buffer memory, 18...Modem, 19...Transmission line, 20.21...DFF, 22...Subtraction circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 少なくとも2種類の変化点のアドレスを表示す、る装置
と、そのアドレス間の差を表示する装置とを具備するこ
とを特徴とする高速ファクシミリの符号化装置。
1. A high-speed facsimile encoding device comprising: a device for displaying addresses of at least two types of change points; and a device for displaying a difference between the addresses.
JP11101182U 1982-07-23 1982-07-23 High-speed facsimile encoding device Pending JPS5917669U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11101182U JPS5917669U (en) 1982-07-23 1982-07-23 High-speed facsimile encoding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11101182U JPS5917669U (en) 1982-07-23 1982-07-23 High-speed facsimile encoding device

Publications (1)

Publication Number Publication Date
JPS5917669U true JPS5917669U (en) 1984-02-02

Family

ID=30257945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11101182U Pending JPS5917669U (en) 1982-07-23 1982-07-23 High-speed facsimile encoding device

Country Status (1)

Country Link
JP (1) JPS5917669U (en)

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