JPS5917645A - Method of test interface - Google Patents
Method of test interfaceInfo
- Publication number
- JPS5917645A JPS5917645A JP57127989A JP12798982A JPS5917645A JP S5917645 A JPS5917645 A JP S5917645A JP 57127989 A JP57127989 A JP 57127989A JP 12798982 A JP12798982 A JP 12798982A JP S5917645 A JPS5917645 A JP S5917645A
- Authority
- JP
- Japan
- Prior art keywords
- test
- controlled device
- state
- connectors
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は制御装置と被制御装置は複数対の制御線にて接
続されており、該被制御装置のテストをする場合は該複
数の制御線の各々にマルチ接続されたテスト情報線及び
該各々のテスト情報線を介してテスト情報を送るための
スリーステート制御可能なドライバのスリーステート情
報線を咳被制御装置とテスト装置間で複数のマルチコネ
クタで接続し、該被制御装置より該テスト装置内の各々
のスリーステート制御可能なドライバへスリーステート
制御情報を送るシステムに係り、該複数のマルチコネク
タの一部の接続忘れの時はテスト不能とするテストイン
タフェイス方式。Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a control device and a controlled device connected by a plurality of pairs of control lines, and when testing the controlled device, A plurality of test information lines are connected to each of the test information lines, and a three-state information line of a three-state controllable driver for sending test information through each of the test information lines is connected between the controlled device and the test device. Regarding a system that connects with multi-connectors and sends three-state control information from the controlled device to each three-state controllable driver in the test equipment, if you forget to connect some of the plurality of multi-connectors, perform a test. Test interface method that makes it impossible.
伽）従来技術と問題点
第１図は従来例の制御装置及び被制御装置及びテスト装
置間の回路のブロック図である◎図中１．１，１，３，
３．８ はスリーステート制御可能なドライバ（以下
ドライバと称す）、２Ｉ２．２ はレシーバ、４はイ
ンバータ、５＋６＋７はマルチコネクタ、８は制御装置
、９は被制御装置、１０はテスト装置、Ｒ，Ｒ１は抵抗
、十ｖ１゜十ｖ、は正の直流電圧、ＳＷはスイッチ、１
１゜１１．１１ は制御線、１２．１２ 、１２
はテスト情報線、１３はスリーステート情報線を示す。佽）Prior art and problems Figure 1 is a block diagram of a circuit between a control device, a controlled device, and a test device in a conventional example. ◎1.1, 1, 3,
3.8 is a three-state controllable driver (hereinafter referred to as driver), 2I2.2 is a receiver, 4 is an inverter, 5+6+7 is a multi-connector, 8 is a control device, 9 is a controlled device, 10 is a test device, R, R1 is a resistor, 10v1゜10v is a positive DC voltage, SW is a switch, 1
1゜11.11 is the control line, 12.12, 12
13 indicates a test information line, and 13 indicates a three-state information line.
又制御装置８のドライバ１．１．１ は能動状態にな
っており、制御装置８よりの制御指令はドライバ１．１
．１ 及び制御ｉｌｌ、１１．１１ を介Ｌ７被制御
装置９のレシーバ２．２．２ に送られている０同第
１図の場合は制御線が３つの場合の例を示しておりもっ
と多い場合も同様の動作をする０今被制御装置９のテス
トを行う場合は、マルチコネクタ５．６．７を接続して
、制御線１１゜るようにし、スイッチＳＷをオンとして
、ドライバ１．ｉ、ｔ＋ハイインピーダンスとし、ドラ
イバ３．３．３ を能動状態とし、テスト情報をドラ
イバ３，３，３．テスト情報線１２，１２．１２を介し
てレシーバ２．２．２ に送りテストを行う０尚ドラ
イバ１，１．１ はスイッチＳＷがオフの時はスリー
ステート状態を制御する端子には正の直流電圧十Ｖ、よ
り抵抗Ｒを介してＨレベルが加わっていて能動状態とな
っており、又ドライバ３，３．３ は正の直流電圧十
Ｖ３より抵抗Ｒ。Also, the driver 1.1.1 of the control device 8 is in an active state, and the control command from the control device 8 is transmitted to the driver 1.1.
．． 1 and control ill, 11.11 are sent to the receiver 2.2.2 of the L7 controlled device 9.0 Figure 1 shows an example where there are three control lines, but if there are more If you want to test the controlled device 9, connect the multi-connector 5, 6, 7 so that the control line 11 is connected, turn on the switch SW, and connect the driver 1. i, t+ high impedance, driver 3.3.3 is in active state, and test information is set to driver 3, 3, 3. The test information is sent to the receiver 2.2.2 via the test information lines 12, 12.12 for testing. Furthermore, when the switch SW is off, the driver 1, 1.1 has a positive DC current at the terminal that controls the three-state state. The voltage is 10V, and the H level is applied through the resistor R, making it active, and the drivers 3 and 3.3 are connected to the positive DC voltage 10V and the resistor R is applied.
及びインバータ４を介しスリーステート状態を制御する
端子にはＬレベルが加わっていて、ノ１イインピーダン
スの状態となっている。以上の状態でテストを行うが、
この場合例えばマルチコネクタ６の接続を忘れたとする
と、レシーバ２′の出力はＨレベルのままとなし、他の
レシーバ２．２にはテスト情報が送られ語ったテストが
行なわれることになる。このような欠点を第１図のシス
テムでは持っている口
（０） 発明の目的
本発明の目的は上記の欠点をなくするために、マルチコ
ネクタが全部接続状態になければ被制御装置のテストを
行なえなくシ、ｖ４りたテストを行なわないテストイン
タフェイス方式の提供に表るＯ３−
（ｄ） 発明の構成
本発明は上記の目的を達成するために、テストの場合、
テスト装置のドライバを能動状態とする接続されるよう
にし、どれかのマルチコネクタが接続されていなけれは
テスト装置の全てのドライバは能動状態でなくハイイン
ピーダンスの状態で、テスト情報が全部被制御装置に送
られなくしたことを特徴とする〇
（ｅ） 発明の実施例
以″Ｆ本発明の一実施例につき図に従って説明する。第
２図は本発明の実施例の制御装置及び被制御装置及びテ
スト装置間の回路のブロック図で制御縁が３つの場合の
例でおる。The L level is applied to the terminal for controlling the three-state state via the inverter 4, and the impedance is zero. The test will be conducted under the above conditions, but
In this case, for example, if one forgets to connect the multi-connector 6, the output of the receiver 2' remains at the H level, test information is sent to the other receivers 2.2, and the aforementioned test is performed. The system shown in Fig. 1 has such drawbacks (0).Objective of the InventionThe purpose of the present invention is to eliminate the above-mentioned drawbacks by making it difficult to test the controlled device unless all the multi-connectors are connected. (d) Structure of the Invention In order to achieve the above object, the present invention provides, in the case of testing,
Set the test equipment driver to active state.If any multi-connector is not connected, all the test equipment drivers are not active and are in a high impedance state, and all test information is transferred to the controlled device. 〇(e) Embodiment of the Invention From ``F'' An embodiment of the present invention will be explained according to the drawings. Fig. 2 shows a control device, a controlled device, and a controlled device according to an embodiment of the present invention. This is an example of a block diagram of a circuit between test devices in which there are three control edges.
図中第１図と同一機能のものは同一記号で示す、５．６
．７ はマルチコネクタ、９ ｋ′ｉ被制御装置、１
０ ｔ／ｉテスト装置、１４は発光素子、ＳＷＩはスイ
ッチ、十Ｖ１１／ｉ正の直流電圧、ＲＬはリレー、ｖ／
はリレーＲＬの接点を示す。Items with the same functions as those in Figure 1 are indicated by the same symbols. 5.6
．． 7 is a multi-connector, 9 k′i controlled device, 1
0 t/i test equipment, 14 is a light emitting element, SWI is a switch, 11V11/i positive DC voltage, RL is a relay, v/
indicates the contact point of relay RL.
４−
第２図で第１図と異なる点はスリーステート情＠線１３
がマルチコネクタｂ のイ点及びマルチコネクタ６０口
点及びマルチコネクタ７ のへ点にて、テスト装置１０
＠と被制御装置θ 側と接続されており、 ｆＡｌえ
はマルチコネクタ６ が接続状態にない場合はスイッチ
ＳＷＩをオン（テスト状態）としでもインバータ４の入
力はアースとならずドライバ３．Ｂ、３ｄハイインピー
ダンスのままで能動状態とならない点と、スイッチＳＷ
１をオンとした時全てのマルチコネクタが接続状態でお
れば１ル−ＲＬが動作し、この接点ｒｅがオンとなり発
光素子１４を発光さす点である。4- The difference in Figure 2 from Figure 1 is the three-state information @line 13
is the test device 10 at the A point of the multi-connector b, the multi-connector 60 port point, and the e-point of the multi-connector 7.
@ is connected to the controlled device θ side, and if the multi-connector 6 is not connected, the input of the inverter 4 will not be grounded even if the switch SWI is turned on (test state), and the driver 3. B, 3d remains high impedance and does not become active, and switch SW
If all the multi-connectors are in the connected state when 1 is turned on, 1-RL is activated, and this contact re is turned on, causing the light emitting element 14 to emit light.
他の動作Ｆｉｍ１図の場合と同様である・従って被制御
装置９ のテストを行う場合マルチコネクタ５ ＊６
＊７ が接続されておれば、スイッチ８Ｗ１をオンとす
ることで第１図の場合と同様の動作でテストすることが
出来る。尚この場合はリレーＲＬが動作し、発光素子１
４を発光させ全てのマルチコネクタが接続状態であるこ
とが判る。今ガ番げマル手コ十／ＩＡＱ ｔ７′１憔
１古ｒ−亡お１Ｌ謙り１ドライバ３，３．３ はハイ
インピーダンスのままで能動状態とならず全てのテスト
情報は被制御装置９′に送られないのでテストは不態に
なり誤ったテストを行なうことはない。面この場合は発
光素子１４は発光せずどれかのマルチコネクタが接続状
態にないことが判る。It is the same as the case of other operation Fim1 diagrams. Therefore, when testing the controlled device 9, the multi-connector 5 *6
*7 If it is connected, by turning on the switch 8W1, the test can be performed in the same manner as in the case of Fig. 1. In this case, relay RL operates and light emitting element 1
4 lights up, and it can be seen that all the multi-connectors are connected. Imabange Maruteko 10/IAQ t7'1 1 old r-1L low 1 driver 3, 3.3 remains at high impedance and does not become active and all test information is transmitted to the controlled device 9 Since the test is not sent to ``, the test will not be erroneous and the test will not be performed incorrectly. In this case, the light emitting element 14 does not emit light, indicating that one of the multi-connectors is not connected.
（ｆ） 発明の効果
以上詳細に説明せる如く本発明によれば、被制御装置を
テストする場合どれかのマルチコネクタの接続を忘れた
場合はテストが出来ず誤ったテストをすることがなくな
る効果がある。(f) Effects of the Invention As explained in detail above, according to the present invention, when testing a controlled device, if you forget to connect one of the multi-connectors, you will not be able to perform the test and you will not be able to perform an incorrect test. There is.
Ｍ１図は従来例の制御装置及び被制御装置及びテスト装
置間の回路のブロック図、第２図は本発明の実施例の制
御装置及び被制御装置及びテスト装置間の回路のブロッ
ク図である。
図中１．１．１ ．３，３．３ はスリーステート制
御可能なドライバ、２．２ 、２ はレシーバ、４は
インバータ、５．５．６，６ 、’ｉ、’ｌ はマルチ
コネクタ、８は制御装置、９．９は被制御装置、１０、
１０ はテスト装置、１１．１１ 、１１ ！ｉ′ｉ
制御線、１２，１２．１２ はテスト情報線、１３は
スリーステート情報線、１４１’を発光素子、ＳＷ。
ＳＷＩはスイツチ、ＲＬはリレー、ｒｌはリレーＲＬの
接点、ＲＩＲ，は抵抗、＋Ｖ１ ＋ 十Ｖ＠ ＋ 十Ｖ
ｓは正の直流電圧を示す。FIG. M1 is a block diagram of a circuit between a control device, a controlled device, and a test device in a conventional example, and FIG. 2 is a block diagram of a circuit between a control device, a controlled device, and a test device in an embodiment of the present invention. 1.1.1 in the figure. 3, 3.3 are three-state controllable drivers, 2.2, 2 are receivers, 4 are inverters, 5.5.6, 6, 'i, 'l are multi-connectors, 8 is a control device, 9.9 is a controlled device, 10,
10 is the test equipment, 11.11, 11! i′i
12 is a control line, 12 is a test information line, 13 is a three-state information line, and 141' is a light emitting element, SW. SWI is a switch, RL is a relay, rl is a contact of relay RL, RIR is a resistance, +V1 + 10V@ + 10V
s indicates a positive DC voltage.
Claims (1)
おり、該被制御装置のテストをする場合は該複数の制御
線の各々にマルチ接続されたテスト情報線及び該各々の
テスト情報線を介してテスト情報を送るためのスリース
テート制御可能なドライバのスリーステート情報線を該
被制御装置と該テスト装置間で複数のマルチコネクタで
接続し、該被制御装置より該テスト装置内の各々のスリ
ー八 ステート制御可能なドラ４バオスリーステート制由して
該被制御装置より該テスト装置に接続されるようにした
ことを特徴とするテストインタフェイス方式。[Claims] A control device and a controlled device are connected by a plurality of pairs of control lines, and when testing the controlled device, a test information line is connected to each of the plurality of control lines. and a three-state information line of a three-state controllable driver for sending test information via each test information line is connected between the controlled device and the test device by a plurality of multi-connectors, and the controlled device A test interface system characterized in that the controlled device is connected to the test device by controlling each of the three-eight-state controllable drivers and four-basis three-states in the test device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57127989A JPS5917645A (en) | 1982-07-22 | 1982-07-22 | Method of test interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57127989A JPS5917645A (en) | 1982-07-22 | 1982-07-22 | Method of test interface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5917645A true JPS5917645A (en) | 1984-01-28 |
Family
ID=14973693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57127989A Pending JPS5917645A (en) | 1982-07-22 | 1982-07-22 | Method of test interface |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5917645A (en) |
-
1982
- 1982-07-22 JP JP57127989A patent/JPS5917645A/en active Pending
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