JPS59174976A - Vector generating system - Google Patents

Abstract

PURPOSE:To shorten the whole operation time of vector operation mechanisms by installing several series of vector operation mechanisms which generates the address of a side to be based and simultaneously executing vector operation in parallel after dividing the calculation. CONSTITUTION:A total of 2N series of vector operation mechanisms are installed. A vector data control circuit 28 discriminates DELTA=to be based/base and 1/2N and, when DELTA<=1/2N, sets an initial value in all digitized differential analyzers DDA, an address counter to be based for calculation, and a counter to be based for calculation. When the setting of the initial value is completed, each calculating mechanism operates by using each parameter in response to an operation step control clock signal. Each base address counter for calculation adds + or -2N to a calculated result and supplies the added result to the memory 29. Each DDA sums up 2NXDELTA and makes the address counter to be based for calculation cumulate the overflow value and supplies the cumulated overflow value to the memory 29. Each length counter counts the calculating frequency and controls the operation of each operation mechanism. Each memory write control circuit repeats the addition of one to the address and completes the vector drawing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a vector generator that generates continuous coordinate values of display graphic line segments, that is, vectors, in a graphic processing device or the like, and particularly to a vector generator that generates continuous coordinate values of display graphic line segments, that is, vectors, in a graphic processing device, etc. The present invention relates to a vector generation method that is equipped with an arithmetic mechanism, divides a target vector into a plurality of parts, and calculates each of the divided sections in parallel, thereby increasing the speed.

[Technology background]

Generally, in a 9-figure processing device, vector data of 9-displayed figures is processed using DDA or BRM (Bina-ry
However, it has already been generated using the Rate Multiplier.

Since the latter has a problem with the quality of the generation point sequence, the former DDA method is often used.

FIG. 1 shows an example of a vector.

From point A at the coordinates (0,0) shown to B at the coordinates (10,7)
When displaying the integral toward a point on a graphic display device such as a CRT, it is necessary to interpolate the coordinate values of each point between the two vectors A and B.

FIG. 2 shows the principle of a conventional DDA vector generator for interpolating the coordinate values of intermediate points (dots) of arbitrary vectors. In the figure, ■ is an R register that holds the remainder of the addition result.

2 is a P register that stores the address value of the sum of the ΔL/sister and 3C addition results.

First, the relative distances 1ΔX1 and 1ΔY1 between two points are investigated, and the larger one is set as the base, and the smaller one is set as the base. 1st
In the example shown, IΔXI =10. l△Yl=7,
Since 1ΔX1≧1ΔY1, ΔX is the base and ΔY is the based. From now on, by DDA, △=1
Base 1/1 base cut=1ΔY1/1ΔX1 is calculated. This Δ value represents the amount of change in the Y coordinate per unit address of the X coordinate, and is stored in the Δ register 2 in the figure 2.

Conversely, when ΔY is the base, this Δ value represents the change in the X coordinate per unit address of the Y coordinate.

Next, the remainder of the previous addition result in R register 1 (initially 'o') is added to the Δ value in Δ register 2, and the result is stored in R register 1. When the addition result exceeds the value 1, an overflow pulse is sent to P register 3, and P
Add 1 or -1 to the 9 values in the register. Here, the P register 3 is a base address counter, and its contents represent the address value of the Y coordinate (in this example, the initial value is 101).

The above calculation operations are sequentially repeated for addresses within the ΔX range of the X coordinate. FIG. 3 shows the contents of each register in FIG. 2 when calculations are executed when the vectors in FIG. 1 are generated.

In the conventional vector generator using the DDA method described above, the coordinate values of each point constituting one vector are always calculated using the immediately previous calculation result, so complete data about the vector can be obtained. There was a problem in that it took a long time to complete and the display of 1 was delayed.

[Object and structure of the invention]

An object of the present invention is to increase the speed of a DDA type vector generator, and achieves the above object by dividing a vector to be generated into a plurality of parts and performing parallel operations.

Accordingly, the configuration of the present invention is such that the relative addresses △X, △Y and length of the vector to be generated are inputted in the vector generator, the smaller of △X and △Y is used as the base, and the larger one is used as the base. A vector data control circuit that calculates Δ=+1 base I/1 pace 1 as a base, divides the vector to be generated by 2N, where N is an integer, and uses the above Δ value to calculate the vector of each divided section. 2N m vector calculation means for calculating the 2N m vector calculation means.
This method is characterized in that two vector calculation means are simultaneously executed in parallel.

[Embodiments of the invention]

The details of the present invention will be explained below based on two examples.

Introduction 9 For comparison with the present invention, the configuration of the conventional DDA type vector generator explained in Fig. 2 will be explained.

This will be explained with reference to FIG.

In the diagram, 11 is a DDA, 12 is a base address counter, 13 is a base address counter, 14 is a length counter, and 15 is a +1 circuit.

16 is a clock control circuit, and 17 is a bitmap memory.

DDAII calculates 1 base l/1 base 1 according to input parameters ΔX and ΔY to obtain a Δ value. Subsequently, the +1 circuit 15 increments the base address counter 12 in response to the arithmetic step control clock signal supplied from the μ-clock control circuit 16, and supplies the increment to the bitmap memory 17 as a base-side address. DD at the same time
AII is.

The Δ values are accumulated, the overflow value is accumulated in the base address counter 13, and is supplied to the bitmap memory 17 as the base address. length counter 14
counts the number of vector write dots, that is, the number of calculation steps, based on the length data in the input parameter.

Controls the operation of address counters 12 and 13.

The bitmap memory 17 has an address counter 12゜1.
11# is written to the dot position accessed according to the base/base address supplied from 3. With this method, only one vector address can be calculated in one clock period.

In contrast, the present invention provides a 2N (N is an integer) series of vector calculation mechanisms that generate addresses on the base side, divides the vector address calculations, and executes them simultaneously in parallel, reducing the overall calculation time. This shortens the term.

FIG. 5 is a block diagram of a vector generator according to an embodiment of the present invention. In the figure, 21α, ..., 21n are each DDA
(1),...=, (2N), and 22a,
-, 22s address register (1) for calculation of heath
,..., (2'), and 23α,..., 23n are base calculation address registers (1),..., (2N).
Teari, 24a,...

24? S is length counter (1),..., (2N
).

' 25a, . . . , 25n are memory write control circuits. 26 is an addressed register;
27 is a base address counter, 28 is a vector data control circuit, 29 is a bitmap memory, and 30 is a clock control circuit.

First, the parameters ΔX, ΔY, and length.

The vector data is input to the control circuit 28. Here, 1
It is determined whether the Δ value of base 1 is smaller than 1/2N. If △>'/2N then 2
At the boundary between the divided address sections, there is a risk that two addresses of the base may change at once, and the quality of the drawn point sequence will deteriorate. (only υ is used; on the other hand, △〈
In the case of 1/2N.

All of DDA(1), . . . (2N) are used.

Let each series of the 2N vector calculation mechanisms be Vl,...,V
When expressed as n, Vl(21α, 22a, 23a, 24a
,';'5a).

---, VfL (21s, 22n, 23s, 24s, 2
5s).

Address calculation is performed for each corresponding address section of the base divided by n=2N.

After determining △ and 1/2N, the vector data control circuit determines △〉
In the case of 1/2N, only DDA (1), △≦1/2N
In this case, initial values should be set for all DDA(1) to (2N), and the corresponding initial values should be set for each calculation base address counter, calculation base address counter, and length counter. Control. When the set is completed, each page) Le Performance'1-WNlt
Is Vx~Vn a vector data system? It operates in response to an arithmetic step control clock signal supplied from the ripple control circuit 30 using each parameter supplied from the Rj circuit. Each calculation base address counter adds ±2N in response to the calculation step control clock signal and supplies the result to the bitmap memory 29 as a base address.

Each DDA accumulates (2N×△), and the overflow value is accumulated in the calculation spaced address counter and supplied to the bitmap memory 29 as the base address. Each length counter counts the number of calculations for each DDA and controls the operation of each vector calculation mechanism V l -V n. Each memory write control circuit controls each address supplied by each vector operation mechanism.

As a result, n vector addresses are generated simultaneously,
The data is supplied to a bitmap memory 29.

Memory write control circuits (1), . . . controlled by length counters (1), . . . (2N)
, (2N) writes lII to the dots at each of the nine generated addresses and repeats the necessary number of times to complete vector drawing. The base address and base address that drew the final vector are stored in the pace address counter 27. is set in the base address counter 26,
Display the current address point.

As mentioned above, if △> 1/2N, DDA
(1) 21α, address color data 26, 27.
A length counter (1) 24α and a memory write control circuit (1) 2sa are used to generate vectors in the same manner as the conventional device shown in FIG.

〔Effect of the invention〕

As a result, when there are many drawings of near-horizontal and vertical vectors, vector drawing can be performed at a high speed nearly n (2N) times the conventional speed.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of vectors, Figure 2 is a diagram of the operating principle of the conventional vector generation system, Figure 3 is an explanatory diagram showing the contents of each register in Figure 2, and Figure 4 is a diagram of the conventional vector generation system. The block diagram, FIG. 5, is an embodiment of a vector generator according to the present invention. In the figure, 218 to 21% is DDA, 22. 22n to 22n are address registers for base calculation, 23α to 23% are address registers for base calculation, 24α to 24n are length counters, 25a to 257L are memory write control circuits, 26 is a base address counter, 2
7 is a base address counter, 28 is a vector data control circuit, and 29 is a bitmap memory. Patent applicant Fujitsu Limited

Claims (1)

[Claims] The relative addresses ΔX, ΔY, and length of the vector to be generated in the vector generator are input, and ΔX
The smaller one of
A vector data control circuit that divides a vector generated by taking Δ as an integer into 2N, and 2N vector calculation means that calculates vectors in each of the divided sections using the Δ value described above. A vector generation method characterized by concurrently executing vector calculation means in parallel.