JPS59172988A - Control circuit for servo motor - Google Patents

Abstract

PURPOSE:To enable to control a speed of a servo motor in a wide range without anxiety of stepout by suppressing a current of the motor when the period of a reference pulse signal is the prescribed value or higher. CONSTITUTION:When the period of a clock signal CK to become a speed command is the prescribed value or lower, the Q output of a flip-flop 52 is high level, and a drive signal DS1 in response to the phase difference between the signal CK and a speed signal VS is applied to a transistor 141. When the period of the signal CK becomes the prescribed value or higher, the Q output of a flip- flop 52 becomes high level, and a drive signal DS2 is applied to a transistor 146. At this time, a current is supplied through a resistor 149 to a servo motor 15, and the current of the motor 15 is limited. In this manner, the stability in low speed rotation range increases, thereby preventing the stepout.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a servo motor control circuit, and more specifically, it proposes a servo motor control circuit capable of controlling speed over a wide range.

Force 2 - In a drum rotary printer such as an inkjet printer, the drum is rotated at a constant speed using a servo motor. This is because different constant rotation speeds are required for the operation of winding the printing paper around the drum, the printing operation, and the operation of separating the printed paper from the drum. This rotation control is performed by a clock signal C having a period corresponding to the rotation speed of the drum 12, as shown in FIG.
K to the control circuit 11, and a rotary encoder 13 connected to the drum so as to rotate in conjunction with the drum.In order to eliminate the phase difference between the output vS of the rotary encoder 13 and the clock signal CK, a servo motor 15 for driving the drum is provided. I was trying to speed up and brake. Note that 14 is a drive circuit for the servo motor 15.

However, in the past, a phenomenon occurred in which the motor rotated out of balance at an integral multiple of the period of the clock signal CK.
There were disadvantages such as variations in the rotational speed of the drum during one rotation, resulting in misalignment of prints. Therefore, the inventor of the present invention proposed a servo motor control circuit that memorizes the advance and lag of the clock signal and the rotary encoder output, thereby preventing the balance from being lost while the clock signal is out of step (Patent Application No. 58-4380 issue).

Figure 2 shows an example of this, including direct set,
Reset type D-7 lip 70 tab 41° 42, 43.
44.45, AND gate 46, and clock signal CK
and one-shot multi signals 47 and 48 used to create short time width (low level) pulse signals from each of the velocity signals vS obtained from the rotary encoder 13. A reference signal CK' obtained by applying a clock signal CK serving as a speed command to the one-shot multi 47 is applied to the D terminal of the flip-flop 43, the direct reset terminal RD, and the T terminal of the 7-lip 70-tub 41.42.
The detection signal vS' obtained by applying the speed signal VS obtained from the rotary encoder 13 to the one-shot multi 48 is applied to the D terminal of the slip 70 tube 41, the direct reset terminal RD, and the T terminal of the 7 lip-flop 43, 44. 0 Q output of flip-flop 41 is flip-flop 42
The Q output of the flip-flop 43 is applied to the D terminal of the flip-flop 70 and the AND gate 46. The Q output of the flip-flop 42 is given to the direct reset terminal RD of the flip-flop 45, and the output of the flip-flop 44 is supplied to the flip-flop 70.
It is applied to the direct set terminal SD of the knob 45.

Both the terminal and T terminal of the flip-flop 45 are set at low level, and the Q output thereof is used as the braking signal BS.

Further, the q output is used as another input of the AND gate 46, and the output of the AND gate 46 is used as the drive signal DS. Direct set terminals SD and direct reset terminals RD of flip-flops 41 to 45 are negative logic inputs, and direct set terminals SD of flip-flops 41 to 44 and direct reset terminals RD of flip-flops 42 and 44 are both at high level. It is fixed to .

The drive signal DS and braking signal BS obtained from the control circuit 11 described above are applied to the drive circuit 14 of the servo motor 15. In this drive circuit 14, when the drive signal DS becomes high level, the input stage transistor 141 is turned on, and the amplifier stage transistor 1421143 is also turned on, and the servo motor 15 is turned on.
When the braking signal BS becomes high level, the transistors 144 and 145 are turned on to short-circuit both terminals of the servo motor 15 to apply braking.

FIG. 3 is a time chart showing the operation of this control circuit 11, in which the speed signal vS lags behind the clock signal CK.
Therefore, the detection signal vS' is delayed with respect to the reference signal CK', and the drive signal DS becomes high level by an amount corresponding to this delay, indicating a situation in which the servo motor 15 is driven.

At the moment shown by ■, both the trench reference signal CK' and the detection signal VS' are at the 71 level, and the drive signal D is
Suppose that a low level pulse of the signal vS' is input in a situation where S is high level and the output of the flip-flop 43 is low level (braking signal BS is low level), the 7 flip-flop 41 is directly reset. Since the Q output becomes low level, the drive signal DS changes to low level. Then, at the rising timing of the above-mentioned pulse, the 7 lip flop 43 is set,
Its Q output becomes high level. However, next time (i CK' becomes a low-level pulse ■, the flip-flop 43 is directly reset. Also, at the rising timing of the pulse ■, the D input of the flip-flop 41 becomes Since it is at a high level, this is set and its Q output goes to a high level.On the other hand, since the 7 flip-flop 45 remains reset during this time, its output goes to a high level, and therefore the output of the AND gate 46, that is, the drive The signal DS will return to high level.Flip 70 knob 4
5 is set on D of flip 70 knob 44.
This is because while the input (the Q output of the same 43) is at the 71-level level, the signal S' does not change to the 71-level level, and therefore the 7-lip-flop 44 is not set.

Next, the operation when an abnormality occurs will be explained based on the time chart of FIG. The first abnormal pattern is seen in the period indicated by ■, where two pulses of the signal vS appear during one cycle of the signal CK' (the actual rotation is faster than the speed commanded by the clock signal CK). This is the case. The operation when the second pulse (2) of the signal vS' is input during this one cycle period will be described. First, at the falling edge, since the slip-flop 41 is already in the reset state, no change occurs. Next, at the rising edge, since the D terminal of the flip-flop 44 is at a high level, it is set, and the output becomes a low level (the Q output is shown in the figure), which causes the flip 70 knob 45 to direct is set, and the braking signal BS becomes high level. In other words, the rotation of the servo motor 15, which is faster than the clock signal CK, is braked.

Next, the pulse ■ of the signal CK' will be input,
At the falling timing, the 7 flip-flop 43 is directly reset, and at the rising timing, since the D terminal of the flip-flop 41 is at a high level, it is set. and signal VS
7 lip-flop 41 is directly reset at the falling edge of the next pulse 2', and 7 lip-flop 41 is reset at the rising edge of the pulse
The knob 43 is set, and the flip-flop 4 is set accordingly.
4 is reset. Thereafter, the braking signal BS remains at high level and the drive signal DS remains at low level. Note that there are three pulses of the signal VS' during one period of the signal CK'.
If more than one signal appears, the same signal changes as in the case described above will occur.

In the second abnormal pattern, as seen in the period indicated by 0, no pulse of the signal S' appears during one period of the signal CK' (the actual rotation speed is lower than the speed commanded by the clock signal CK). slow). The flip 70 knob 42 is set at the rising timing of the pulse 2 of the signal CK' which is inputted prior to the pulse of the signal vS', and the output changes to low level (the Q output is shown in the figure). Accordingly, the flip-flop 45 is directly reset, and the braking signal BS becomes low level. In other words, braking was applied because the actual rotation was faster than the command, but since the actual rotation was slower than the command, the braking was now released. Then, since both inputs of the AND gate 46 become equal to 1, the drive signal DS becomes equal to 1.

Next, when the pulse (2) of the signal vS' is input, the flip-flop 41 is directly reset at the falling edge of the signal vS', and the drive signal DS changes to low level, and the 7 flip-flop 43 is set at the rising edge of the signal vS'. Next, when the pulse ■ of the signal CK' is input, at its falling edge 7 rip 70 43
is reset, and at the rising edge 7 lip-flop 41
is set and 42 is reset. Since the flip-flop 41 is set, the drive signal DS becomes high level. In this way, the driving of the servo motor 15 is restarted again.

As mentioned above, in this circuit, the flip-flop 4
4, it is detected that the speed detection signal ■S' is ahead of the speed command signal CK', and the flip 7
The 0 knob 42 detects that the signal vS' is delayed from the signal CK', and this sets or resets the 7 lip 70 knob 45 to correct the detected content, that is, the phase lead or lag. It will be stored here until it is released. Therefore, as shown in FIG. 4, when a state in which the detected speed is faster than the speed command occurs, the slip-flop 45 is set to memorize this, and at the same time, the servo motor 15 is braked to decelerate it. , when this is resolved, in other words, when a state in which the detected speed is slow compared to the speed command appears, the flip-flop 45 is reset to memorize this, and the servo motor 15 is intermittently driven to eliminate this delay. By performing such braking, the signals CK' and V during this period are
The number of pulses of S' matches, and the balance is maintained even if the signal is out of step, so that it is not reversed.

However, when the clock signal CK becomes a very low frequency, the servo motor 15 follows it and rotates at a low speed, but as the energization period of the servo motor 15 becomes longer, the energizing current becomes shorter in cycle. It is larger than when the energization period is short due to intermittent driving, and the rotational speed tends to be higher than the speed commanded by the clock signal CK.
In order to suppress this, the braking signal BS is issued repeatedly, which results in an inconvenience in that smooth rotation is not performed and furthermore, the motor loses synchronization.

The present invention has been made to solve this problem, and when the period of the clock signal CK becomes larger than a predetermined value, power is supplied to the servo motor via a current limiting resistor. It is an object of the present invention to provide a servo motor control circuit that has a configuration that suppresses the supplied current and expands the low speed rotation range to perform speed control over a wider range without causing step-out.

The present invention will be specifically described below based on drawings showing embodiments thereof. FIG. 5 is a circuit diagram of a servo motor control circuit according to the present invention, and parts similar to those shown in FIG. 2 are given the same reference numerals. As can be understood from the comparison between the two figures, the circuit of the present invention is a retriggerable one-shot multivibrator (hereinafter referred to as a retriggerable one-shot multivibrator).
51, Direct set, reset type D-7 lip 7
A series circuit including a transistor 148 connected in parallel to the transistor 143, an AND gate 53 and 54, and a current limiting resistor 149 are added.

The configuration will be explained below. A reference signal CK' obtained by applying a clock signal CK serving as a speed command to the fun shot multi 47 is applied to the D terminal of the flip-flop 43 and the direct reset terminal RD.

The detection signal ■S is applied to the T terminals of the flip-flops 41, 42, and 43 and the trigger terminal of the retriggerable one-shot multi 51, and is obtained by applying the speed signal vS obtained from the rotary encoder 13 to the one-shot multi 48.
' is applied to the D terminal and direct reset terminal RD of the flip-flop 41, and the T terminals of the flip-flops 43 and 44.

The Q output of the flip-flop 41 is the Q output of the flip-flop 42.
The Q output of the flip-flop 43 is applied to the D terminal of the 7-rib-flop 44. The Q output of the flip-flop 42 is given to the direct reset terminal RD of the flip 70 knob 45, and the Q output of the flip flop 44 is applied to the flip 70 knob 45.
It is applied to the direct set terminal SD of the knob 45.

Both the terminal and T terminal of the flip-flop 45 are set at low level, and the Q output thereof is used as the braking signal BK.

Also, the Q output is used as another input of the AND gate 46, and the output of the AND gate 46.0 is used as an AND gate)53.
All 54 people are working on their own.

The output of the retrigger pull one-shot multi 51 is given to the D terminal of the flip-flop 52. The Q output and Q output of the flip-flop 52 are connected to an AND gate 53, respectively.
and 54, respectively, and the outputs of AND gates 53 and 54 are connected to drive signals DSI and DS.
It is set at 2.

The time constant of the retrigger pull one-shot multi 51 is the clock signal C that causes step-out in the conventional circuit shown in FIG.
Let it roughly match the low frequency limit of K.

Direct set terminal S of flip-flops 41 to 45
D and the direct reset terminal RD are negative logic inputs, and the direct set terminals SD of the flip-flops 41 to 44 and 52 and the flip-flops 42, 44 .
All of the direct reset terminals RD 52 are fixed at an output level.

Drive signal DSI obtained from the above-mentioned control circuit 11'.

DS2 and braking signal BS are applied to the drive circuit 14' of the servo motor 15. This drive circuit 14' has a drive signal D
When SI (or DS2) becomes high level, the input stage transistor 141 (or 146) turns on, and the amplifier stage transistors 142, 143 (or 147, 148) also turn on, supplying power to the servo motor 15 and rotating it. When the braking signal BS reaches the level of 1, the transistors 144,
145 is turned on, short-circuiting both terminals of the servo motor 15 and applying braking. transistor 14
A current limiting resistor 149 is interposed between the servo motor 8 and the servo motor 15.

The operation of the circuit of the present invention having the above-mentioned structure is as follows. That is, when the period of the clock signal CK is shorter than the time constant of the retrigger pull one-shot multi 51, its output is always at a high level, and therefore the flip-flop 52
The Q output of becomes high level, the single power of AND gate 53 becomes high level, and the single power of AND gate 54 becomes low level, so when AND gate 46 outputs a high level signal, drive signal DSI is obtained, The drive signal DS1
is applied to transistor 141. Therefore, in this case, the speed of the servo motor 15 will be increased in exactly the same manner as the circuit shown in FIG. The operation is similar when two pulses of the signal vs are obtained during one period of the clock signal, or when no pulse of the signal Vs is obtained.

On the other hand, when the period of the clock signal CK is longer than the time constant of the digital trigger pull one-shot multi 510, the following will occur.

FIG. 6 shows changes in the output of the retrigger pulldown multiplier 51 and the Q output of the flip-flop 52, and which transistors 143 or 148 are turned on when the signal CK' changes from a short period to a long period. .

After the retriggerable one-shot multi 51 is triggered by the pulse O of the signal CK', its output changes to -H low level when the time constant T elapses, and is retriggered at the rising edge of the next pulse ◎. flip 70 knob 52
is reset and its Q output becomes low level. After that, the retrigger pull one-shot multi 51 is triggered and the output changes to high level, but at the timing when the next pulse of signal CK' is input, its output, that is, the D input of flip-flop 52 changes to low level. Therefore, while the period of the clock signal CK is longer than T, the Q output of the flip-flop 52 is at a low level and the Q output is at a high level. Human power has reached a high level, and A
'When the ND gate 46 outputs a high level signal, a drive signal DS2 is obtained, which causes the transistor 14
8 becomes conductive. In other words, during low-speed rotation when a clock signal CK with a cycle longer than T is applied, power is supplied to the servo motor 15 through the transistor 148 and the resistor 149, and the presence of this resistor 149 limits the current flowing through the servo motor 15. As a result of maintaining the low speed rotation, step-out is prevented.

The operation of the drive circuit 14' in response to the braking signal BS is similar to that in the circuit shown in FIG. Furthermore, in the above embodiment, the resistor 149 is interposed in the power supply circuit of the servo motor 15 to suppress the current flowing during low speed rotation. It is also possible to suppress the servo motor current.

As described above, the servo motor control circuit according to the present invention includes a circuit for selecting a large or small current flowing through the servo motor, and a circuit for comparing the period of a reference pulse signal serving as a speed command with a predetermined value, and the said period is a predetermined value. If the above occurs, the servo motor is designed to reduce the current flowing through it, so
It is possible to provide a servo motor control circuit that increases stability in the low-speed rotation range and enables wide-range speed control without fear of step-out.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the rotation control system of a drum rotary printer, FIG. 2 is a circuit diagram of the control circuit of the prior invention, and FIGS. 3 and 4 are time charts for explaining its operation.
FIG. 5 is a circuit diagram of the control circuit of the present invention, and FIG. 6 is a time chart for explaining its operation. 11'...Control circuit 13...Rotary encoder 1
4'... Drive circuit 15... Servo motor 41, 42... 45, 52... Flip-flop 5
1... Retrigable one-shot multi 141.1
42...148...Transistor 149...Current limiting resistor Patent applicant Noboru Kono, Patent attorney representing Sanyo Electric Co., Ltd.

Claims (1)

[Claims] 1. Drive to eliminate the phase difference between the reference pulse signal serving as the speed command and the detection pulse signal obtained by detecting the rotation speed,
A control circuit for a servo motor that performs braking includes a circuit for selecting a large or small current flowing through the servo motor and a circuit for comparing the cycle of a reference pulse signal with a predetermined value, and when the cycle exceeds a predetermined value, A servo motor control circuit characterized in that it is configured to reduce the current flowing through the servo motor.