JPS59172193A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the number of wiring of a semiconductor memory and make the semiconductor memory highly integrated one by newly constituting the memory cell of electric current sensing system of a dynamic RAM to increase number of transistors at one memory cell by one, and to reduce the number of wiring by one. CONSTITUTION:The electric potential of all bit lines 32, word lines 33, and data lines 34 are set at 0V and the electric potential of a bis line 32 and word line connected to a cell to be selected is made high. When 0V or a high electric potential is impressed upon the data line 34 under this condition, a node A obtains a 0V or a high voltage. When the voltage of the selected bit line 32 and word line 33 is reduced to the original 0V, the node A is cut off from other nodes and fixed at the 0V or high electric potential to maintain this condition and to write data. Reading operation fixes the voltage of the bit lines, data lines, and word lines at 0V and the bit line 32 and word line 33 of a selected cell 31 obtain the high voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor memory, and in particular to dynamic RA.
This invention relates to improvements in M memory cells.

[Technical background of the invention and its problems]

Conventional dynamic RAM has one transistor per cell as shown in Fig. 1, voltage sensing method such as 1-canon or shifter, and 3-transistor per cell as shown in Fig. 2.
There were two types of current sensing methods such as 1-capacitor. In FIG. 1, 11 is a memory cell, and T11 is M
O8 type FET (hereinafter simply referred to as transistor), C1
1 is a capacitor, 12 is a word line, and 13 is a bit line. In FIG. 2, 21 is a cell, T-T
is a transistor, C2 is a capacitor, 21
23 22 is a read select line, 23 is a power supply vss line, 24 is a write select line, and 25 is a bit line that also serves as a data line.

The voltage sensing method shown in Figure 1 has only two elements per cell (one transistor, one transistor) and is suitable for high integration, but as the cell area becomes smaller and the capacitance becomes smaller, However, the following drawbacks have arisen.

That is, in this method, the potential of the capacitor C4 is output to the bit line 13 by turning on the transfer dart T,1, and this potential is detected. 1
Since the bit line is divided by a stray capacitance such as 3, the capacitance information applied to the bit line becomes extremely small.

Especially as the capacity of the capacitor C11 becomes smaller,
The stray capacitance of bit lines 13 and the like cannot be reduced in many cases, and has been a major obstacle to integration.

On the other hand, in the current sensing method shown in Fig. 2, the bit line 2
5. Transistor T25' Although the transistor T25' senses the current flowing to the V line 23 through T22, it has been thought that it is not suitable for integration because the number of elements per cell 21 is large. However, recently, as the problems with miniaturization of the voltage sensing method described above have become more serious, this has been reconsidered.

That is, in the cell 21, information is stored in the capacitor C21, but at the time of reading, the capacitor C2 is not connected to wiring outside the cell such as the drain 25, so the potential of the capacitor C2 is divided by stray capacitance, etc. at the time of reading. This is because it never happens. However, this current sensing method also requires four wiring lines (lines 22 to 22) per cell.
25), posing a major problem in terms of integration.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and aims to provide a semiconductor memory that can reduce the number of wiring lines in a current sensing type dynamic memory and achieve high integration.

[Summary of the invention]

The present invention achieves this by reconfiguring the current sensing type dynamic 5-RAM memory cells.
Although the number of transistors per memory cell increases by one, the number of wiring lines is reduced by one.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In this example, the transistor is an N-channel type MO8F.
Let us take the case of using ET as an example. FIG. 3 is an example of a circuit diagram of the dynamic RAM cell 31 according to the present invention, in which the drain of the transistor T31 is connected to the bit line (first select line), the dart is connected to the drain of the transistor T5□, and the source is connected to the drain of the transistor T53. Connect to each. The r-t of transistor T52 is connected to the bit line 32, and the source is connected to the drain of transistor T34. The dart of the transistor T33 is connected to the word line (second select line) 33, and the source is connected to the data line 34, respectively. The dart of the transistor T54 is connected to the word line 33, and the source thereof is connected to the data line 34. One end of the capacitor c31 is connected to the transistor T3. Connect to the dirt of the terminal, and connect the other end to the ground terminal (board may be sufficient).

The write operation of the above configuration will now be explained.

First, it is assumed that the potentials of all the bit lines 32, word lines 33, and data lines 34 are Ov (that is, logically "'0"). Next, set the potentials of the bit line 32 and word line 33 connected to the cell to be selected to a high potential (for example, 5V) (that is, logically set to 1"). At this time, '°
The transistor T of the cell connected to the 1# bit line 32 is turned on, the transistor T54 of the cell connected to the n 1 # word line 2 33 is turned on, but the transistor T3 of the other cell is turned on.

T34 remains off. Therefore, in one cell, transistors T and T are both turned on at 32
54 Only in the selected cell, one electrode (node A) of the capacitor C3 is connected to the data line 34.
connected to. By applying QV (ie, 0'') or high voltage (ie, 1'') to the data line 34 in this state, node A becomes Ov or a high voltage. Here, if the voltage of the selected bit line 32 and word line 33 is lowered to ov ("o") as before, node A is disconnected from other nodes and becomes OV (0") or It is fixed at a high potential ("1"') and this state is maintained. That is, data is written.

Note that in this example, the bit line 32 and the word line 33
After making the selection, data is sent to data lines 3 and 4, but this can be done at the same time, or the data can be sent to the data line earlier than the selection of the bit line and word line. .

Next, the read operation will be explained. First, as in writing, the voltages of the data line, bit line, and word line are initially fixed at Ov. Next, the potential □ of the bit line 32 and word line 33 of the selected cell 31 is set to a high voltage (for example, 5V or "°1"). In this way, transistors T3□ to T54 are turned on. At this time, when OV (that is, 0'') is stored in node A, the transistor T31 remains off until t, and the path from the bit line 32 in the 1# state to the data line 34 is cut off. No current flows through the data line.Since the data line 34 is at Ov, the potential at node A remains at Ov even if the transistors 32 and 34 are turned on.In other words, the potential at node A is set to 0 through the data line 34. The node A is firmly fixed and refreshed. That is, the potential of node A does not change due to reading. In this state, the voltages of the bit line and word line are lowered to complete the read cycle.

Next, consider the case where node A is at a high potential. At this time, transistor T3. is on, so bit line 3
When node B becomes a high voltage, node B also becomes a high voltage.

Further, since the word line 33 also becomes a high voltage, the transistor Tss is also turned on, and a current flows through the data line 34. At this time, the transistors T3□ and T34 are also turned on, so the data line 34 is connected to the high potential node A.
Current will also flow through. As this current flows, the potential of the node A becomes OV, the transistor T31 turns off, and the current flowing to the data line 34 stops.

Therefore, when a high potential is stored at node A, current flows instantaneously. In other words, a pulsed current flows. At this time, the current sense amplifier 35 shown in FIG. 5 at the end of the data line 34 (36 is a bit line and data line select section, 37 is a word line select section) detects the above-mentioned atomic current, and The voltage on line 34 is raised to a high potential. In this way, 32
34 High potential on data line 34 is written to node A again. That is, it is refreshed. In this state, the voltages on the bit line and word line are lowered to complete the read cycle. At this time, node A has returned to its original high voltage state. In this way, in the present invention, data of '0' and 'P1' are read out depending on whether a pulsed current flows through the data line or not.

Note that the following method can be used to increase the base pulse width of the i4 pulse-shaped current. (a) Raise the voltage on the bit line 32 before the word line 33, and
3. (b) Add capacitor C35, resistor R31, etc. to the dirt line of transistor T32 as shown in Figure 6, and turn on transistor T3□. delay time. (c) Capacitor 032 at node B
etc., to increase the charge accumulated at node B. )
A resistor R3□ is inserted in the line between the transistors 32 and 34 to slow down the outflow of the charge from the capacitor 51.On the other hand, there is no need to provide a special capacitor for the capacitors C31 to C53, etc. It is usual to devise an A-turn arrangement to increase the stray capacitance between the capacitor and the substrate.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the example of FIG.
Although the bit line 32 is parallel to the data line 34, the bit line 32 may be parallel to the data line 34 as shown in FIG. In addition, in the embodiment, an N-channel type MO8FET is used as an example of a transistor, but the transistor is not limited to this, and the transistor is a P-channel type MO8FET.
O8FET, Junction FET %
It may be a metal FET (MESFET) or a combination thereof.

〔Effect of the invention〕

As explained above, according to the present invention, by adopting the above structure, it is possible to reduce the number of wiring lines by one compared to the conventional current sensing type dynamic RAM cell, which contributes to high integration of LSI. This contributed greatly to the development of this product. Also, the number of transistors has increased by one, but this can be overcome by using clever placement or three-dimensional IC technology. Further, the advantage of this configuration is that a sense amplifier is added, and the read cells are automatically refreshed, which also has the advantages of the conventional voltage sensing method.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of a cell section of a conventional dynamic RAM, FIGS. 3 and 4 are circuit diagrams of a cell section of an embodiment of the present invention, and FIG. 5 is a layout diagram of the same cell and wiring. , FIG. 6 is a circuit diagram of a cell section of a different embodiment of the present invention. 31...Memory cell, 32...Bit line, 3
3...Word line, 34...Data line, T3
1 to T34...FET, C3,... Capacitor. Applicant's agent Patent attorney Takehiko Suzue 13- Figure 1 Figure 2? 1 2 ~T23゜1.1 i -ゝC21~ 123 Jiko, 24 Fig. 5 3Rajri Jko 35 6th B! ! 2

Claims (7)

[Claims] (1) Connect the drain of the first FET to the first select line, the date to the drain of the second FET, and the source to the drain of the third FET, and connect the dart of the second FET to the first select line. line, source to 4th FET
The y-t of the 30th FET is connected to the second select line and the source is connected to the data line, and the dart of the fourth FET is connected to the second select line and the source is connected to the data line. and one end of the capacitor is connected to the dirt of the tenth FET. (2) The semiconductor memory according to claim 1, wherein the first select line and the data line are parallel to each other, and the first select line and the second select line are orthogonal to each other. (3) The semiconductor memory according to claim 1, wherein the second select line and the data line are parallel, and the first select line and the second select line are perpendicular to each other. (4) The semiconductor memory according to any one of claims 1 to 3, wherein a sense amplifier is connected to the data line. (5) After reading data to the data line, applying a potential corresponding to the read data to the data line,
5. The semiconductor memory according to claim 1, wherein read data is written into the capacitor again. (6) The FET is an MO8 type FET or a junction type FET
The semiconductor memory according to any one of claims 1 to 5, characterized in that it is made of a Schottky gate type FET or a combination thereof. (7) A resistor or a capacitor is added to a desired node so as to extend the time during which the current flows from the first select line to the data line. The semiconductor memory according to any one of the above.