JPS59171126A - Etchant for palladium - Google Patents

Etchant for palladium

Info

Publication number
JPS59171126A
JPS59171126A JP4423583A JP4423583A JPS59171126A JP S59171126 A JPS59171126 A JP S59171126A JP 4423583 A JP4423583 A JP 4423583A JP 4423583 A JP4423583 A JP 4423583A JP S59171126 A JPS59171126 A JP S59171126A
Authority
JP
Japan
Prior art keywords
palladium
film
iodine
ammonium iodide
aperture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4423583A
Other languages
Japanese (ja)
Inventor
Shiyoujirou Sugashiro
菅城 象二郎
Akira Kikuchi
菊地 彰
Seiichi Iwata
誠一 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4423583A priority Critical patent/JPS59171126A/en
Publication of JPS59171126A publication Critical patent/JPS59171126A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

PURPOSE:To totally eliminate the generation of unsatisfactory characteristics of a device by a method wherein, when the palladium silicide electrode of an Si semiconductor device is going to be formed into the prescribed form by etching, an etchant solution of palladium, consisting of ammonium iodide of 4wt% or above, iodine of approximately 0.01wt% and water for the remainder, is used. CONSTITUTION:An N type region 2 is formed on a P type Si substrate 1 by diffusion or by performing ion implantation, and an SiO2 film 3 is generated on the whole surface by performing a heat treatment. Then, an aperture 4 is provided on the film 3 corresponding to the region 2 by performing a photoetching method, and a Pd film 5 is coated on the whole surface including the aperture 4. Subsequently, a heat treatment is performed at the temperature of 150 deg.C or above, a palladium silicide layer 6 is formed in the vicinity of the aperture 4 by having the film 5 and the region 2 reacted each other, and then a non-reacted film 5 is removed using the mixed solution of ammonium iodide and iodine. At this time, the composition of solution is formed as follows: 4wt% or above ammonium iodide, 0.01wt% or above iodine and water for the remainder. The above etchant is used, and an Al electrode 8 is coated on the remaining layer 6 through the intermediary of Ti-W alloy film 7.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はパラジウムのエツチング液に関する。[Detailed description of the invention] [Field of application of the invention] The present invention relates to a palladium etching solution.

し背景技術〕 従来、シリコン半導体装置のケイ化パラジウム電極の製
造においては、上衣面が絶縁膜で覆われたシリコン半導
体基体−Hに、−削孔を開[」シリコン半導体衣而を露
出させた後、パラジウムを蒸着し、さらに熱処理を行な
い、上記開孔部にのみケイ化パラジウムを形成し、未反
応のパラジウムのみをヨウ化カリウム、およびヨウ素の
混合水溶液で除去することにより形成した。ヨウ化カリ
ウム、およびヨウ素の水溶液は、パラジウムをエツチン
グするが、ケイ化パラジウムをほとんどエツチングしな
いため、上記開孔部にのみ選択t″1・jにケイ化パラ
ジウムを形成することができた。
BACKGROUND TECHNOLOGY Conventionally, in the production of palladium silicide electrodes for silicon semiconductor devices, a hole is drilled in a silicon semiconductor substrate H whose upper surface is covered with an insulating film to expose the silicon semiconductor substrate. Thereafter, palladium was vapor-deposited and further heat-treated to form palladium silicide only in the openings, and only unreacted palladium was removed with a mixed aqueous solution of potassium iodide and iodine. An aqueous solution of potassium iodide and iodine etches palladium, but hardly etches palladium silicide, so palladium silicide could be formed only in the openings at the selected t″1·j.

しかし、ヨウ化カリウム、およびヨウ素の水溶液には、
カリウムが含まれる。寸だ、ヨウ化カリウムには一般(
で、ナトリウムが不純物として多h1に含捷れる。ナト
リウム、カリウム等のアルカリ金属は、シリコン半導体
装置に広く用いられる酸化シリコン膜中の拡散が極めて
早く、また、イオン化し易い。このように、イオン化し
たアルカリ金属は、シリコン半導体の表面電位を変動さ
せる。
However, aqueous solutions of potassium iodide and iodine have
Contains potassium. In fact, potassium iodide has a common (
Sodium is included as an impurity in the polyh1. Alkali metals such as sodium and potassium diffuse extremely quickly in silicon oxide films widely used in silicon semiconductor devices, and are easily ionized. In this way, the ionized alkali metal changes the surface potential of the silicon semiconductor.

シリコン半導体の表面電位の変動は、MOSダイオード
のしきい値電圧変動等、シリコン半導体装置の特性不良
を引き起こす。このため、ヨウ化カリウム、およびヨウ
素の混合水溶液をケイ化パラジウム電極の作製に用いる
のは望ましくない。
Fluctuations in the surface potential of silicon semiconductors cause characteristic defects in silicon semiconductor devices, such as fluctuations in the threshold voltage of MOS diodes. For this reason, it is not desirable to use a mixed aqueous solution of potassium iodide and iodine for producing a palladium silicide electrode.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、シリコン半導体装置のケイ化パラジウ
ム電極の製造法において、アルカリ金属を含−まないパ
ラジウムとケイ化パラジウムの選択エツチング液を提供
することである。
An object of the present invention is to provide a selective etching solution for palladium and palladium silicide that does not contain an alkali metal in a method for manufacturing palladium silicide electrodes for silicon semiconductor devices.

〔発明の概陳〕[Summary of the invention]

本発明は、ヨウ化カリウムを使用することなしに、ヨウ
化アンモニウムを使用するものである。
The present invention uses ammonium iodide without using potassium iodide.

ヨウ化カリウムはカリウムを含むが、さらにカリウムと
同族同素であるナトリウム等のアルカリ金属を不純物と
して含む。先に述べたように、アルカリ金属は、シリコ
ン半導体装置の特性不良の原因となる。一方、ヨウ化ア
ンモニウムはアルカリ金属をほとんど含壕ない。このた
め、シリコン半導体装置製造工程中に本発明によるパラ
ジウムのエツチング液を使用しても、シリコン半導体装
省の特性不良を引き起こすことはない。
Potassium iodide contains potassium, but it also contains impurities such as alkali metals such as sodium, which are homologous to potassium. As mentioned above, alkali metals cause poor characteristics of silicon semiconductor devices. On the other hand, ammonium iodide contains almost no alkali metal. Therefore, even if the palladium etching solution according to the present invention is used during the manufacturing process of silicon semiconductor devices, it will not cause defects in the characteristics of the silicon semiconductor devices.

〔発明の実施例〕[Embodiments of the invention]

以下、ケイ化パラジウム電極を用いたp −nダイオー
ドの製造法に関する実施例を用いて、本発明の詳細な説
明する。
Hereinafter, the present invention will be described in detail using an example of a method for manufacturing a p-n diode using a palladium silicide electrode.

まず、第1図に示すように、p型半導体基鈑に通常の拡
散法、およびイオン注入法によりn型領域2を形成17
、その後、熱酸化により、酸化シリコン膜3を形成した
。さらに、通常写真食刻法により、孔4を酸化/リコン
膜3に開口した。次に通常の蒸滑法によりパラジウム膜
5を形成した。
First, as shown in FIG. 1, an n-type region 2 is formed 17 on a p-type semiconductor substrate by a normal diffusion method and an ion implantation method.
Then, a silicon oxide film 3 was formed by thermal oxidation. Further, holes 4 were opened in the oxidation/recon film 3 by ordinary photolithography. Next, a palladium film 5 was formed by a normal evaporation method.

さらに、第2図に示すように、150U以十の熱処理を
行ないパラジウム膜5とI]型シリコン基板2とを反応
させることにより、孔4の近傍にケイ化パラジウム層6
を形成した。その後、第3図に示すように、ヨウ化アン
モニウムおよびヨウ素の混合水溶液により、未反応のパ
ラジウム膜5を除去した。このとき、ヨウ化アンモニウ
ムおよびヨウ素の混合水溶液の濃度を重量比で、ヨウ化
アンモニウム4 W 1%以上、ヨウ素0.0]、wt
%以にとすると、同液によるパラジウムのエツチング速
度は、ケイ化パラジウムのエツチング速度(D 10倍
以上である匁第、ケン化パラジウム層6は、未反応パラ
ジウム膜5のエツチング後も、存在することから、ケイ
化パラジウム電極が形成できた。
Further, as shown in FIG. 2, a heat treatment of 150 U or more is performed to react the palladium film 5 and the I type silicon substrate 2, thereby forming a palladium silicide layer 6 in the vicinity of the hole 4.
was formed. Thereafter, as shown in FIG. 3, the unreacted palladium film 5 was removed using a mixed aqueous solution of ammonium iodide and iodine. At this time, the concentration of the mixed aqueous solution of ammonium iodide and iodine was determined by weight ratio: ammonium iodide 4W 1% or more, iodine 0.0], wt
%, the etching rate of palladium by the same solution is at least 10 times the etching rate of palladium silicide (D), and the saponified palladium layer 6 remains even after the unreacted palladium film 5 is etched. Therefore, a palladium silicide electrode could be formed.

さらに、チタンおよびタングステンの合金膜7、アルミ
ニウム膜8を順次通常の蒸五法で形成し、さらに、通常
の写真食刻法でアルミニウム膜8、チタンおよびタング
ステンの合金膜7を順次エツチングし、配線層を形成し
た。
Furthermore, a titanium and tungsten alloy film 7 and an aluminum film 8 are sequentially formed using a normal vapor deposition method, and further, the aluminum film 8 and a titanium and tungsten alloy film 7 are sequentially etched using a normal photolithography method to form wiring lines. formed a layer.

次に、ヨウ化アンモニウムおよびヨウ素の混合水溶液に
よるパラジウムのエチング速度を第4図および第5図に
示す。
Next, the etching rate of palladium by a mixed aqueous solution of ammonium iodide and iodine is shown in FIGS. 4 and 5.

第4図はヨウ化アンモニウムおよびヨウ素混合水m 液
(7J)ヨウ素濃度によるパラジウムのエツチング速度
依存性を示したものである。なお、ヨウ化アンモニウム
と水との重量比は0.5で、測定温度は25C1である
。第4図より、ヨウ素濃度が重量比でo、oiwt%以
上であれば、パラジウムのエツチング速度は15nm/
min以上である。寸だ、ヨウ化アンモニウムおよびヨ
ウ素の混合水溶液によるケイ化パラジウムのエツチング
速度は約1〜1、5 nm/m i n程度である。従
って、ヨウ素濃度が0.01w13以上であれば、ケイ
化パラジウムとパラジウムのエッチング速度比1tlo
倍以上となり、パラジウムのみを選択的にエツチングし
、ケイ化パラジウムのみを残すことができる。
FIG. 4 shows the dependence of palladium etching rate on the iodine concentration of ammonium iodide and iodine mixed water solution (7 J). Note that the weight ratio of ammonium iodide to water was 0.5, and the measurement temperature was 25C1. From Fig. 4, if the iodine concentration is 0, oiwt% or more by weight, the etching rate of palladium is 15 nm/
It is more than min. In fact, the etching rate of palladium silicide with a mixed aqueous solution of ammonium iodide and iodine is about 1 to 1.5 nm/min. Therefore, if the iodine concentration is 0.01w13 or more, the etching rate ratio of palladium silicide and palladium is 1tlo.
This makes it possible to selectively etch only palladium, leaving only palladium silicide.

第5図はヨウ化アンモニウムおよびヨウ素混合化溶液の
ヨウ化アンモニウム濃度によるパラジウムのエツチング
速度依存性を示したものである。
FIG. 5 shows the dependence of the palladium etching rate on the ammonium iodide concentration of the ammonium iodide and iodine mixed solution.

なお、ヨウ素とヨウ化アンモニウムの重量比−0,1で
あり、測定温度は25Cである。第5図よシ、ヨウ化ア
ンモニウム濃度が重量比で4Wj%以上あれば、パラジ
ウムのエツチング速度け15nm/min以上である。
Note that the weight ratio of iodine and ammonium iodide is -0.1, and the measurement temperature is 25C. As shown in FIG. 5, when the ammonium iodide concentration is 4 Wj% or more by weight, the palladium etching rate is 15 nm/min or more.

捷だ、ヨウ化アンモニウムおよびヨウ素の混合水溶液に
よるケイ化パラジウムのエツチング速度は1〜1.5 
nm/m i n  程度である。従って、ヨウ化アン
モニウム濃度が4wt%以上あれば、ケイ化パラジウム
とパラジウムのエツチング速度比は10倍以上であり、
パラジウムのみを選択的にエツチングでき、ケイ化パラ
ジウムのみを残すことができる。
However, the etching rate of palladium silicide with a mixed aqueous solution of ammonium iodide and iodine is 1 to 1.5.
It is about nm/min. Therefore, if the ammonium iodide concentration is 4 wt% or more, the etching rate ratio of palladium silicide and palladium is 10 times or more,
Only palladium can be selectively etched, leaving only palladium silicide.

第4図、および第5図の結果から、重匍゛化において、
ヨウ素濃度が0.01w13以上で、かつ、ヨウ化アン
モニウムが4wt%以上であれば、ヨウ化アンモニウム
およびヨウ素の混合水溶液で、10倍以上の選択比で、
パラジウムをエツチングし、ケイ化パラジウムを残すこ
とができる。
From the results shown in Figures 4 and 5, in increasing weight,
If the iodine concentration is 0.01w13 or more and the ammonium iodide is 4wt% or more, a mixed aqueous solution of ammonium iodide and iodine with a selectivity of 10 times or more,
Palladium can be etched leaving behind palladium silicide.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図は本発明の一実施例を示す工程図、第
4図および第5図は本発明の効果を示す曲線図である。 1.2・・・シリコン半導体基板、3・・・酸化シリコ
ン膜、4・・・孔、5・・・パラジウム膜、6・・・ケ
イ化パラジウム層、7・・・チタンおよびタングステン
の合金■  1  図 第  /  n 千  3  図 第    4    し1 !−一、 −一−−,1 1(II 、、−、、−2□。tuty) ”’  “
′佑 5  図 、NHaI湾屓 (−bit別
FIGS. 1 to 3 are process diagrams showing one embodiment of the present invention, and FIGS. 4 and 5 are curve diagrams showing the effects of the present invention. 1.2... Silicon semiconductor substrate, 3... Silicon oxide film, 4... Hole, 5... Palladium film, 6... Palladium silicide layer, 7... Titanium and tungsten alloy ■ 1 Figure No./n 1,000 3 Figure 4 Shi 1! -1, -1--,1 1(II,,-,,-2□.tuty) ”' “
'Yu 5 Figure, NHaI bay (-by bit)

Claims (1)

【特許請求の範囲】[Claims] 重量比において、ヨウ化アンモニウムはぼ4wt%以上
、ヨウ素はぼ0.01wt%以上、残部水から成るパラ
ジウムのエツチング液。
A palladium etching solution consisting of approximately 4 wt% or more of ammonium iodide, approximately 0.01 wt% or more of iodine, and the balance water in terms of weight ratio.
JP4423583A 1983-03-18 1983-03-18 Etchant for palladium Pending JPS59171126A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4423583A JPS59171126A (en) 1983-03-18 1983-03-18 Etchant for palladium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4423583A JPS59171126A (en) 1983-03-18 1983-03-18 Etchant for palladium

Publications (1)

Publication Number Publication Date
JPS59171126A true JPS59171126A (en) 1984-09-27

Family

ID=12685865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4423583A Pending JPS59171126A (en) 1983-03-18 1983-03-18 Etchant for palladium

Country Status (1)

Country Link
JP (1) JPS59171126A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7265040B2 (en) * 2002-12-05 2007-09-04 Samsung Electronics Co., Ltd. Cleaning solution and method for selectively removing layer in a silicidation process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7265040B2 (en) * 2002-12-05 2007-09-04 Samsung Electronics Co., Ltd. Cleaning solution and method for selectively removing layer in a silicidation process

Similar Documents

Publication Publication Date Title
JP2701730B2 (en) Semiconductor device and manufacturing method thereof
US4220706A (en) Etchant solution containing HF-HnO3 -H2 SO4 -H2 O2
JP2544396B2 (en) Method for manufacturing semiconductor integrated circuit device
US3477886A (en) Controlled diffusions in semiconductive materials
JPH05102155A (en) Copper wiring structure and its manufacture
JPS6064431A (en) Method of etching refractory metal film on semiconductor structure
JPH035058B2 (en)
JPS59171126A (en) Etchant for palladium
US3640782A (en) Diffusion masking in semiconductor preparation
US10930519B2 (en) Wet etching of samarium selenium for piezoelectric processing
JP2594032B2 (en) Light emitting element
JPH0529470A (en) Forming method of wiring
JP4740469B2 (en) Method for forming gate electrode of semiconductor element
JPS6321871A (en) Fsemiconductor device
JPS60251663A (en) Semiconductor device
JPH02299237A (en) Heat treatment of al film
JPS62281353A (en) Semiconductor device
JPS6151941A (en) Manufacture of electrode wiring film
JPS62143422A (en) Manufacture of semiconductor device
JPH0867993A (en) Production of semiconductor device and method for inspecting semiconductor device
JPH05109996A (en) Semiconductor device
JPS5867078A (en) Manufacture of compound semiconductor device
JPS60115244A (en) Manufacture of semiconductor device
JPH0491429A (en) Manufacture of semiconductor device
JPS6240770A (en) Manufacture of semiconductor device