JPS59165117A - Digital input device - Google Patents

Digital input device

Info

Publication number
JPS59165117A
JPS59165117A JP58038952A JP3895283A JPS59165117A JP S59165117 A JPS59165117 A JP S59165117A JP 58038952 A JP58038952 A JP 58038952A JP 3895283 A JP3895283 A JP 3895283A JP S59165117 A JPS59165117 A JP S59165117A
Authority
JP
Japan
Prior art keywords
signal
circuit
input
digital
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58038952A
Other languages
Japanese (ja)
Inventor
Shuji Naraoka
修治 奈良岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58038952A priority Critical patent/JPS59165117A/en
Publication of JPS59165117A publication Critical patent/JPS59165117A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE:To reduce the heat generation of an input current limiting resistance and to realize high-density packaging by providing a storage circuit which is stored with the logical information of a digital signal output source in the feeding period of an impulsive input current. CONSTITUTION:A pulse generating circuit 21 generates a pulse signal 22 with a period tau, which is inputted to a switching circuit 24 through a photocoupler 23 for insulation. A voltage supplied from an external DC power source 2 at the timing of this signal 22 is outputted to input circuits 11-14 by turning on the circuit 24 for a period (t). At this time, the input current i2 flows through a photocoupler 7 and the input current limiting resistance 9 for the period (t). Therefore, a logical level signal 3A after the level conversion by the photocoupler 7 is latched by the storage circuit 25 at a rise of the signal 22 and outputted as a digital signal 3B. The signal 22 falls with slight- time delay, and consequently the circuit 25 latches the signal 3A. Other input circuits 12-14 operate similarly.

Description

【発明の詳細な説明】 〔技術分野の説明〕 不発明はディジタル入力装置に係シ谷;I7のプロセス
コントローラシステム6二使用されるコントローラ外部
のディジタル信号を、コントローラ側で必狭なディジタ
ル信号(二便候する改良されたディジタル人力装@1=
関する。
Detailed Description of the Invention [Description of the Technical Field] The invention relates to a digital input device; Improved digital human-powered equipment for two reasons @1=
related.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

プロセスコントロールシステムで扱つテイシタル信号(
二は各種のディジタル信号がオシ、それ等の信号の出力
源(二は、スイッチ及びリレーで代衣される接点(二よ
るオン・オフ出力の他トランジスタ等の半導体スイッチ
による磁気的なオン・オフ出力がある。これらのディジ
タル1g号の電圧レペは谷ディジタル系R(=よって各
々ま′c)まちである為、各電圧レベル別にディジタル
入力装置の入力抵抗等を換える4が必要である。その為
、プロセスコントロールシステムで扱う入力点蘇(二加
えて各電圧レベル毎のディジタル入カーA直が心安とな
シ、ディジタル入力装置の種部が多くなると云う問題が
ある。
Statistical signals handled by process control systems (
The second is the output source of various digital signals, and the output source of those signals (the second is the on/off output by switches and relays, and the magnetic on/off output by semiconductor switches such as transistors). There is an output.Since the voltage repeats of these digital 1g are different from the valley digital system R (=therefore, each ma'c), it is necessary to change the input resistance etc. of the digital input device for each voltage level. Therefore, there is a problem in that the number of input points handled by the process control system (in addition to the number of input points handled by the process control system) and the number of digital input devices for each voltage level increases.

また′#J1図は従来の一般的なディジタル入力装置の
外部デジタル入力部を示す回路図でbる。同図(二おい
て1はディジタル入力装置、2は外部直流°鴫源、3〜
6はディジタル信号出力源の接点及びスイッチでおる。
Figure '#J1 is a circuit diagram showing an external digital input section of a conventional general digital input device. The same figure (in 2, 1 is a digital input device, 2 is an external DC source, 3-
6 is a contact and a switch of a digital signal output source.

ディジタル人力装置lは信号絶縁のためのフォトカプラ
7、逆゛龜圧+X、護ダイオ−ド8、入力′磁流制限抵
抗9、及びレベル変換抵抗lOから成る入力回路11〜
14で構成されている。
The digital human power device 1 is an input circuit 11 consisting of a photocoupler 7 for signal isolation, a reverse voltage +X, a protection diode 8, an input magnetic current limiting resistor 9, and a level converting resistor 10.
It consists of 14.

上記構成(1於て1、谷ディジタル信号出力源3〜6の
オン・オフ(二対応して各入力回路11〜14の出力(
二はロジックレベルに変換されたディジタル信号3A〜
6Aが得られる。
The above configuration (1 in 1, valley digital signal output sources 3 to 6 on/off (2) corresponding to the outputs of each input circuit 11 to 14 (
The second is the digital signal 3A converted to logic level.
6A is obtained.

谷ディジタル信号出力源3〜60オン状態のとき谷入力
回路11〜141mは外部直流鴫源2の磁圧と入力電流
1tI’月衣抵抗9の坤抗値で冥まる入力−流11が流
れる。この入力4(Iff、itはディジタル信号出力
源3〜4のオン・オフ状態を検出するに必要な値に設定
する必要がある。
When the valley digital signal output sources 3 to 60 are on, an input current 11 flows through the valley input circuits 11 to 141m, which is filled with the magnetic pressure of the external direct current source 2 and the input current 1tI' and the resistance value of the resistor 9. This input 4 (Iff, it) must be set to a value necessary to detect the on/off state of the digital signal output sources 3 to 4.

しかし外部直戎竜諒2の磁圧が萬くなる(二つれて入力
磁流ilン設定する為の入力磁流制限抵抗9で消費され
る電力損失が大きくなシ発熱が大きくなる。この為、デ
ィジタル入力装置1の温度上昇2招く事になる。
However, the magnetic pressure of the external direct coil 2 becomes weak (the power loss consumed by the input magnetic current limiting resistor 9 for setting the input magnetic current is large, and the heat generation increases. , this will lead to a temperature rise 2 in the digital input device 1.

さら(二人力電流市1」限抵抗9の抵抗値も外部直流屯
源20屯圧別(二設屋する必資があり、発熱のための竜
力容電の大きな抵抗な必狭とするため、実装密度が低く
なると云う問題がある。
In addition, the resistance value of the limiting resistor 9 (two-person power current city 1) is also external DC source 20 tonne pressure (2 installations are required, and the large resistance of the power capacitor for heat generation is required) , there is a problem that the packaging density becomes low.

(発明の目的〕 本発明は前記事由(1鑑みてなされたものでちゃ、外部
匝゛流磁源から流入するディジタル信号出力源(ヨよる
入力電流を周期的なパルス状の入力電流とし、そのパル
ス状の入力Kmの通電期間(ニデイジタル信号出力源の
論理情報ン記憶する目己憶回路な設け、ディジタル信号
入力回路の入力電流制限抵抗の発熱を低減したディジタ
ル入力装置ン得るのが目的でおる。
(Object of the Invention) The present invention has been made in view of the above-mentioned reason (1). The purpose is to provide a memory circuit for storing the logic information of the digital signal output source during the energization period of the pulsed input Km, and to obtain a digital input device that reduces the heat generation of the input current limiting resistor of the digital signal input circuit. is.

〔発明の概要〕[Summary of the invention]

本発明は各種スイッチの開閉(−よる繊理情報を電気的
なロジックレベルのディジタル信号(二に侯するディジ
タル入力装置tt二於て、前記各棟スイッチが閉じたと
き嘔気的なロジックレベルに変換する入力回路(1流れ
る入力444周期的(=パルス状に通′屹するスイッチ
ング回路と、前記パルス状(二通電した期間(己変換さ
れた前記ロジックレベルの信号を保)持して前記ディジ
タル信号として出力する記憶回数!設は入力電媒制限抵
抗の・電力損失な低減して発熱を少くしたディジタル入
力装置である。
The present invention converts the fiber information caused by the opening and closing of various switches into an electrical logic level digital signal (tt2) into a disgusting logic level when each of the switches is closed. An input circuit (1 flowing input 444) periodically (=pulse-like) switching circuit, and the above-mentioned pulse-like (2) period of energization (holding the self-converted logic level signal) to output the digital signal. The device is a digital input device that reduces heat generation by reducing input voltage limiting resistance and power loss.

〔発明の実施例〕[Embodiments of the invention]

第2図は本発明の一実施例を示すディジタル入力装置の
構成図である。
FIG. 2 is a block diagram of a digital input device showing one embodiment of the present invention.

同図に於て第1図と同じ符号は同じ機能を示す。In this figure, the same reference numerals as in FIG. 1 indicate the same functions.

21はパルス発生回路で一定の周期で一定のパルス幅の
パルス信号22を発生する。るはパルス16号nの絶縁
用フォトカプラ、腐はスイッチング回路で7オトカプラ
おの出力(二よシ外部直流峨源2の電圧をパルス信号2
2(二同期してチョッピングして出力する。5は記憶回
路で入力口′N111〜14から出力サレるロジックレ
ベル信号3八〜6Aを一時記憶してディジタル信号3B
〜6Bとして出力する。
A pulse generating circuit 21 generates a pulse signal 22 having a constant pulse width at a constant cycle. The output is the insulating photo coupler of the pulse No. 16 n, and the switching circuit is used to convert the voltage of the external DC voltage source 2 into the pulse signal 2.
2 (Two synchronously chopped and output. 5 is a storage circuit that temporarily stores the logic level signals 38 to 6A output from the input ports N111 to 14 and outputs the digital signal 3B.
~ Output as 6B.

第3図は第2図で示す本発明の詳細な説明する為のタイ
ムチャートでおる。パルス発生回路21から第3図で示
す様な所定の周期τのパルス信号nk発生させ、絶縁用
フォトカフ2232通してスイッチング回Nr2/i(
二人力する。このパルス信号ρのタイミングで外部直流
電源2から供給される電圧を第3図で示すtの期間だけ
スイッチング回路冴を導通して、入力回路11〜14i
二出力する。この時例えばディジタル信号出力源3が第
3図で示す株なタイミングでON、OFFFF信号力出
力いるとすると7オトカプラ7、入力電流制限抵抗9ケ
逃して入力電流12はtの期間だけ流れる。従って7オ
トカグラ7(二よシレベル変換されたロジックレベル信
号3Aは入力電流12と同じ波形の信号となる。このロ
ジックレベル信号3Aはパルス16号nの立上シのタイ
ミングt1で記憶回路改に2ツテされディジタル信号3
Bとして出/力される。ロジックレベル信号3Aの立下
シ時刻はパルス16号ρの立上シ時刻よシ微少時間の遅
れを有し、これによシ記憶回路5はロジックレベル信号
3A’t’ラツチすることができる。
FIG. 3 is a time chart for explaining in detail the present invention shown in FIG. 2. A pulse signal nk with a predetermined period τ as shown in FIG. 3 is generated from the pulse generation circuit 21, and the switching circuit Nr2/i (
Two people work together. At the timing of this pulse signal ρ, the voltage supplied from the external DC power supply 2 is turned on for a period t shown in FIG.
Outputs two. At this time, for example, if the digital signal output source 3 outputs ON and OFF signal power at the regular timing shown in FIG. 3, the 7 automatic couplers 7 and the 9 input current limiting resistors miss, and the input current 12 flows for a period of t. Therefore, the logic level signal 3A after level conversion becomes a signal with the same waveform as the input current 12.This logic level signal 3A is input to the memory circuit 2 at the timing t1 of the rising edge of the pulse No. 16n. Digital signal 3
It is output/output as B. The falling time of the logic level signal 3A is slightly delayed from the rising time of the pulse No. 16 ρ, so that the memory circuit 5 can latch the logic level signal 3A't'.

パルス信号nにより周期τヲ経過するK(二ラッチ動作
が行なわれ時刻tsl二於てディジタル信号3Bが便化
する。尚時刻t2ではディジタル信号出力源3がON状
態のま−なのでラッチ制作が行なわれてもディジタル信
号3Bは変化しない。他のディジタル1g号出力源4〜
6(二ついても同様の動作が行なわれラッチされたディ
ジタル信号4B〜6Bが記憶回路5から出力される。
K (two latch operations are performed and the digital signal 3B is generated at time tsl2 when the period τ elapses due to the pulse signal n. At time t2, the digital signal output source 3 is still in the ON state, so latch production is performed. The digital signal 3B does not change even if the other digital signal 1g output sources 4~
6 (even if there are two, the same operation is performed and the latched digital signals 4B to 6B are output from the memory circuit 5.

上記の様(二本発明のディジタル入力装置(二おいては
入力′電流12はディジタル信号出力源3〜6が常時オ
ン常態であっても第3図で示す周期τ(二対しtの期間
たけ流れるパルス状の電流となる即ち入力電流12の実
効値は1.、Jt/τ とな9、t/τを小さくすれば
入力電流制限抵抗9で消費される磁力損失及び発熱が小
さくなる。また入力電流制限抵抗9の層数は外部直流゛
電源2の電圧(二よらず一定とすることができる。
As described above (2) In the digital input device of the present invention (2), even if the digital signal output sources 3 to 6 are always on, the input current 12 has a period of A pulse-like current flows, that is, the effective value of the input current 12 is 1. Jt/τ 9. If t/τ is reduced, the magnetic loss and heat generated by the input current limiting resistor 9 are reduced. The number of layers of the input current limiting resistor 9 can be constant regardless of the external DC voltage or the voltage of the power source 2.

〔発明の効米〕[Efficacy of invention]

本発明のディジタル入力装置(二よれば入力電流制限抵
抗の発熱が少ないので用品の高密度実装が0丁能となる
。またディジタル信号出力源(二用いられる外郡竜源の
′重圧レベルが異っても使用することが可hヒとなり襟
早化が9ロじとなる。従って採寸性の向上したディジタ
ル入力装置ケ得ることができる。
According to the digital input device (2) of the present invention, the heat generation of the input current limiting resistor is small, so high-density packaging of supplies is possible.Also, the digital signal output source (2) has different pressure levels of the outside gun source used. Therefore, it is possible to use a digital input device with improved measuring performance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のディジタル入力装置の構成図、゛ 第2
図は本発明の一実施例を示す構成図、第3図はその動作
説明の為のタイムチャートである。 1・・・ディジタル入力装置 3A〜6A・・・口〃力
ど仏悄号2・・・外部直流屯源   21・・・パルス
発生回路3〜6・・・ディジタル信号出力源 る・・・
フォトカプラ7・・・フォトカプラ   冴・・・スイ
ッチング回路8・・・逆電圧保譲ダイオード5・・・記
憶回路9・・・入力電流制限抵抗 3B〜6B・・・デ
ィジタル信号11〜14・・・入力回路
Figure 1 is a configuration diagram of a conventional digital input device.
The figure is a block diagram showing one embodiment of the present invention, and FIG. 3 is a time chart for explaining its operation. 1... Digital input device 3A to 6A... Word of mouth 2... External DC source 21... Pulse generation circuit 3 to 6... Digital signal output source Ru...
Photocoupler 7... Photocoupler Sae... Switching circuit 8... Reverse voltage holding diode 5... Memory circuit 9... Input current limiting resistor 3B-6B... Digital signal 11-14...・Input circuit

Claims (1)

【特許請求の範囲】[Claims] 各種スイッチの開吐10よる論理情報な磁気的なロジッ
クレベルのディジタル信号(二変侯するディジタル入力
装置(:於て、前記各種スイッチが閉じたとき磁気的な
ロジックレベルに変換する入力回路に流れる人力′電流
を周期的(ニパルス状に迫也するスイッチング回路と、
前記パルス状(=iljl 也した期間(−変換された
前記ロジックレベルの1d号を保持してFitJ記ディ
ジタル1B号として出力する+1iL8渾回路を設けた
ことを**とするディジタル入力装置。
When the various switches are closed, a digital signal at a magnetic logic level, which is logic information, flows into an input circuit that converts it into a magnetic logic level when the various switches are closed. A switching circuit that generates a human-powered current in a periodic (double-pulse) manner,
The digital input device is provided with a +1iL8 arm circuit that holds the converted logic level 1d and outputs it as a FitJ digital number 1B during the pulse-like (=iljl) period (-).
JP58038952A 1983-03-11 1983-03-11 Digital input device Pending JPS59165117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58038952A JPS59165117A (en) 1983-03-11 1983-03-11 Digital input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58038952A JPS59165117A (en) 1983-03-11 1983-03-11 Digital input device

Publications (1)

Publication Number Publication Date
JPS59165117A true JPS59165117A (en) 1984-09-18

Family

ID=12539531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58038952A Pending JPS59165117A (en) 1983-03-11 1983-03-11 Digital input device

Country Status (1)

Country Link
JP (1) JPS59165117A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63204426A (en) * 1987-02-20 1988-08-24 Nec Corp Interface system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63204426A (en) * 1987-02-20 1988-08-24 Nec Corp Interface system

Similar Documents

Publication Publication Date Title
JP2009094576A (en) Signal transfer circuit
KR930009490B1 (en) Instantaneous test mode designation circuit
JPS59165117A (en) Digital input device
US8112653B2 (en) Apparatus and method of generating power-up signal of semiconductor memory apparatus
JP2009147564A (en) Signal transfer circuit
US3229112A (en) Arrangement for controlling a direct voltage source
US4230206A (en) Transistorized elevator control button
KR100206922B1 (en) Control circuit of write
US6459327B1 (en) Feedback controlled substrate bias generator
GB897532A (en) Amplifier-regulating circuits
US3010028A (en) Asynchronous to synchronous pulse converter
JP2008054042A (en) Insulated contact output circuit
JP2009181241A (en) Signal transfer circuit
JPS5917915B2 (en) signal isolation circuit
KR0137972B1 (en) Signal input device of semiconductor device
JPH0142089B2 (en)
KR100596872B1 (en) Level Tunning Circuit
US3466468A (en) Monostable controlled saturable core blocking oscillator circuit
RU1802391C (en) Device for control over multicell d c/d c converter
SU1610554A1 (en) Device for shaping thyristor control pulses
JPH0349168B2 (en)
JPH07264041A (en) Input buffer circuit
Lee A set of voltage-switched magnetic-core decoding matrices
RU1791247C (en) Track circuit receiver
JPH11185480A (en) Input buffer circuit