JPS5916423B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having a nonvolatile memory function in which stored information can be electrically written and erased.

In order to realize high-density storage capacity in semiconductor integrated circuit structures, it is necessary to improve selective etching technology, high-precision formation technology for conductive type regions, and use physical phenomena suitable for pattern placement and integrated circuit characteristics during mask design. .

A non-volatile memory device, which has a wide range of applications as a memory device, accumulates positive and negative injected charges mainly at the floating gate and trap center in the insulated gate film of an MIS field effect transistor (MIS transistor). Conventionally, in order to control the injection of digits, it was necessary to provide a memory transistor and two decode transistors, as well as an information line to control positive and negative charge injection, and because the digit lines were insulated and separated, the memory cell The disadvantage was that the structure was complex and high integration density could not be achieved. In addition, the ideal features of non-volatile storage devices are Random Access Memory (RAM) in which information can be selectively written.
The purpose of this is to have a storage function and to hold stored information in a non-volatile manner. It is therefore an object of the present invention to provide a non-volatile memory device with high integration density. Another object of the present invention is to provide a nonvolatile storage device having a high integration density, capable of selectively writing not only information "1" but also information "0" to a selected address, and equipped with a RAM function. Our goal is to provide the following. According to this invention, the memory cells arranged in the row and column direction have first and second opposite conductivity type regions on one main surface of a single conductivity type semiconductor substrate,
A drive transistor (decode transistor) having a control gate electrode coupled to a common row line for each row via an insulating gate film is formed on the surface between the first and second opposite conductivity type regions, and A memory transistor (memory transistor) in which an insulating gate film, a floating gate electrode, and a covering insulating film for the electrode are sequentially deposited on the surface between the second and Ξ chain-type regions, and another control gate electrode is provided on the upper surface. ), in which the first and Ξth opposite conductivity type regions are commonly connected to other memory cells, and the second opposite conductivity type region is connected to the semiconductor substrate. having a PN junction with a region of one conductivity type having a higher degree of conductivity than the base body in a part under the floating gate electrode,
In addition, a semiconductor device is obtained in which the other control gate electrodes are coupled to column lines for every same column. This semiconductor expansion device uses a vapor-phase growth film such as silicon oxide or alumina as the covering insulating film between the floating gate and control gate electrode of the memory transistor, so that information X1 or XO can be sent to the selected address. and information X1〃8'10''
Or non-volatile RAM that rewrites information from O'' to Sll'
is obtained. The semiconductor device of the present invention has the advantage of a high degree of integration when the memory circuit is integrated because the first and third opposite conductivity type regions are shared by adjacent memory cells. It has an excellent storage function as a programmable read-only memory (PROM) that can be erased and rewritten, or a nonvolatile RAM that can write information 11'10'' to a selected address.

Next, in order to better understand the features of this invention, examples of this invention will be explained using figures.

FIG. 1 shows a part of a circuit diagram of an embodiment of the present invention, in which N channels are set at the intersections of row lines Xi, Xi+1, Xi+2 extending in the row direction and column lines Yj, Yj+1 extending in the column direction. type memory transistor Qrrl,N
It has a memory cell consisting of a channel type decoding transistor Q, a transistor and a diode Di. The gate electrode of the memory transistor 1Qm is connected to the column lines Yj, Y extending in the column direction.
j+1 VC are commonly connected for each column and decode transistor 3
The gate electrode of tQd is connected to the row lines Xi, Xi+ extending in the row direction.
1 and Xi+2 for each row. The diode D1 is a PN junction formed by the contact between the N-type region connecting each transistor Qm, Q, and the P-type region having a higher concentration than the base on the surface of the P-type silicon substrate under the floating gate of the memory transistor. , this P-type region is led out to a base terminal SB common to the base regions of transistors Qnl and Qd. The other N-type regions of each transistor Qm, Qd are respectively led out to a common output line D, ll) along with memory cells at other addresses. FIG. 2 shows the operating voltage waveform of the first embodiment of FIG. In this figure, the applied voltage Vx to the selected row line X and the applied voltage Vy to the selected column line Y are at times Tl and t2.
, . . . , a synchronizing signal is given to T3, and the output current IDT5 flowing from terminal D to terminal D at each time is shown. Voltage is applied to the sample by applying a base voltage of -10V to the base electrode, which will be described later, and applying a voltage of V at the output terminal D. are performed by applying a DC potential of 30V to each. The other output terminal D is open in a write operation and is set to 0V in a read operation. Select 110 from time t1 to T2
``When writing is performed and pulse voltages of peak values 35V and 10V are applied to the matrix lines extending to the selected address, respectively, the decode transistor 1Qd becomes conductive and a voltage exceeding about 20V avalanche breakdown voltage is applied to the diode D1. Avalanche...High-energy electrons attracted by the positive gate electric field near the breakdown point put the floating gate in a negative charge accumulation state.At times T3-T4, this information is transferred by driving the voltages Ve and Vy to +5V. A SO'' read current 1D'T5 is applied to the read output. Furthermore, when voltage signals of 35V and -10V are applied to voltages Vx and VyVC at times T5 and T6, respectively, the diode undergoes avalanche surrender again, and under this condition, the floating gate of the memory transistor is in a positive charge accumulation state due to the effect of the negative gate electric field. becomes. When the voltages Vx and Vy of +5V are again applied to the selected matrix lines in the read operation from time T7 to T8, a read current of 111'' is obtained at the terminals D and D. FIG. 3 shows the part of the embodiment shown in FIG. A top view is shown.

Further, cross-sectional views of this plane taken along lines a-a'' and b-b' are shown in Figures 4 and 5.As shown in these figures, this embodiment has a resistivity of 4Ω-Mf) P type. The active region on one surface of the silicon single crystal substrate 1 has a surface depth of 10 to 1021 (-m-
3 N-type regions 2, 3, and 4, and a polycrystalline silicon row line X, +1 extends to the substrate surface between the N-type regions 2 and 3 via a S, O2 film 5 of approximately 1000 Af). . This row line Xi
+1 is the active region of this part and is the gate electrode of the decode transistor. A floating gate FG of polycrystalline silicon is provided on the substrate surface between the N-type regions 3 and 4 via an S, O2 film 6 of approximately 300 Å, and a silicon nitride film 7 of approximately 2000 Å is provided on the upper surface of these polycrystalline silicon. An aluminum column Yj extends through it to form a memory transistor. A junction with a P-type region 8 having a surface concentration of 6.times.10@16 to 10@18 cm@-3 is provided in a portion of the N-type region 3, which couples the memory transistor and the decode transistor, directly below the floating gate FG. As shown in FIG. 6, the memory cell shown in the embodiment of FIG. 3 to FIG. , Deco-1 driven by . It includes a card and memory transistors Qd and Qm.

The memory transistor also includes a diode Di having a reverse breakdown voltage of 10 to 22 V between the N-type region within the memory cell and the substrate SB. In FIG. 7, the memory cell in FIG. 6 is fixed at a base potential of -10V, and the potential of one output line b is fixed at 0V, and a drive signal V,
It shows the change in the gate threshold value Vt of the memory transistor when the drive signal Vg is applied to the column line Y for 1 second and the drive signal Vg is applied to the column line Y at the same time.

When the signal Vg of the column line Y is 0V, the memory transistor has the gate threshold value V,
does not change, and when the signal Vg is driven with a positive voltage, the gate threshold increases after the avalanche breakdown of the diode. or,
When the signal Vg is driven with a negative voltage and has a gate threshold corresponding to the information 0''Vc, the gate threshold drops sharply and approaches the information 1''. According to the above-described embodiment, the N-type regions D or D of each memory cell adjacent in the row direction are always shared, and there is no need for insulation separation between the memory cells, so that this semiconductor memory integrated circuit has two transistors/bit. Despite its configuration, it forms an extremely high-density memory circuit,
Moreover, it has the advantage of being able to selectively write information 111'' and 0'' to selected bits.

In addition, in order to make the gate voltage of the memory transistor positive when writing this information 1" and 1", it is preferable to use a vapor phase grown film such as a silicon nitride film or alumina film that can prevent ion drift characteristics. A membrane is provided between the floating gate and the column line Y. These vapor-phase grown films have a high dielectric constant and a low conductivity compared to thermal oxide films of polycrystalline silicon, so the gate electric field can be effectively applied to the S, O2 film between the floating gate and the substrate to improve the operating characteristics. and improve operational reliability. Also, other metal materials such as molybdenum and non-ungsten can be used for the floating gates and row lines.
FIG. 8 is a plan view of a memory cell according to another embodiment of the invention.

In this embodiment, the N-type region FJ sandwiched between the floating gate FG and the row line X between D-b of the N-type region has a memory transistor of 0 m
A low breakdown voltage diode is formed with the P-type region P at a portion away from the P-type region P. Since this diode is formed directly under the floating gate, the effect Vc is the same as that of the previous implementation, and since it is away from the operating region as a transistor, it reliably avalanches and falls at the potential of the N-type region FG. FIG. 9 is a plan view of a memory cell according to still another embodiment of the present invention, which includes a P-type region P across the channel length direction of the memory transistor Qm, and a P-type region P for the N-type regions DG and D. Form a junction.

In the PN junction, when the voltage is operated as shown in FIG. 2, the potential of the intermediate N-type region FJ is always higher than that of the N-type region 'DVC on the output line side, so there is no problem in circuit operation. In this embodiment, a high-density integrated circuit with high pattern accuracy and margin can be obtained when the channel length of the transistor is shortened.

[Brief explanation of the drawing]

FIG. 1 is a response diagram of an embodiment of the present invention, FIG. 2 is a voltage waveform diagram of the embodiment of FIG. 1, FIG. 3 is a plan view of the embodiment of FIG. 1, and FIG. 4 is a diagram of the voltage waveform of the embodiment of FIG. 5 is a sectional view taken along line bb'' in FIG. 3, FIG. 6 is an equivalent circuit diagram of the memory cell section in FIG. 3, and FIG. 8 is a plan view of another embodiment of the invention, and FIG. 9 is a plan view of still another embodiment of the invention.

Claims (1)

[Claims] 1. In a semiconductor memory device in which a plurality of memory cells are arranged in a matrix, each of the memory cells has two opposite conductivity type regions formed on a substrate of one conductivity type as a source and a drain, respectively, and the region between the source and the drain. A first insulating film is provided on the conductive type substrate, a floating gate electrode is provided on the first insulating film, a second insulating film is provided on the floating gate electrode, and the second insulating film The field effect transistor includes an insulated gate field effect transistor having a structure in which a control gate electrode is provided thereon, and a portion below the floating gate electrode between the source or the drain and the one conductivity type substrate is compared to the one conductivity type substrate. 1. A semiconductor memory device, wherein a high concentration region of one conductivity type is provided, and the second insulating film contains silicon nitride or alumina.