JPS59161949A - Loop type information transmission system - Google Patents

Abstract

PURPOSE:To secure the synchronization for the phase and the frequency in a loop transmission system by providing a buffer memory at a main station to absorb the phase difference between the reception information and the transmission information. CONSTITUTION:When the reception information RXD is supplied and the reception clock RX is supplied to a memory control circuit 14, the information RXD is written to a memory 11 by a writing address WA. While the memory 11 is read by the circuit 14 and a reading address RA while the transmission clock TXC and its 2-split clock 2TXC are kept at ''L''. Then the information TXD is transmitted, and the phase synchronization is obtained. The addresses WA and RA are compared with each other through a comparator 31, and a signal P1 is delivered when the difference between both addresses exceeds a fixed level. Then a part of a frame is deleted by a sequencer 34 for control of frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement of a Rougue type information transmission system in which a plurality of transmission stations are connected in a loop and data is transmitted between each transmission station.

[Technical background of the invention]

Conventionally, as this type of system, there is a system as shown in FIG. 1, for example. That is, this method uses a plurality of terminals la, . . . , such as facsimile IJ devices.

In, 2a, ~, 2n1..., 5a, ~5n are connected to a plurality of transmission stations 1, 2... ..., 5 are connected in a Luzo-like manner, and a main station 6 is provided within this loop.

Then, the main station 6 creates a plurality of pieces of transmission information with fixed frame lengths, and by connecting these pieces of transmission information to each other and making them circulate on a loop, data is transmitted between each transmission station. ing. FIG. 2 shows an example of the frame structure of the above-mentioned transmission information. Starting from the beginning, the synchronization flag SYN, the i9ket part P that controls the inside of the loop,
K Ding, data transmission time slot TS7, ~.

The information part (484 bytes) consisting of TS400 is arranged, and the non-information part (17 bytes) is added afterwards, a total of 5
It consists of 01 bytes.

By the way, in this type of transmission system, generally each transmission station 1, 2
．． . . , 5 causes a transmission delay during handover or on the transmission path, so a phase difference occurs between the transmitted and received transmission information at the time of rounding. This phase difference is extremely undesirable because it causes bit loss of transmitted information and causes a reduction in transmission performance.

Conventionally, for example, the main station 6 is provided with a shift register or a memory using a first-in, first-out (FIFO) method, and by temporarily storing received transmission information in these registers or FIFO memory, the phase difference between the input and output timing of the transmitted and received transmission information is reduced. It is designed to absorb noise and jitter.

[Problems with background technology]

However, if the transmission path includes a microwave line or other transmission path that is relatively prone to phase differences, the phase difference between the transmitted and received transmission information becomes extremely large and cannot be absorbed by the conventional buffer memory described above. It may disappear. In addition, in a loop type transmission system, when a certain transmission station generally becomes unable to transmit due to a failure, some downstream transmission station transmits information to the effect that the failure has occurred according to its free-running frequency to the main station. The main station sends out control information for switching transmission paths, etc.

In such a case, a frequency deviation occurs between the received transmission information and the transmitted transmission information at the main station because the received transmission information is transmitted at the free-running frequency of the transmission station, and this frequency deviation is could not be absorbed by the buffer memory.

[Purpose of the invention]

The present invention aims to provide a loop-type information transmission system that reliably absorbs even if there is a large phase difference or frequency difference between received transmission information and transmitted transmission information and has high transmission reliability. purpose.

[Summary of the invention]

In order to achieve the above object, the present invention provides a main station with a buffer memory that absorbs the phase difference between the received transmission information and the transmitted transmission information, and also sets the writing position of the received transmission information in this buffer memory and the transmitted transmission information. A means is provided to determine the phase difference between the received and sender transmitted information from the difference with the reading position of the transmitted information, and expand or contract the frame length of the transmitted transmission information depending on the magnitude of this phase difference. When the phase difference between the transmitted information reaches an amount corresponding to a predetermined frequency deviation, the frame length is changed by adjusting the slots of the non-information part of the transmitted transmission information in order to bring the frequency deviation closer to zero. υIt is designed to absorb large phase differences and frequency deviations.

[Embodiments of the invention]

FIG. 3 is a circuit diagram showing the parts related to the present invention of a main station to which a loop type information transmission method is applied in one embodiment of the present invention, in which 10 is a buffer memory circuit, 30 is a frame expansion/compression circuit, and 40 is a circuit diagram showing parts related to the present invention. Loop control circuits are shown respectively.

First, the buffer memory circuit 10 has a random access
A memory 11 consisting of a memory (RAM), an address specifying section 12 that specifies a write address and a read address for this memory 11, and the memory 1
A transmission information input/output unit 13 supplies received transmission information to the memory 1 and outputs transmitted transmission information from the memory 1, and a memory control circuit 14 specifies write and read modes of the memory 1. It is configured.

The addressing unit 12 includes two counters, a receive byte counter 15 and a transmit byte counter 16, a selector 17 that selectively supplies the outputs of these counters 15 and 16 to the memory 1, and the transmit byte counter It is composed of a latch circuit 18 that sets an initial value for the counter 16. The received byte counter 15 divides the received clock RXC by IA by the frequency divider 19, counts the clock with one period for one byte, and outputs the counted value as the write address WA. On the other hand, the transmission bite counter 16 receives the transmission clock T generated from the oscillation circuit 50.
XC is counted and the counted value is output as a read address RA.

The transmission information input/output unit 13 sends the received transmission information RXD to S/P.
After converting the serial data into 79 parallel data using the converter 20, it is supplied to the memory 11 via the dart circuit 21, and the transmission information read from the memory 11 is latched by the latch circuit 22 after passing through the dart circuit 21. It is configured to output the data to a transmission circuit (not shown) as transmission data.

The memory control circuit 14 is configured as shown in FIG. 4, for example. That is, in this circuit 14, the rising edge of the reception clock RXC is the flip-flop 7'23.
A and the AND dart 23b are detected, and at the time of detection, the f-to signal WRY is generated from the free lag flop 24m, and the NAND dart 24b is opened only during the generation period of this dart signal Vl/RY. And this Nantes Gate 2
The 2-frequency divided clock 2 TXC that has arrived during the opening period of 4b is outputted as a write designation signal WC, and the trailing edge of this signal WC is detected by a differentiating circuit 25 and the detection output WEND is used to output each of the above-mentioned 7 lip-frogs 23a.

24m has been reset. Note that the frequency-divided clock 2 TXC is generated by dividing the transmission clock TXC by two, and is generated from the oscillation circuit 50. Further, the memory control circuit 14 detects the falling edge of the transmission clock TXC using a graph frog 26, and uses the detection output to open the NAND dart 27 to pass the inverted output of the frequency-divided output 2TXC. Then, this passed frequency-divided output 2 TXC is outputted as the read designation signal RC after passing through the AND/DART 28. In addition, the above Nantes Gate 2
When the output divided by 7 to 2' is sent out, its trailing edge is detected by the differentiating circuit 29, and the shift flip-flop 26 is reset by the detection output REND.

Next, the frame expansion/contraction circuit 30
an address comparator 3 which compares the write address and read address output from the reception byte counter 15 and the transmission byte counter 16, the address comparator 31f), the address detection circuit 32 which sets the comparison timing, and the transmission a transmission frame counter 33 that counts the number of transmission frames by counting the clock TXC;
Sequencer 3 that configures the frame of transmission transmission information TXD
It is composed of 4.

The address detection circuit 32 monitors the read address output from the transmission byte counter 16 and issues a detection signal when the address becomes '0', and uses this detection signal as a comparison timing signal to the address comparator 31. This is used to perform address comparison.

Next, the loop information transmission system in this embodiment will be explained based on the above configuration. First, in a normal transmission operation state, the phase difference between the transmitted transmission information TXD and the received transmission information caused by the receiving and passing operations of each transmission station and the state of the transmission path is absorbed as follows.

That is, the memory control circuit 1 of the buffer memory circuit 10
4, the transmission clock generated from the oscillation circuit 50, TX
C and its 2 frequency divider No. 2 TXC are respectively supplied. When the received transmission information RXD arrives in this state and its received clock RXC is input to the memory control circuit 14, the memory control circuit 14 starts the rising of the received clock RXC as shown in the operation timing of FIG. A dirt signal is detected, and a dirt signal W is generated from that point on.

After the dart signal Vl/RY is generated, the H'' level period of the first input frequency-divided signal 2TXC is outputted as the write designation signal WC and supplied to the memory 11.

Also, at this time, the write address WA of the received byte counter 15 is supplied to the memory 1 via the selector 17. Therefore, the memory 1 can be written to during the period specified by the write designation signal WC9, and as a result, the received transmission information RXD is sequentially written to the specified address of the memory 1 for each bit within the write designation period. will be written to. Note that once the above writing period has elapsed, the dirt signal V/RY remains at the I L n level, and from then on, the next reception information bit arrives until the next rising edge of the reception clock RXC is detected. The "L" level is maintained until Therefore, writing to memory 1 during this period is prohibited by 1-.

On the other hand, during the period when the transmission clock TXC is at the "L" level and the frequency-divided signal 2 TXC is at the "Ll level", the memory control circuit 14 generates the read designation signal RC as shown in FIG. is in read mode. As a result, from memory 1, the transmitted byte counter 16
The transmission information TXD is read out one bat at a time in accordance with the read address RA specified by , and is sent out to the υ transmission line from a transmission circuit (not shown) at regular intervals as shown in FIG. Thus, the phase difference between the received transmission information RXD and the transmitted transmission information TXD is absorbed. Furthermore, in the above configuration, a general-purpose RAM is used as the memory 1, and this RAM
Since the write period and read period of M are each limited to 1/4 of the 1 btt period of the transmission information and are set to be independent from each other, ・Compared to the case where a ring shift register or FIFO memory is used as the grapher memory, , it is possible to perform buffer operation at high speed with a simple configuration.

By the way, if the phase difference between the transmission and reception timing becomes very large υ, or if any transmission station in the route becomes unable to transmit during the above transmission operation, this causes the transmission station downstream of this failed transmission station to If the main station transmits information indicating that a fault has occurred according to the free-running frequency, a frequency deviation will occur between the fault information, which is received transmission information, and the transmitted transmission information at the main station, and the buffer memory circuit 10 described above will It becomes impossible to absorb the above frequency deviation.

However, in this embodiment, the write address WA of the receive byte counter 15 and the read address RA of the transmit byte counter 16 are compared by the address comparator 3, and the length of the transmit transmission information TXDO frame is expanded or contracted according to the comparison result. It will be done.

For example, if the reception clock frequency of the received transmission information becomes high and the difference between the p write address and the read address becomes more than a predetermined amount, then the address comparator 3
A signal P1 for shortening the frame length of the transmitted transmission information is outputted from No. 1 and supplied to the sequencer 34. As a result, the sequencer 34 constructs a frame by deleting 1 digit from the non-information portion located at the rear end of the transmission information to be transmitted next, and sends it out from the transmission circuit. Thus, the frequency deviation between the transmitted transmission information and the received transmission information is absorbed as a result. Therefore, the problem that the write address and read address of the memory 1j match and transmission information is lost can be reliably prevented. vice versa,
When the reception clock frequency becomes low, the address comparator 3 issues a signal P2 to extend the frame length, and a long frame with 1 byte of non-information added to the non-information portion is transmitted to the transmission path. Information is sent. Note that the above frame expansion/contraction operation is performed until the interval between the input address and the read address becomes the maximum, assuming that the memory 1 is a read/write memory. This is because when a frequency deviation or a large phase difference occurs, it is most difficult for the write address and read address to match.

By the way, when you expand or contract the frame length as described above,
It is also necessary to set the read address RA in memory 1 along with LK. On the other hand, in this embodiment (is the synchronization flag RX-SYN of the reception transmission information RXD).
When the write address WA is received, the write address WA is loaded into the latch circuit 18, and at the start of transmission of the received transmission information RXD, the loaded address is loaded into the transmission byte counter 16, and the read address of the memory 11 is set as the initial RX. I'm trying to set it up. Therefore, even if the frame length is expanded or contracted as described above, all data can be reliably transmitted.

As described above, with the method of this embodiment, if the phase difference between the transmission and reception timing exceeds the absorption capacity of the buffer memory circuit 10, or if a failure occurs in the loop, this will cause reception and transmission using the free-running frequency. Even if information arrives, the frame length is expanded or contracted by reducing and adding multiple pieces of non-information in the transmitted information, so loop transmission can always be performed reliably without loss of information.

In addition, when the loop system starts operating or recovers,
Linking between frames of transmission information transmitted in a loop can also be performed reliably and easily by expanding and contracting the frame length, and furthermore, the number of frames existing in the loop can be easily optimized. In addition, since a general-purpose RAM can be used as the buffer memory circuit by devising write and read operations, it is possible to realize a high-speed buffer operation with a simpler configuration than that using a shift reno star or FIFO memory.

Note that the present invention is not limited to the above embodiments.

For example, a means for setting whether to utilize the )9777 function or to pass it may be added, so that the main station is not fixed and the main station is contended for when the system starts operating. In addition, the configuration of the buffer memory circuit, the configuration of the frame expansion/contraction circuit, etc. can be modified in various ways without departing from the gist of the present invention.

〔Effect of the invention〕

As described in detail above, the present invention provides a main station with a buffer memory that absorbs the phase difference between the received transmission information and the transmitted transmission information, and also sets the position where the received transmission information is saved in the buffer memory and the transmitted transmission information. The means fR calculates the phase difference between the received and sender transmitted information from the difference with the reading position of the transmitted information, and compresses the frame length of the transmitted transmitted information according to the magnitude of this phase difference. When the phase difference between the transmitted information reaches an amount equivalent to a predetermined frequency deviation, the frame length is varied by adjusting the slots of the non-information part of the transmitted information in order to bring the frequency deviation closer to zero. It is 1-layered to absorb phase differences and frequency deviations.

Therefore, according to the present invention, even if there is a large phase difference between received transmission information and transmitted transmission information, or even if there is a frequency deviation, these can be reliably accommodated and the loop-type information transmission with high transmission reliability can be achieved. method can be provided.

[Brief explanation of the drawing]

1 and 2 are for use in explaining the conventional technology; FIG. 1 is a block configuration diagram of a loop type information transmission system, FIG. 2 is a frame configuration diagram of transmission information used in the system, Figures 3 to 5 are for explaining one embodiment of the present invention. Figure 3 is a block diagram showing the main part analysis of the main station to which the loose type information transmission method is applied, and Figure 4 is A circuit configuration diagram of the memory control circuit, and FIG. 5 is an operation timing diagram of the buffer memory circuit. 10...Buffer memory circuit, 11...Memory (R
AM), 12...address designation section, 13...transmission information input/output section, 14...memory control circuit, 15...
Received byte counter, 16...Sent byte counter,
17...Selector, 18...Latch circuit, 19...
・IA frequency divider, 30...frame expansion! Circuit, 31...
- Comparison circuit, 32... Comparison timing setting circuit, 33
...Transmission 7 frame counter, 34...Sequencer,
35...address detector, 5o...oscillation circuit.

Claims (2)

[Claims] (1) Multiple transmission stations including one main station are connected in a loop, and multiple pieces of transmission information with fixed frame lengths are interconnected and circulated on this loop, and the data between each transmission station is In a loop type information transmission method for performing transmission, the main station includes a buffer memory that absorbs the phase difference in input/output timing between received transmission information and transmitted transmission information, and the reception is determined by the write and read operation timing of this buffer memory. means for detecting a phase difference in input/output timing between transmitted transmission information; 1. A loop information transmission system characterized by comprising means for expanding and contracting the frame length by adjusting the number of slots. (2) The buffer memory has a storage means consisting of a random access memory, divides the output clock signal which determines the output timing of the transmission information by two, and writes one level of the divided output as the specified period. At the same time, two writing designated periods and two reading designated periods are set for each 1-bit period of the transmitted transmission information, with the other level as the read designated period, and when writing the received transmission information to the storage means, the above two writing periods are set. Select one of the specified periods that is included in the 1-bit period of the received transmission information and write in this period, and when reading, specify one of the two read specified periods for each bit. The loop type information transmission system according to claim 1, wherein reading is performed during the lever period and transmission information with a constant bit period is transmitted.