JPS59161195A - Differential signal detecting circuit - Google Patents
Differential signal detecting circuitInfo
- Publication number
- JPS59161195A JPS59161195A JP58034587A JP3458783A JPS59161195A JP S59161195 A JPS59161195 A JP S59161195A JP 58034587 A JP58034587 A JP 58034587A JP 3458783 A JP3458783 A JP 3458783A JP S59161195 A JPS59161195 A JP S59161195A
- Authority
- JP
- Japan
- Prior art keywords
- current
- voltage
- mirror
- differential signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M19/00—Current supply arrangements for telephone systems
- H04M19/001—Current supply source at the exchanger providing current to substations
- H04M19/005—Feeding arrangements without the use of line transformers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Signal Processing (AREA)
- Interface Circuits In Exchanges (AREA)
- Devices For Supply Of Signal Current (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、差動信号検出回路に係シ、さらに詳しくは、
電話交換機等の加入者回路に設けられ、半導体集積回路
化に好適な差動信号検出回路に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a differential signal detection circuit, and more specifically,
The present invention relates to a differential signal detection circuit that is installed in a subscriber circuit such as a telephone exchange and is suitable for semiconductor integrated circuit implementation.
第1図は従来技術における電話交換機の加入者回路の構
成を示したものであって、同図において、VIIEは電
池、1は直流に対しては低インピーダンスであり、交流
に対しては高インピーダンスを示す電流供給回路、3は
加入者端末であシ、線路抵抗4を介して交換機側と接続
される。5〜8は抵抗、9は演算増幅器を示し、これら
によって差動増幅器を構成し、線路側に現われる2線差
動信号の検出と、加入者端末3と電流供給回路1間で形
成される直流ループ監視用の直流電圧の検出をも行なっ
ている。Figure 1 shows the configuration of a subscriber circuit of a telephone exchange in the prior art. In the figure, VIIE is a battery, 1 is a low impedance for direct current, and high impedance for alternating current. A current supply circuit 3 is a subscriber terminal, and is connected to the exchange side via a line resistor 4. 5 to 8 are resistors, and 9 is an operational amplifier. These constitute a differential amplifier, and are used to detect the two-wire differential signal appearing on the line side and to detect the direct current generated between the subscriber terminal 3 and the current supply circuit 1. It also detects DC voltage for loop monitoring.
第1図に示す構成によると、電池p−nn0値が太きく
(−48V)、しかも2線側に発生する同相雑音電圧
が太きb等のために、低消費電力と、良好な同相雑音抑
圧のためには、差動増幅器を構成する抵抗5〜8に高精
度、高抵抗を用いる必要があり、モノシリ゛ツク半導体
集積回路化するには適して込なかった。According to the configuration shown in Fig. 1, the battery p-nn0 value is large (-48V), and the common-mode noise voltage generated on the 2nd wire side is large, etc., resulting in low power consumption and good common-mode noise. In order to suppress this, it is necessary to use high precision and high resistance for the resistors 5 to 8 constituting the differential amplifier, which is not suitable for fabrication into a monoseries semiconductor integrated circuit.
本発明の目的は、前記した従来技術における欠点をなく
し、電話交換機等を電子化するに必要な加入者回路をモ
ノシリツク半導体回路化し、かつ、低コストで高精度化
することKある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, to convert subscriber circuits required for electronic telephone exchanges into monolithic semiconductor circuits, and to achieve high accuracy at low cost.
本発明による差動信号検出回路は、2線電圧を検出する
互いに相補な第1j第2のカレントミラーと1.その第
1カレントミラーの出力電流を反転する第3のカレント
ミラーと、第1.第2のカレントミラーの電流に比例し
た電圧と電流を発生する2個の出力と基準入力をもつ互
すに等価な一対の電圧電流発生器↓シ成シ、2線電圧に
生ずる同相雑音を抑制するように、前記電圧電流発生器
の電流出力を互いに接続して差動電流検出回路を構成し
、前記電圧電流発生器の一方の基準入力端子を他方の電
圧出力端子に接続し、一方の電圧出力端子から差動電圧
検出出力を取出す構成を特徴とするものである。The differential signal detection circuit according to the present invention includes a 1j-th second current mirror that detects a two-wire voltage, and 1. a third current mirror that inverts the output current of the first current mirror; A pair of mutually equivalent voltage and current generators with two outputs and a reference input generate a voltage and current proportional to the current of the second current mirror, suppressing common mode noise occurring in the two-wire voltage. The current outputs of the voltage and current generators are connected together to form a differential current detection circuit, and one reference input terminal of the voltage and current generator is connected to the voltage output terminal of the other, and one voltage This device is characterized by a configuration in which a differential voltage detection output is taken out from the output terminal.
以下、第2図〜第4図に従って本発明の一実施例を詳述
する。第2図は加入者回路の具体的な構成を示したもの
であって、第1図と同一符号を付しであるものは同一機
能を有するものである。第2図において、10.11は
線路に設けた抵抗、 12.13.14はカレントミラ
ーを示し、抵抗10とカレントミラー12によってB線
側(端子Bで示す)の電圧を検出し、抵抗11とカレン
トミラー13はA線側(端子Aで示す)の電圧を検出す
るものである。Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4. FIG. 2 shows a specific configuration of the subscriber circuit, and components having the same reference numerals as those in FIG. 1 have the same functions. In Fig. 2, 10.11 is a resistor provided on the line, 12.13.14 is a current mirror, and the voltage on the B line side (indicated by terminal B) is detected by the resistor 10 and the current mirror 12. The current mirror 13 detects the voltage on the A line side (indicated by terminal A).
このカレントミラー12の具体的な構成は第3図(α)
、 (blに示す様であり、入力電流11Nに比例し・
た出力電流10UTを生じる機能を有し、トランジスタ
17’r、 2Tr fi”第3図(Alの如く接続し
て成る。The specific configuration of this current mirror 12 is shown in FIG. 3 (α).
, (as shown in bl, and is proportional to the input current of 11N.
It has the function of generating an output current of 10 UT, and is composed of transistors 17'r and 2Tr fi'' (FIG. 3) connected as shown in FIG.
またカレントミラー13の具体的な構成は第4図体)、
(blに示す様で−あシ、このカレントミラー、 3
。The specific configuration of the current mirror 13 is shown in Figure 4).
(As shown in BL-Ashi, this current mirror, 3
.
13はカレントミラー12と相補な特性を持つもので、
第4図(Alに示す如(トランクiり’ 57’r、
4Trを図示の如く接続して成る。13 has characteristics complementary to the current mirror 12,
Figure 4 (as shown in Al) (trunk i'57'r,
It consists of 4Tr connected as shown.
さらに第2図において、15.17はトランジスタを示
し、トランジスタ15は出力電流10UT″が出力され
る端子20にコレクタが接続され、ベースは接地される
。このコレクタはトランジスタ17のコレクタと接続さ
れ、エミッタは抵抗16ヲ介してトランジスタ170ベ
ースに接続される。Furthermore, in FIG. 2, 15.17 indicates a transistor, the collector of the transistor 15 is connected to the terminal 20 from which the output current 10UT'' is output, and the base is grounded. This collector is connected to the collector of the transistor 17, The emitter is connected to the base of transistor 170 via resistor 16.
一方のトランジスタ17のエミッタは抵抗18を介して
差動信号出力端子19に接続される。トランジスタ17
0ベースはカレントミラー13の出方端子に接続され、
抵抗18を介してトランジスタ17のエミッタはカレン
トミラー′14の出力端子に接続される。さらに、カレ
ントきラー12の出力端子はカレントミラー14の入力
端子に接続しである。The emitter of one transistor 17 is connected to a differential signal output terminal 19 via a resistor 18. transistor 17
0 base is connected to the output terminal of the current mirror 13,
The emitter of transistor 17 is connected via resistor 18 to the output terminal of current mirror '14. Furthermore, the output terminal of the current killer 12 is connected to the input terminal of the current mirror 14.
第2図の如き構成における動作を説明すると、まず加入
者端末3より発生する2線差動信号電流は実線矢印・i
dで示すようK、カレントミラー、4 。To explain the operation in the configuration as shown in FIG. 2, first, the two-wire differential signal current generated from the subscriber terminal 3 is
K, current mirror, 4 as shown in d.
12.1!Sを流れ、カレントミラー12の出力電流は
カレントミラー14により電流反転され、抵抗18とト
ランジスタ17ヲ流れる。カレントミラー13の出力電
流は抵抗16とトランジスタ15に流れる。12.1! The output current of the current mirror 12 is reversed by the current mirror 14, and flows through the resistor 18 and the transistor 17. The output current of current mirror 13 flows through resistor 16 and transistor 15.
すなわち、抵抗16にカレントミラー13の電流に比例
した電圧が発生しており、トランジスタ15のコレクタ
からはカレントミラー13の電流と等しい電流が出力さ
れる。また、トランジスタ15のベースは抵抗16の電
圧降下の基準点を与える基準入力となっている。いわば
、トランジスタ15と抵抗16はトランジスタ15のコ
レクタを電流出力とし、ベースを基準入力とし抵抗16
のトランジスタ15のエミッタに接続される端子とは反
対側の端子を電圧出力とする電圧電流発生器を構成して
いると言える。That is, a voltage proportional to the current of the current mirror 13 is generated in the resistor 16, and a current equal to the current of the current mirror 13 is output from the collector of the transistor 15. Further, the base of the transistor 15 serves as a reference input that provides a reference point for the voltage drop across the resistor 16. In other words, the transistor 15 and the resistor 16 use the collector of the transistor 15 as a current output, the base as a reference input, and the resistor 16 as the collector.
It can be said that a voltage and current generator is configured in which the terminal opposite to the terminal connected to the emitter of the transistor 15 outputs a voltage.
トランジスタ17と抵抗18による回路も同様に、カレ
ントミラー14に流れる電流、すなわちカレントミラー
12に流れる電流に比例した電圧と電流を発生する電圧
電流発生器を構成している。Similarly, the circuit including the transistor 17 and the resistor 18 constitutes a voltage/current generator that generates a voltage and current proportional to the current flowing through the current mirror 14, that is, the current flowing through the current mirror 12.
そして、その基準入力端子はトランジスタ15と抵抗1
6による電圧電流発生器の電圧出力端子に接続されてい
ることになる。The reference input terminal is a transistor 15 and a resistor 1.
6 is connected to the voltage output terminal of the voltage and current generator.
ここで、抵抗16.18の抵抗値を等しくRとし、差動
電流fidとすると、上述のように抵抗16゜18には
同一極性でRitLの電圧降下が生じ、出力端子19に
は2Ridの差動信号電圧が生じる。一方、トランジス
タ15.17のコレクタ電流も同一極性であることから
出力端子20には2idの差動信号電流が生じる。ここ
で、線路抵抗4に容量性の結合等によシ図の点線itで
示す同相雑音電流が生じたとすると、カレントミラー1
2に入力する同相電流成分が反対方向となるので、抵抗
16゜17に生じる同相電圧は逆極性となり、出力端子
19には同相成分は生じガい、同様にトランジスタ15
.17のコレクタ電流に生じる同相電流成分も逆極性と
なるので出力端子20には同相雑音電流は生じない。す
なわち、2個の差動信号出力端子19.20からは差動
信号のみが検出され同相雑音信号が抑圧されることにな
る。第2図の回路構成では加入者端末3が開放状態の場
合はカレントミラー12.13には電流が流れないので
、差動信号電圧、電流を発生するトランジスタ15゜1
70消費電力もほぼゼロとなシ、従来例のように消費電
力低減のために高抵抗を用いる必要はなく、モノリシッ
ク半導体集積回路化が容易となる利点が生じる。さらに
、カレントミラー12゜13のミラー比〔出力電流(I
ovr)/入力電流CIIn))を適当に選ぶことによ
って出力端子19の電圧変動範囲を半導体集積回路化し
やすい低い値にすることが可能であり、さらに、上述し
たように出力端子9では同相雑音が抑圧されるので従来
例のように演算増幅器を用すて同相抑圧能力を改善する
必要はなく、回路が簡単となる利点もある。さらに、第
2図では電圧出力とは別に電流出力も取シ出せるので回
路設計上の自由度が増す利点も生じる。たとえば、出力
端子19は2線信号の検出に用い、出力端子20はルー
プ監視検出用に用いる方法等が好適な例とし考えられる
。Here, if the resistance values of the resistors 16 and 18 are equal to R and the differential current fid, a voltage drop of RitL occurs with the same polarity at the resistors 16 and 18 as described above, and a difference of 2Rid occurs at the output terminal 19. A dynamic signal voltage is generated. On the other hand, since the collector currents of the transistors 15 and 17 have the same polarity, a 2id differential signal current is generated at the output terminal 20. Here, if a common mode noise current shown by the dotted line it in the diagram occurs in the line resistance 4 due to capacitive coupling, etc., the current mirror 1
Since the common mode current component input to the transistor 2 is in the opposite direction, the common mode voltage generated at the resistor 16°17 has a reverse polarity, and no common mode component is generated at the output terminal 19.
.. Since the common mode current component generated in the collector current 17 also has the opposite polarity, no common mode noise current is generated at the output terminal 20. That is, only the differential signal is detected from the two differential signal output terminals 19 and 20, and the common mode noise signal is suppressed. In the circuit configuration shown in FIG. 2, when the subscriber terminal 3 is in an open state, no current flows through the current mirrors 12 and 13.
70, the power consumption is almost zero, there is no need to use a high resistance to reduce power consumption as in the conventional example, and there is an advantage that it is easy to form a monolithic semiconductor integrated circuit. Furthermore, the mirror ratio of the current mirror 12°13 [output current (I
By appropriately selecting ovr)/input current CIIn)), it is possible to reduce the voltage fluctuation range of the output terminal 19 to a low value that is easy to integrate into a semiconductor integrated circuit.Furthermore, as mentioned above, the common mode noise at the output terminal 9 can be reduced. Since it is suppressed, there is no need to use an operational amplifier to improve the common mode suppression ability as in the conventional example, and there is also the advantage that the circuit can be simplified. Furthermore, in FIG. 2, a current output can be taken out in addition to a voltage output, which has the advantage of increasing the degree of freedom in circuit design. For example, a suitable example may be a method in which the output terminal 19 is used for detecting a two-wire signal and the output terminal 20 is used for loop monitoring detection.
なお、上述の実施例では、回路構成要素とし、 7 。In the above embodiment, the circuit component is 7.
てバイポーラトランジスタを用いて説明したが、これと
同等の動作をする他の機能素子(例えば電界効果トラン
ジスタ)や機能ブロック(演算増幅器子トランジスタ)
を用いても本発明が実施可能であるのは明らかであろう
、また、第2図のカレントミラー13とカレントミラー
14の出力を入れ替えた回路構成によっても本発明が実
施可能であるのは明らかであろう。Although the explanation was given using bipolar transistors, other functional elements (e.g. field effect transistors) and functional blocks (operational amplifier child transistors) that operate in the same way as bipolar transistors can also be used.
It is obvious that the present invention can be carried out by using a circuit configuration in which the outputs of the current mirror 13 and the current mirror 14 shown in FIG. Will.
上述の実施例からも明らかなように本発明によれば、電
話交換機等の加入者回路をモノシリツク半導体集積回路
化が低コストで、しかも高精度のものが実現できるとい
う利点がある。As is clear from the embodiments described above, the present invention has the advantage that subscriber circuits such as telephone exchanges can be implemented as monolithic semiconductor integrated circuits at low cost and with high accuracy.
第1図は従来の電話交換機における加入者回路の構成図
、第2図は本発明の一実施例を示す加入者回路の具体的
な回路構成図、第5図(α)。
(J)並びに第4図(α)、(A)は第2図に示す一部
回路の具体的な回路構成を示す図である。
1・・・電流供給回路 3・・・加入者端末、 8
。
4、10.11.16.18・・・抵抗12.13.1
4川カレントミラー
15.17・・・トランジスタ Vnn・・・電池嶌
1 図
嶌 2 図
15 14
嶌 3 喝
(o−)(b)
峯 、41!1
3
(とス−) (bン606−FIG. 1 is a block diagram of a subscriber circuit in a conventional telephone exchange, FIG. 2 is a specific circuit block diagram of a subscriber circuit showing an embodiment of the present invention, and FIG. 5 (α). (J) and FIGS. 4(α) and (A) are diagrams showing specific circuit configurations of some of the circuits shown in FIG. 2. 1... Current supply circuit 3... Subscriber terminal, 8
. 4, 10.11.16.18...Resistance 12.13.1
4 River current mirror 15.17...Transistor Vnn...Battery 1 Figure 2 Figure 15 14 3 O-(b) Mine, 41!1 3 (Tosu-) (b-606-
Claims (1)
あって1.2線電圧を検出するための互いに相補な第1
と第2のカレントミラーと、咳第1のカレントミラーの
出力電流を反転する第3のカレントミラーと、前記第1
.第2のカレントミラー各々に流れる電流に比例した電
圧と電流を発生し、2個の出力と基準入力をもつ互すに
等価な一対の電圧電流発生器を備えて成)、2線電圧に
生じる同相雑音を抑圧するように前記一対の電圧電流発
生器の電流出力を互いに接続して差動電流検出回路を形
成し、前記電圧電流発生器の一方の基準入力を他方の電
圧出力に接続し、該一方の電圧出力から差動電圧検出出
力を取出すように構成したことを特徴とする差動信号検
出回路。A differential signal detection circuit in a subscriber circuit such as a telephone exchange, in which first and second lines complementary to each other are used to detect 1 and 2 line voltages.
and a second current mirror; a third current mirror that inverts the output current of the first current mirror; and a third current mirror that inverts the output current of the first current mirror.
.. The second current mirror generates a voltage and current proportional to the current flowing through each, and includes a pair of mutually equivalent voltage and current generators having two outputs and a reference input, and generates a two-wire voltage. forming a differential current detection circuit by connecting the current outputs of the pair of voltage and current generators to each other so as to suppress common mode noise, and connecting the reference input of one of the voltage and current generators to the voltage output of the other; A differential signal detection circuit characterized in that it is configured to extract a differential voltage detection output from the one voltage output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3458783A JPH0646756B2 (en) | 1983-03-04 | 1983-03-04 | Differential signal detection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3458783A JPH0646756B2 (en) | 1983-03-04 | 1983-03-04 | Differential signal detection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59161195A true JPS59161195A (en) | 1984-09-11 |
JPH0646756B2 JPH0646756B2 (en) | 1994-06-15 |
Family
ID=12418450
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3458783A Expired - Lifetime JPH0646756B2 (en) | 1983-03-04 | 1983-03-04 | Differential signal detection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0646756B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5654160A (en) * | 1979-10-11 | 1981-05-14 | Oki Electric Ind Co Ltd | Interface circuit for subscribing line |
-
1983
- 1983-03-04 JP JP3458783A patent/JPH0646756B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5654160A (en) * | 1979-10-11 | 1981-05-14 | Oki Electric Ind Co Ltd | Interface circuit for subscribing line |
Also Published As
Publication number | Publication date |
---|---|
JPH0646756B2 (en) | 1994-06-15 |
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