JPS59160892A - Prom device - Google Patents

Abstract

PURPOSE:To prevent the increase of power to write in an unselected state even when memory capacity increases by supplying a high voltage for writing to a writing circuit part through plural switching transistors (TR) connected in parallel and controlling the plural switching TRs by an address signal. CONSTITUTION:When the most significant digit bit of an address is at a level 1, a charge pump circuit 8 is operated by a control signal C1 and a charge pump circuit 9 is not operated by a control signal Ctheta. Therefore, Vpp'1 is held at a level Vpp and Vpp'theta is at a level theta. On the other hand, the most significant digit bit of the address is at a level 0, the charge pump circuits operate reversely; and the Vpp'1 is at the level theta and the Vpp'theta is at the level Vpp. Therefore, the Vpp' varies between the levels theta and Vpp according to the most significant digit bit delta, 1 of the address. Namely, the Vpp' in the half area of memory capacity varies between the levels theta and Vpp. Therefore, even when the half area of the memory capacity is in a writing mode, a write current is not conducted to reduce the power consumption for writing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an F ROM 2, particularly an ultraviolet erase type PRO.
It belongs to M.

Normally, I) When writing a take to ROM, select one address, set a take for one word, and set the number pulse to 4F.
The take is actually loaded by applying the =' sign. At this time, a rich voltage (hereinafter abbreviated as vpp') is applied to the control gate voltage of the memory cell group (memory cells for one word) corresponding to the selected address, and this Vl
) The information generated by the high-speed turtle world is stored in the floating cage.

In order to prevent programming from occurring in other non-selected address groups, only voltages close to θ■ are applied to the control gate voltages of the memory cell groups corresponding to these address groups. When the F ROM with a memory capacity of N (natural number) words is in the storage state, the control gate of the memory cell group for l words is applied, and the other N-1 words are controlled. A voltage close to θV is applied to the control gates of the memory cell group.

The circuit shown in FIG. 1 is usually used as a circuit for controlling the voltage of the control gate of the memory cell 1, that is, the voltage of the control gate of the memory cell 1, that is, the voltage of the word νVL. In order to make the pressure close to θV, it is necessary to flow a current from PH depletion type transistor 2 to depletion type transistor 3 to transistor 4 to form a tecode to GND.

Therefore, as the memory capacity increases, the current flowing through the write circuit of the unselected memory cell group increases, which is undesirable. For example, when the current of the write circuit increases, it becomes necessary to increase the wiring width of the embedded voltage supply line1, and the capacity of the power supply for the write voltage also needs to be increased, and furthermore, the power of the FROM chip increases. This causes inconveniences such as increased heat generation.

The book is that even if the amount of memory increases while looking at the point during the rush method of the above-mentioned Ic, the power of looking at the evil in the form of non-reduction is t・n7
Add 2 P i < (It is intended to be a capital that serves 4 villages.

In other words, the high voltage of 7% is connected in parallel with several ft f (switch transistors are supplied through the 7 circuits, and several switch transistors are connected in parallel). 41 is a spider equipped with a 1M circuit controlled by an address signal, which supplies a fixed voltage only to the area in the crowded state, and spreads it to other areas of the area that are not selected. It's something that eliminates the extra current that comes with it.

Next, we will explain in detail using 11 pieces of ψ.

In FIG. 2, 8.9 is a known charge pump circuit which controls a switch transistor 6.7. Here, the t-included voltage VpI)' is the switch transistor 6
．． In order to prevent the pressure from dropping by the value 'j-' of 7, a charge pump circuit 8.7 is used.

Historically, the charge pump circuit corresponds to the most significant hit of the address and is inversely controlled by the six control numbers CI and Cθ. Example λ
If the upper bit of the address is taken, the /L level is 5, which corresponds to the area corresponding to that address, which corresponds to the area of the memory cell group kl in FIG. p p', is given by 4P1. When the most significant bit of the address is at the Nv〃 level, it corresponds to the area [■] of the 3rd mail 7, and writing to that area ``Fh pressure is Vl) [)''
θ is supplied.

Now, when the most significant bit of the address is at the StlIt level, the charge pump circuit 8 operates due to C1, and the charge pump circuit 9 does not operate due to the control signal C0Vc. Therefore, Vpp; becomes the Vl)J) level, and Vl)I)'θ becomes the "6" level.On the other hand, when the most significant bit of the address is the SSvtt level, it is completely inverse as above, ■pp The tube ?θ〃 level, Vpp'+ becomes the Vl)p level.

Therefore, VpP' shown in FIG.
．． Nos + (j〃, according to Qi〃, ant θ〃 level, vpp
Level changes. That is, Vp of 1/2 area of memory capacity
It changes to p/gari〃 level and Vri p level. Therefore, even when 1/2 of the memory capacity is written, the saved current is no longer θIC, and the saved power can be reduced.

On the flow side, the VII) I) line is divided into two by two switch transistors, but if it is further divided into four, the convolution is 1D and the power loss can be further reduced. In the above embodiment, charge pumps are provided individually, but it is also possible to use a common charge pump and control the output of the charge pump.

FIG. 3 is a diagram illustrating the relationship between the memory cell group on the actual flow side and the blue ′[K pressure].

Here, 1...memory cell, 2...depression type load transistor, 3...depression type control transistor, 4...ennome type Transistor, 5...depression type load transistor p, 6.7...enhancement type switch transistor, 8.9...
・It is a charge pump circuit.

Figure 1 Figure 2 Vpp’o VPP’1 Figure 3 1111/FP’0

Claims (1)

[Claims] The writing cylinder pressure is supplied to the false write circuit section via several switch transistors connected in series.
FROMMo is characterized by having a circuit in which a number of switching transistors are controlled by an address signal.