JPS59160772A - Line abnormality detector - Google Patents
Line abnormality detectorInfo
- Publication number
- JPS59160772A JPS59160772A JP59030851A JP3085184A JPS59160772A JP S59160772 A JPS59160772 A JP S59160772A JP 59030851 A JP59030851 A JP 59030851A JP 3085184 A JP3085184 A JP 3085184A JP S59160772 A JPS59160772 A JP S59160772A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- transistor
- becomes
- state
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Locating Faults (AREA)
- Tests Of Electronic Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は各種設備の監視装置における線路異常を検出す
る装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for detecting line abnormalities in monitoring devices for various types of equipment.
従来例の構成とその問題点
従来のこの種の装置を第1図に示す。この装置は端子A
、B間の線路等の入力抵抗Rの変化によす、トランジス
タT R,、TR2の状態が決まり、トランジスタTR
2の状態によシトランジスタTR3が動作し、端子Cに
生ずる出力が変化する。例えば入力抵抗Rが正常時(約
4000)の場合にA点の電圧はR=i= 2 R1と
した場合約4vとなる。但しR2>>R1+ Ra >
>R1とする。またツェナーダイオードz1のツェナー
電圧を6vとすると、トランジxりTR1ハOF F状
態となシ、R4=2R5とするとトランジスタTR2が
ONとなり、TR5はOFFとなり、出力端子Cには出
力が生じない。1. Structure of a conventional example and its problems A conventional device of this kind is shown in FIG. This device has terminal A
, B, the state of the transistors TR, , TR2 is determined by the change in the input resistance R of the line between the lines, etc.
Depending on the state of 2, the transistor TR3 operates and the output generated at the terminal C changes. For example, when the input resistance R is normal (approximately 4000), the voltage at point A is approximately 4V when R=i=2R1. However, R2>>R1+ Ra>
>R1. Further, when the Zener voltage of the Zener diode z1 is 6V, the transistor x is in the OFF state, and when R4=2R5, the transistor TR2 is turned on and TR5 is turned off, so that no output is generated at the output terminal C.
次に入力抵抗Rが異常時(ショート状態)となった場合
、A点の電圧u12 vsツェナーダイオードZ、のツ
ェナー電圧を5 ”I 、 R2: R3とするとトラ
ンジスタTR1のベース電圧が約3vとなり、このトラ
ンジスタTR1はONl トランジスタTR2はOFF
である。なおR6−1−R,六R8とするとトランジス
タTR3がONとなりゲー) 、I C1を経て出力端
子Cに出力が生じる。また入力抵抗Rが0(開放状態)
の場合、抵抗R6、R7、RB、の分圧比によりトラン
ジスタTR,がON状態となPゲートIC,を経て出力
端子Cに出力が生じる。Next, when the input resistance R becomes abnormal (short-circuited), if the Zener voltage of the voltage u12 at point A vs. the Zener diode Z is 5''I, R2: R3, the base voltage of the transistor TR1 will be about 3V, This transistor TR1 is ONl, transistor TR2 is OFF
It is. Note that when R6-1-R and six R8 are set, the transistor TR3 is turned on and an output is generated at the output terminal C via IC1. Also, input resistance R is 0 (open state)
In this case, an output is generated at the output terminal C via the P-gate IC, in which the transistor TR is turned on due to the voltage division ratio of the resistors R6, R7, and RB.
しかしこの様な回路においては入力状態の感知時にツェ
ナーダイオードZ1と、抵抗R2,R5の分圧比によっ
てトランジスタTR,の動作電圧を決めているため、電
源電圧の変動の影響を受けやすく、また入力抵抗の感知
幅が広く正常時と異常時の判別がしにくい問題があった
。例えば入力抵抗RキR5とした場合、電源電圧(vl
)を1ovとするととするとトランジスタTR1のベー
ス電圧はOvとなり、このトランジスタTR1はOFF
状態であるが、電源電圧が13vとなった場合そのベー
ス電圧は約0,8vとなりトランジスタTR,はON状
態となる場合があシ、正常入力状態においても異常出力
を出力してしまう。またツェナーダイオードZ1の特性
バラツキや温度変化の影響を受けやすい問題点があった
。However, in such a circuit, when sensing the input state, the operating voltage of the transistor TR is determined by the voltage division ratio of the Zener diode Z1 and the resistors R2 and R5, so it is easily affected by fluctuations in the power supply voltage, and the input resistance The problem was that the sensing range was wide, making it difficult to distinguish between normal and abnormal conditions. For example, if the input resistance is R and R5, the power supply voltage (vl
) is 1ov, the base voltage of transistor TR1 is Ov, and this transistor TR1 is OFF.
However, when the power supply voltage becomes 13V, the base voltage becomes approximately 0.8V, and the transistor TR may be turned on, and an abnormal output is output even in a normal input state. Further, there is a problem that the Zener diode Z1 is susceptible to variations in characteristics and temperature changes.
発明の目的
本発明は上述した従来の欠点を除去し、正確に線路異常
を検出することのできる検出装置を提供することを目的
とする。OBJECTS OF THE INVENTION It is an object of the present invention to provide a detection device that can eliminate the above-mentioned conventional drawbacks and accurately detect line abnormalities.
発明の構成
不発明の線路異常検出装置は、第1.第2のトランジス
タに基準電圧を与える共通の抵抗分圧回路、線路等の状
態によって変化する電圧により前記第1のトランジスタ
を制御する手段を設け、前記第1のトランジスタにより
前記第2のトランジスタを制御して前記線路等の状態を
判別するものである。Structure of the Invention The inventive line abnormality detection device has the following features: 1. A means for controlling the first transistor by a voltage that changes depending on the state of a common resistive voltage divider circuit, a line, etc. that applies a reference voltage to the second transistor is provided, and the second transistor is controlled by the first transistor. This is used to determine the condition of the line, etc.
実楕例の説明
第2図において、1〜7はトランジスタ11゜12の動
作点設定用の抵抗、8はトランジスタ11の補償用抵抗
、9,1oはトランジスタ13の動作設定用抵抗、14
は論理を合わせるためのIC。Explanation of an actual elliptical example In FIG. 2, 1 to 7 are resistors for setting the operating points of transistors 11 and 12, 8 is a compensation resistor for transistor 11, 9 and 1o are resistors for setting the operation of transistor 13, and 14
is an IC for matching logic.
18は遅延用のコンデンサである。ム、B[入力抵抗端
子、c、ni出力端子である。18 is a delay capacitor. B [input resistance terminal, c, ni output terminal.
次にこの実施例の動作を説明する。なお抵抗1−I−1
0の各抵抗値をR1,R2・・・・・・ R,。とする
。今、入力抵抗Rが正常時(約400Ω)の場合、A点
の電圧は、R中2R,とすれば約4vとなる。この時1
、トランジスタ11のエミッタ電圧は抵抗4゜5.6の
分圧比となり、R4中R5キR6とすれば、約4vとな
る。従ってトランジスタ11[、OFF状態である。た
だし抵抗1,3は充分に高抵抗であるとする。次にR1
キR3とするとトランジスタ12のベース電圧は約8v
1トランジスタ12のエミッタ電圧はR4中Rs:R6
から約8vとなシ、トランジスタ12はOFF状態とな
シ、トランジスタ13もOFFとなる。従−って出力端
子Cには出力が生じない。次に入力抵抗Rが異常時(短
絡状態)となった場合、A点の電圧は12vとなりトラ
4ジスタ11はONとなシ、トランジスタ12.13が
ONとなり、グー)’IC1を経て出力端子Cには出力
が生じる。次に入力抵抗がW (開放状態)の場合、R
2<< (R4+Rs )とす゛るとトランジスタ11
はOFF、トランジスタ12のエミッタ電圧は約8vと
なる。また( R+ +R2)jR,ノためトランジス
タ12のベース電圧は約6vとなる。従−〕てトランジ
スタ12+13[それぞれONとなり、グー)IC1を
経て出力端子Cには出力が生じる。Next, the operation of this embodiment will be explained. Note that resistance 1-I-1
Each resistance value of 0 is R1, R2...R,. shall be. Now, when the input resistance R is normal (approximately 400Ω), the voltage at point A is approximately 4V, assuming that R is 2R. At this time 1
, the emitter voltage of the transistor 11 has a voltage division ratio of resistance 4° and 5.6, and if R4 is R5 and R6, it is about 4V. Therefore, the transistor 11[, is in the OFF state. However, it is assumed that resistors 1 and 3 have sufficiently high resistance. Next R1
If R3 is set, the base voltage of transistor 12 is approximately 8V.
The emitter voltage of one transistor 12 is Rs in R4: R6
When the voltage becomes about 8V, the transistor 12 is turned off, and the transistor 13 is also turned off. Therefore, no output is generated at output terminal C. Next, when the input resistance R becomes abnormal (short circuit state), the voltage at point A becomes 12V, the transistor 11 is turned on, the transistor 12.13 is turned on, and the output terminal is passed through IC1. An output occurs at C. Next, if the input resistance is W (open state), R
2<< (R4+Rs), transistor 11
is OFF, and the emitter voltage of transistor 12 is approximately 8V. Also, since (R+ +R2)jR, the base voltage of the transistor 12 is approximately 6V. Therefore, transistors 12+13 (each of which is turned on) produce an output at the output terminal C via IC1.
上記実施例から明らかな様に、トランジスタ11.12
の動作状態は電源電圧に対する抵抗4゜5.6による分
圧電圧を基準電圧と設定して、各入力抵抗に対するA点
の電圧およびトラ4ジスタ12のベース電圧変化によっ
て決まるため、電源電圧が変化した場合、基準電圧も同
様の比率で変化し、電源電圧変化を補正する状態とな9
従来の方式に比べ動作が安定である。またツェナーダイ
オードを使用していないため基準電圧のバラツキもなく
、温度安定度も良い。As is clear from the above embodiment, transistors 11 and 12
The operating state of is determined by the voltage at point A for each input resistance and the change in the base voltage of the transistor 12, with the voltage divided by the resistor 4°5.6 against the power supply voltage set as the reference voltage, so the power supply voltage changes. In this case, the reference voltage will also change at the same rate, and the state will be in such a state that the power supply voltage change will be corrected.
Operation is more stable than conventional methods. Additionally, since no Zener diode is used, there is no variation in reference voltage, and temperature stability is good.
発明の効果
以上の説明から明らかなように本□発明によれば、電源
電圧の変化にかかわらず安定した異常検出動作を行なわ
せることができるため、その実用上の価値は大なるもの
がある。Effects of the Invention As is clear from the above description, the present invention has great practical value because stable abnormality detection can be performed regardless of changes in power supply voltage.
第1図は従来の線路異常検出装置の結線図、第2図は本
発明の一実施例による線路異常検出装置の結線図である
。
1〜8 ’ ”’抵抗、11,12°°−°鴫トランジ
スタ。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図FIG. 1 is a wiring diagram of a conventional line abnormality detection device, and FIG. 2 is a wiring diagram of a line abnormality detection device according to an embodiment of the present invention. 1 to 8 ''''Resistors, 11, 12°°-°Shizu transistors. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure
Claims (1)
信号を発生させる線路異常検出装置において、第1.第
2のトランジスタに基準電圧を与える共通の抵抗分圧回
路、線路等の状態によって変化する電圧によシ前記第1
のトランジスタを制御する手段を設け、前記第1のトラ
ンジスタによシ前記第2のトランジスタを制御して前記
線路等の状態を判別8jることを特徴とする線路異常検
出装置。In a line abnormality detection device that detects a change in input resistance of a line or the like of various equipment monitoring devices and generates an abnormal signal, the first. A common resistive voltage divider circuit that provides a reference voltage to the second transistor, and a voltage that changes depending on the state of the line, etc.
A line abnormality detecting device comprising means for controlling a transistor, the first transistor controlling the second transistor to determine the state of the line, etc.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59030851A JPS59160772A (en) | 1984-02-21 | 1984-02-21 | Line abnormality detector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59030851A JPS59160772A (en) | 1984-02-21 | 1984-02-21 | Line abnormality detector |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59160772A true JPS59160772A (en) | 1984-09-11 |
JPS6342232B2 JPS6342232B2 (en) | 1988-08-22 |
Family
ID=12315208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59030851A Granted JPS59160772A (en) | 1984-02-21 | 1984-02-21 | Line abnormality detector |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59160772A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2096514A2 (en) * | 1993-12-31 | 1997-03-01 | Telefonica Nacional Espana Co | Interface scanning circuit. |
-
1984
- 1984-02-21 JP JP59030851A patent/JPS59160772A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2096514A2 (en) * | 1993-12-31 | 1997-03-01 | Telefonica Nacional Espana Co | Interface scanning circuit. |
Also Published As
Publication number | Publication date |
---|---|
JPS6342232B2 (en) | 1988-08-22 |
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