JPS5915982A - Graphic display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a graphic display device, and more particularly to a rask scan type graphic display device.

Conventional Structure and Problems In a rask scan type graphic display device, a graphic cursor, particularly a cross cursor, is often used to indicate a point at an arbitrary position on the display screen. There are several ways to display this cross cursor, such as one that covers the entire display area as shown in FIG. 1, and one that displays a small cross on a part of the screen as shown in FIG. However, the current situation is that the circuit configuration is too complicated to achieve the configuration shown in FIG.

OBJECT OF THE INVENTION The object of the present invention is to facilitate the display of a cross cursor as shown in FIG.

Structure of the Invention In order to achieve the above object, the graphic display device of the present invention includes an m-bit horizontal cursor address register and an n-bit vertical cursor address register each holding the horizontal and vertical addresses of a cross-shaped cursor to be displayed. Address register [However, m and n are 2, where X and y are the number of horizontal and vertical display dots of the cross cursor, respectively.
″′-1<X≦2″′, 2<y≦2″〕
and the initializable m-bit horizontal address counter and n-bit vertical address counter connected to the outputs of the horizontal and vertical cursor address registers, respectively, and the carry output or One of the borrow outputs is an AND gate that takes the AND gate of the output of the horizontal address counter (where 2≦5m-2), and the carry or borrow output of the horizontal address counter (uu) is used. l(m-1 bit shift register for delaying by l dot clock period [however, l!=23,
A comparator is provided that outputs a signal when the most significant bit of the vertical address counter and the other high-order l bits (where l≦i≦n-2) are invalid, and horizontal Dot, y=2 Fin (-1
)-, the configuration displays a cross-shaped cursor with a length of .

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 8 to 47.

In Figure 8, (1) is an m-bit horizontal cursor address register for holding the horizontal address of the cross cursor, and (2) is an n-bit vertical cursor address register for holding the cross cursor placement direction address. The direction cursor address register (3) is a horizontal address counter for counting the initialized horizontal cursor address, and consists of an In-bit down counter with a borrow output. (4) is an acceptance direction address counter for counting the initialized base ml direction cursor address, and is composed of an n-bit down counter with a borrow or carry output. (The 5th block is an l-bit shift register, (
6 is an AND gate, and (7) is an i-bit comparator. Now, -17! 1024 dots in the horizontal direction, 2 lines in the vertical direction on the graphic display,
A case will be described in which a crosshair cursor with 16 dots in the horizontal direction and 82 lines in the vertical direction is displayed.

At this time, each of the above embroidery parameters, m, n, l
.

i is 10, 9, and 8.4, respectively.

Address latch strobe count 1. - Horizontal cursor address l latched in horizontal force direction cursor address register (1) by 3.12. 2 lo) Display timing signal ■ 4 horizontal address counter (3)
is initialized to . The horizontal address counter (3) starts at dot clock 15, is decremented by one every dot clock, and outputs all 0.
When this happens, borrow l is output.

In other words, the display position when the borrow iIl is issued becomes the horizontal cursor address. Similarly, the vertical cursor address 11 latched in the vertical cursor address register (2) by the address latch strobe 1 word I3 is initialized in the vertical address counter (4) by the display timing store number 16. The vertical address counter (4) is activated when the horizontal synchronization signal 1.
Therefore, the cursor address of the deku becomes one for each horizontal period.

The AND gate (6) has a horizontal address counter (3
) are connected to the borrow 19 output of the vertical address counter (4). Therefore, the AND gate (6) is used when the upper 6 bits of the horizontal address counter (3) are all l and the vertical address counter (4J
When Borrow I is output, the vertical address of the display position matches the vertical cursor address, and the horizontal address of the display position is from the address next to the horizontal cursor address to the l6 address. When within the range, the output becomes -l-.

This is illustrated in Figure 4. This becomes the groove line for the crosshair cursor. (Z) represents a set address.

Comparator (7) indicates that when A, = BII (n = 0 to 8) are all 1, and the C input is 1, the horizontal address of the display position is the horizontal cursor address plus 8. When it matches the address and the upward direction address of the display position is within the range of -15, +16 from the vertical direction cursor address, the output becomes 1. This is illustrated in FIG. 6.

This becomes the vertical line of the crosshair cursor.

By logically adding these two signals at the OR gate (8), the output of the OR gate (8) is X. A crosshair cursor signal is output. The dot structure relationship of this cursor is
As shown in the figure.

As shown in FIG. 6, the address actually pointed to by the cross cursor is 9 addresses ahead of the address set in the cursor address register in the horizontal direction. This address correction 1 can be performed by software, but if the Ha display timing signals '4*'6 are set as shown in FIG. 7, the cross cursor will be displayed at the correct address. In FIG. 7, )is is the horizontal synchronization signal, HI
IL is the horizontal blanking signal, VS is the vertical synchronization signal, VBL
is the vertical ml blanking signal.

Note that in the above embodiment, the counter (3) (down counter) is used, but if the cursor address data set in the horizontal and vertical cursor address registers is a two's complement number, the down counter can be used even if an up counter is used. A cross cursor can be displayed in the same way as the counter.

Effects of the Invention As described above, according to the present invention, a cross cursor can be easily displayed at any position on the display screen by latching cursor address data in each of the horizontal and vertical cursor address registers. can. Furthermore, the size of the cross cursor can be easily changed.

[Brief explanation of drawings]

Figures 1 and 2 are explanatory diagrams of display examples of the cross cursor, and Figure 8
The figure is a four-chip circuit diagram showing one embodiment of the present invention, and FIGS. 4 and 5.
The figures are respectively explanatory views of the horizontal edges and vertical line parts of the crosshair cursor that can be applied in one embodiment of the present invention, FIG. 6 is an enlarged view combining FIGS. 4 and 5, and FIG. It is a time chart of various signals in the figure. (Ko...Horizontal cursor address register, (2)...
・・4 +ffi direction cursor address register, (
3)...Horizontal address counter, (4)...Vertical address counter, (5)...Shift register,
(6) ...And gate, (7n... Comparator agent Hiroshi Morimoto Figure 1 Figure 2 Figure 4 Figure 5 Figure 6 Figure 7 Figure I

Claims (1)

[Claims] 1. An m-bit horizontal cursor address register and an n-bit vertical cursor address register that respectively hold the horizontal and vertical addresses of the cross-shaped cursor to be displayed [provided that nl, +1 are the number of horizontal and vertical display bits of the cross cursor (values that satisfy 2< An initializable m-bit horizontal address counter and an n-bit vertical address counter connected to the outputs of the registers, one of the carry output or borrow output of the vertical address counter, and the output of the horizontal address counter written in IJd. an AND gate that performs logical AND with the upper bit (2≦≦m−2), and an l-bit shift register for delaying the carry or borrow output of the horizontal address counter written in uiJ by l dot clock periods. [
However, I! -2 ('- to -s), and the most significant bit of the vertical address counter and the upper 1 other than tt.
A comparator that outputs a signal when the bits [1=i≦n-2] are equal is provided, and horizontal (n-Lee, x-2('-k) dots, y=2 cross of fin length) A graphics display device that displays a type cursor.