JPS59158874A - Electronic lock control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a push-button power-off control, for example, a push-button electronic lock control circuit for automobiles.

A type of electronic lock control circuit that records two types of numbers, a fixed number and an arbitrary number, generates a control signal for a crab-picking device when the pusho-shuhotan operation input signal and the given number match, for example, a car. When the push button operation signal matches the fixed number, the machine can be rewritten to memorize a different number. However, in this type of conventional lock, if the arbitrary numbers used to unlock the lock are all the same number or a combination of numbers that are easy to use based on human psychology, it can be easily unlocked illegally. The drawback is that the anti-theft effect of the tt child lock cannot be fully demonstrated.＼
be.

Therefore, the present invention provides (1) a display circuit which, when a manually entered arbitrary number or a non-registration number corresponds to the number, erases the notation and displays to the user whether or not the number corresponds to a non-registration number; By providing this, the above-mentioned drawbacks are solved.

To explain the drawings, the electronic lock control circuit A of the present invention includes a number setting forceps 11 that manually generates an electric signal of an arbitrary number, and a hash bar that temporarily records the full output of the general control device. 1, 9 circuit 12, fixed number register 1g circuit that stores fixed finger numbers] (3, number setter, A comparator circuit 15 which compares the outputs of the circuit 12 and the fixed finger 3 and the output from the circuit 13 or the arbitrary number storage circuit 14 and outputs a matching signal when they match.
When the outputs of the fixed number storage circuit 13 and the fixed number storage circuit 13 are compared with the previous C1, a match signal generated from the comparison circuit 15 gives a write signal to the arbitrary number storage circuit 14, and also writes a write signal between the buffer storage circuit 12 and the arbitrary number storage circuit 14. Compare the output later 5. When it is generated from the comparison circuit 15 = due to the matching number! The command circuit 1 [5] which generates the control signal for position A is input.

The number setting device 11 converts the output of five push button switches a to e, a chattering prevention circuit 20 connected to these push button switches a to e, and a chattering prevention circuit i circuit 20 into a binary signal. It has a BCD converter 21 for converting, and a one-shot multi-high flake 22 for shaping the output waveform of the BCD converter. In this specification, the one-shot Maruna vibrator is OSM, the random access memory is RAM, and the read-only memory is ROM7.
Output of SM22 (respectively rectifier 2 such as diode)
3. The output 24 is sent out to the Huff-Fa storage circuit 12 and the arbitrary number storage circuit 14. Buffer memory circuit 12
The arbitrary number storage circuit 14 has a RAM and can store the arbitrary number output from the number setter 11.

The output of the thousand-total link prevention circuit 20 is 0)
5 and is sent to the counter 30. Power ``Nonta 3
0 passes through the Atonenos selector 31, Hanofubuki i,
i to the circuit 12, the fixed number storage circuit 13, and the arbitrary number storage circuit 141. The fixed number storage circuit 13 has a ROM. When counter 30 counts the fifth signal from the number setter, value detector 32, which detects "5", produces an output from terminal O5. Similarly, when the seventh signal from counter 30 or number setter is counted, value detector 32 produces an output at terminal O7. This value directivity detector 32 is composed of a known circuit such as a decoder.

The output of the terminal O5 of the value detector 32 is output from the AND gate 26 and (
Pass through the monthly game h33, automatic address signal generator 34
is sent. . Details of automatic address signal generator 34 are shown in FIG. That is, the output of the OR gate 33 inputs the knob flop 35 and outputs the output at its Q terminal. Progressively increase 38 to L
OR through counter No. 38, Il, and BCD converter 39
Gate 40aj output is provided. When the counter 38 counts "5", the flip-flop 35 and 1j6 are reset by the force.

The output of terminal O7 of value detector 32 is sent to automatic address signal generator *4L, which has a circuit substantially similar to automatic address signal generator 34. The output of the flip-flop 42Ill of the auto-r address a signal generator 41 and the terminal O7 is 1-, and the Q output is ANDed)'-to, and the output of the oscillator 44 is ANDed 43 and is counted by a counter 45. The counter 45 generates the signals "6" and "7" and passes them through the BCD converter 46 to OR them.
Supplied to gate 40.

Automatic address signal generator 34 and 41Q) output is . OR
Gate 50.5] and 52 are followed by 2 and sent to the selector 31. Atres Serei Return '31 is the 4th
As shown in the figure, the counter: 30 ('') output and the line 530 through the inverter 54
D Take-55, 5G and 57, OI hole 1-50,
A) AND gate 5 receives the outputs of lines 51, 52 and 53.
8, 59, 60 and these σ)! '1. ND Kate 55
~60 outputs are received and the org key 1.01.62. C
+3 and A]. The outputs of OR cables 1-61 to 63 are
It is sent as an address signal to the storage circuits 12-14.

The output of the first child 05 and 01 of the value detector 32 is -1019
The Q output of flip-flop 7'2.73 is sent to Seno(・01Mo1) through K-1-70 and O8-171, and the Q output of Frynosov I-]tub 72 is
? It is applied to the read V/write hr'a+1 child of the address register 1/actuator 31, the open/manual terminal of the address selector 1/actor 31, and the upper enable/enable terminal of a comparator 80, which will be described later. Q output of flip-flop 72 or H level and 17
level, the buffer storage circuit 12, read mode, write mode, and air I-less selector 31, respectively.
Baso 7jt it auto mode and Manny L full mo l,
Comparators 80 are shifted into enabled mode and disabled mode, respectively. Therefore, Furi Nopfuji 2
When the knob 72 is reset, a(・Response selector 3
1) When the counter 30's a)-response (i'1 is given to each memory circuit 12 to 14, and this or is applied to each memory circuit 12-14.

When the flip-flop 73 is turned on, a chip select signal is applied from the Q terminal to the chip select terminal (hereinafter referred to as the C8 terminal) of the fixed number storage circuit 13. Renp,
Numbering '1. The circuit 14 is connected to the O of the flip-flop 74.
A chip select signal is given to the O8 terminal from the 61st child. Also, arbitrary numbered unique circuit 14 glue -F'/rai 1-
Ishii receives a command signal from AND gate 76 and ○R game 1-78, and when ANI) game 1-76 generates the output of ■Rehel, it becomes Rai[・7-1~, and ■, Rehel's output. When generating an output, it is converted into Rietmo l-. The comparator 80 of the conversion circuit 15 receives an enable signal from the Q terminal of the free-7 block 72 and a clock signal (3) from the ○I gate 40.
The outputs of 4 are compared 7, and an output is given to the counter 81 every time the output of each digit matches or differs from each other. However, as will be described later, the outputs from the fixed number memory circuit 13 and the random number memory circuit 14 are not compared with the output from the buffer memory circuit 12 at the same time. The counter 81 also has a one-shot function.
When the output of the comparator 80 reaches a predetermined value of 1.5i or i7J, the command circuit 16(') ANiD case 1.
Give a matching signal to 82-87 for a certain period of time.

AND gate 2 (2) receives the matching number of the counter 81, the inverted number of the flip-flop 74, and the 0-1 output of the value detector 3 (2), and the input signal of the number setter 11 is fixedly stored. It detects that it matches the last five digits of the number, and sends the output to the OR gate 88 (to set it all the time, or AND data 1-89's inverted inputs I, E:.

Gives 3E output to prevent counter 30 from being reset.

The AND gate 83 receives the inverted signal of the counter 81 and the C7 signal of the value detector 32, detects that the input signal matches the remaining two digits of the fixed number, and outputs the 01 clock 88. Give the output. AN1-) The gate I 84 receives the inverted signal of the counter 81, the Q output of the flop 74, and the 01 output of the value detector 32, and determines whether the input borrowed or matches the arbitrary storage number 4y. Detect this and give the reseno I signal to the OR key 1 88. l\N
I) Game 1-85 receives the counter 8■, Furi 2, Pflo knob 74 and the value (0., output of the broiler 32, and inputs an input signal that matches the arbitrary IQ, !'E-). is sensed and the output is or<game 1-88 and the controlled device 90.
Give it to 90'. The 8ND gate 86 receives the force/'nonta 81 and the oq output of the value detector 32, and converts it into an input lid.
Detects that all match the fixed record/bet number Lf, - and outputs the OR key 1/88 and the sled/knob flop g1's mono 1-U (J, i child. "7
'', the output of the gate 86 is outputted from the OR gate 86 by 4 and applied to the output of the flip-flop 74 (AND gate 1). -75 is applied to the inverting input terminal of the flip-flop 74, thereby preventing the flip-flop 74 from resetting.

ANDK-1・87 is counter 81 and Flinopf 1
: Receives both the inverted sign of the 2 knob 74 and the 05 output of the O value detector 32, detects that the input signal does not match the first 5 digits of the fixed memory number, and outputs the signal automatically through the ○I mage 1-33. Return to JA1-res number generator 34 and return to J (Flinopf l: At the same time as resetting I knob 73, set Flinopf o7 knob 74 to 7 notes, Mu, Ni) Game I.7
6 and OR gate)), the color number storage circuit 14 is set to RI-)-MO1-. Human signal or full circle fixed number 1! 〉It coincides with the number of outputs/\ND gate 86 output, shift 1 Kotpu 91 is set, and its Qh, 'i
4) Inverting inputs of gates 93 and 26;
Since it is applied to y6+6 completion (a), the next 5-digit human input signal is written in the arbitrary number notation circuit 1.), and at the same time, the value detector 32 (〇-11) 1 is applied to 1 input, and AN output is applied. Day l-26
or turn on AI'JD gate 93 (
, 2 Hen) (Mishi, AND Lee-h93's departure, OR
]J! :
, the flip-flop 91 is reset and 1.

In the illustrated circuit, the output a of SM22 of number setter 1 is
t: Through OR Li-1-100, Sui ~ Ligawan/
:lsol-mal-)1 is applied to the high flake 101. Gonori l ~ Rigawansho 7 To Multi High Break 10
1. It has the function of generating an output when it does not receive a signal from the number setter 1 for a certain period of time and resetting all circuits through the OR game 88.

The electric control circuit according to the present invention includes an exclusion number processing circuit B for the registration. This time) Raku B is all 3. I Exclusion Number - 1 ■ It has a circuit 100 and a comparator 101.

Registration exclusion number 1 unique circuit 100 is 0■guge I・78
It is connected to the output of 1120M. The comparator 101 compares the output of the buffer storage circuit 12 and the output of the circuit 100 with a number (excluding the output and registration).
Enable with the output of ○R Casey 78;
Koshifu 1-Sa,'! Receive the outputs of buttons a to e as clock signals through gate 120.
) The output of the ScLL comparison 5101 is counted by the counter 102. This output is output when the counter 102 counts the 5 digits of the registration exclusion number, and this output is 08M10, WHI
-”-S-furi is sent to Pflomep 116.

The OSM 103 thereby targets the diode 105 and rubs the transistor 106 for a certain period of time, or activates an alarm 107 such as an LED or a buzzer for that period of time. When the number corresponds to the outside number, the L converter 107 operates and the RS flip-flop 116 is set to 7), so its Q output is output from the OR gate 3.
8 to reset all circuits, and is applied to the inverting input terminal of AND gate 111 and also to OR gate 33. Therefore, the automatic address signal generator 34 operates, and the address signal generator 34 passes through the address register 31 to the arbitrary number storage circuit 1.
4 is given an address signal. At this time, the arbitrary number storage circuit 14 is connected to the RS flip-flop 1"6 or 601 through the gate 78.
Since there is no code, all the memory contents will be lost.The structure of the RAM ``2[-1'' is written and 33 automatically generates an address signal and outputs 2x34 or 15''.When RS flip-flop 35 is activated, it is output. At the same time, the RS flip-flop 116i is also reset. As mentioned above, the alarm 107 and the transistor 10 (i:5) are on the display circuit that displays whether the arbitrary number input corresponds to the registration exclusion number Q or blue.

If the input text and number do not correspond to the registered number 1, number 1, J-, the alarm 107 operates intermittently. 111
After storing arbitrary numbers such as j, the RS flip-flop 74 is used as U-1-, so the output of OR-1-78 is
It becomes Karo L Le Le. This output is delayed by the delay circuit 104, and then outputs A at the rising edge by SMIIO (:).
A pulse is applied to the ND game 1-1il. At this time, there is no 1 in the output from RS Flinopfl: I knob 11G, and
Since the output is output from 05 of the detector 32, AND sheet t-111 produces an output, and 08M1L2 produces an output after a certain period of time.
The three outputs are given to AND gate 113. Therefore, the AND gate +-113 converts the signal of the pulse generator 114 into a diode).
='l15 to the transistor 106, so the alarm 107 performs intermittent operation. With the intermittent operation, the user is forced to press f7 as soon as the arbitrary number is registered.

To explain the operation of the electric J7 lock control circuit according to the present invention, as an example, if the fixed memory number is 7 digits, and the number (key number 1a) is 5 digits, push the 1st button of the number setter 11. When the switch a-"-e is pressed in 5 digits, the manual signal passes through the chatter link prevention circuit t?Fy20.BCD converter 21. The counter 30 is made to count by "i".

At this time, flip-flops 72, 73.14 beams 10 I
・State! Therefore, the address selector 31 is shifted to manual, the buffer storage circuit 12 is shifted to write, the comparator 8o is disabled, and the fixed number storage circuit 13 and arbitrary number storage circuit 14 have their CS terminals L
Since it is a lehru, it is in a state of decline. The output of the counter 30 is
The address signal is sent to the buffer storage circuit 12 through the A1-1 female selector 31, and the input signal is stored only in this storage circuit 12.

When the counter 30 counts the fifth digit, the output generated from the 05 terminal of the value detector 32 is applied to the AND gate 26. At this time, since the flip-flop 91 is in the 1- state, the inverting input terminal of the AND gate 26 is connected to the
7 Rehel inputs are given, 8 Ni) Keto 26
produces an output. The output of AND gate 1-26 is sent to flip-flop 7 through OR gate 1-70 and OSM71.
Since it is sent to 2.73, these flip-flops are seven times. Therefore, Hasophah 1. The mark circuit 12 enters the read mode, the address selector 31 is converted to OI-, and the comparator 80 is shifted to enable. Also, the output of AntK 1-26 is the output of ORK 1-3.
3 through the automatic address signal generator 34.
"5-1 address signal is generated, OR gate 50-5
2 and address selector 31 to buffer storage circuit 12, the output of automatic address signal generator 34 is applied to comparator 80 as a clock signal through OR gate 40. Since the fixed number storage circuit 13 is in an enabled state since the CS terminal is 1 (RAE), the number signal stored in the fixed storage circuit 17ON413 is sent to the comparator 8 in synchronization with the output of the automatic I/RES signal generator 34.
Send to 0. Therefore, the comparator 80 compares the numbers stored in the buffer storage circuit 12 and the fixed number storage circuit 13, and when each digit matches, a match signal is sent to the counter 81.
Send to.

When five matching signals are generated from the comparator 80 as shown in FIG.

At this point, an output is generated from the AND gate 26 and no output is generated from the flip-flop 74, so an output is generated from the AND gate 1.82. This output is used to reset all circuits through OR gate 88, or to prevent reset/reset of counters 30 and 81 through AND gate 89. Furthermore, when two digits are input from the number setter 11, the counter 30 becomes "7".
2-digit input or buffer storage circuit 1
2 is stored. Counter 30 or 17",
The output generated from the 07 end of the value detector 32 is sent to the flip-flops 72 and 73, and at the same time is sent to the automatic address signal generator 41.

Therefore, since the buffer memory circuit 12 dregs = tomote and the fixed number memory circuit 13 is enabled, "6
"7" signal from the automatic address signal generator 41 through the address selector 31 -C1 These storage circuits 12, 1
3 and their contents are compared by a comparator 80.

At the time of comparison, a clock signal is applied from the OR gate 40 to the CL terminal of the comparator 80.

Two more coincidence signals from the comparator 80 are sent to the counter 81.
, an output is generated from the 07 terminal to the OR gate 105. At this time, since an output is generated from the O7 terminal of the value detector 32, the AND game l-86 generates an output, causes the flip-flop 74.91 to turn 7), and resets the entire circuit through the OR game l-88. do. When the flip-flop 74 is set to '+', the arbitrary number storage circuit 14 is set to write mode and the AND cable 1-8 is set to write mode.
2.

Outputs are given to 84, 85, . . . 87, and an arbitrary number can be stored. In this memorizable state, the fixed number storage circuit 13 is disabled, and the arbitrary number generated by pressing the 11 number setter 11 five times is stored in the arbitrary number storage circuit 14.

The alarm signal is sent to an a circuit 14, which includes a counter 30 and an address selector 31.

When the fifth digit arbitrary number is memorized, O5 of the value detector 32
A blade is generated from the terminal, and its output is changed to AND 1-93. At that time, since the flip-flop 91 is in the set state, the AND gate 1-93 produces an output, resets the entire circuit through the OR gate 88, and then resets the flip-flop 91 through the delay circuit 94. When the work is completed,
(The O5 output of the 1M detection W32 is not sent to the OR gate 33 through the AND gate 26.

Next, to explain the case of generating control signals for the controlled devices 90, 90'ζ,
~e17) After the 5-digit output is written in the buffer storage circuit 12, it is compared with the fixed number of the fixed number writing jQ circuit 13. The unlocking signal is generated depending on the input signal. Since this is only when the contents of the a circuit 14 match, the above-mentioned fixed numbers do not apply. Following the above comparison, 1. An output is generated from the 05 terminal of the value detector 32, but no output is generated from the counter 81. Therefore, AND gate 87 core 3 produces an output, AND goo 1-
33 as well as energizing the automatic address signal generator 34. Since the flip-flop 73 is reset through the R game 1-77 and the flip-flop 74 is set to 1-, the arbitrary number storage circuit 14 is placed in read mode. Therefore, in synchronization with the output of the automatic address signal generator 34, the buffer storage amount it'8i2 and the contents of the arbitrary number storage circuit 14 are compared by the comparator 80. When the 5-digit signals match, the o5 output of the counter 81 is connected to the ○R game 1-105, and the command circuit 1G-2 returns the matching number. Therefore A,
The ND gate 85 is opened, and the entire circuit is reset 71- through the gate 1-88, and the controlled devices 90 and 90' are unlocked.

The input signal for Pollan operation is as shown in 1. If it does not match the entered arbitrary number, the counter 81 will not produce an output.
ND game I.84 generates an output and resets all circuits.

If the button input signal matches the first five digits of the stored fixed number but does not match the remaining two digits, the output from the O7 terminal of the counter 81 will not be controlled, so the output from the AND gate 83 will be occurs and resets all circuits.

2. When the arbitrary number entered falls under the registration exclusion number.2. The comparison in the comparator 101 is performed simultaneously with the storage of the arbitrary number. Therefore, when an arbitrary number is input to the number setter 11-(, the input signal and the contents of the exclusion number register II circuit 100 are compared for each digit of the comparator 101-C. At this time, the output of the counter 102IJ is increased by 4", thereby causing the alarm 107 to emit 31ft for a certain period of time, and the output of the flip-flop 116 resets all circuits. At the same time, the arbitrary number storage circuit 14 is set to light mode. 2, and activates the automatic address signal generator 34.
The stored contents of the arbitrary number storage circuit 14 are erased. The automatic atlas signal 3 outputs ``5'' from the RS flop flop 116 and sets the arbitrary number storage circuit 14 to remote mode.

The entered arbitrary number or registration exclusion number does not correspond to September 1-
At this time, the alarm 10 is activated because there is no output from the comparator 101.
7 is a word that operates continuously. Namely, numbering, twisting.
When the writing to 1814 is completed, OSMilO outputs A with the delayed falling signal of RS flip-flop 7.
Give to ND Kate 111. O of value detector 32 with one foot
5 outputs and AND cable 1.111 controls the output 7, OSM
112 while the output of pulse generator 114 is at I
-Rangister 106? ．． Since two are given, alarm 10
7 performs intermittent operation.

As mentioned above, this invention erases the memory of the input arbitrary number or the registration 31 exclusion number. Since it displays whether or not theft is to be carried out, the fact can be understood directly and has the advantage of significantly improving the anti-theft effect.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of the electronic lock control circuit of the present invention, Figs. 2 and 3 are circuit diagrams of the automatic a) response signal generator,
FIG. 4 is a circuit diagram of the address selector. DESCRIPTION OF SYMBOLS 10...Electronic lock, 11...Number setting device, 12-Buffer storage circuit, 13...Fixed number notation 1a circuit, 14...Arbitrary number storage circuit, 15...Comparison circuit, 16...Command circuit, 13...Registration exclusion number processing circuit, 107...Alarm 1jii [1-Former Chojin Nissan Motor Co., Ltd. Domestic Metal Industry Co., Ltd. Agent Tea Male; dsjf ・:::・, 1 Figure 2 '54 〆R. Figure 3/41 Figure 4 Y→Ki1

Claims (1)

[Claims] Manual operation: A number setter that generates an electrical signal, a low memory circuit that temporarily records the ↑ output signal of the number setter, a fixed number memory circuit that stores a fixed number, and a number setter. an arbitrary number storage circuit that stores an arbitrary number, a comparison circuit that compares the output of the fixed number storage circuit or the arbitrary number recording circuit with the Hasophic 1 circuit and generates a match signal when they match, and a buffer storage circuit. When the outputs of the 1 and 1 circuits are compared to the fixed phase, a match signal generated from the comparator circuit gives a write signal to the arbitrary number 1 circuit, and the buffer storage circuit and the 3-3 A command circuit generates a control signal for controlling the device based on a coincidence signal generated from the comparison circuit when the output from the storage circuit is compared, and a registration exclusion number storage circuit is input (I window number 3).
・An electronic lock control circuit that has a display screen that displays whether or not it corresponds to an exclusion number.