JPS59157760A - List processing system of parallel inference type - Google Patents

Abstract

PURPOSE:To process a large quantity of list data in a high speed by searching experience rules individually when an inference request is accepted in plural processors. CONSTITUTION:An inference request message 52 and an inference data message 53 are transmitted to plural inferring processors 21 through an interpreter processor 11. When receiving the inference data message 53, each inferring processor 21 stores know facts in a fact group list. The inferring processor 21 takes out experience rules in order from the beginning of an experience rule group list. The processor 21 checks whether the fact group list coincides with experience rules or not; and if they coincide with each other, the processor 21 takes out a conclusion part of experience rules and transmits back an inference response message to the interpreter processor 11. Inferring processors 21 have a shared memory and can execute parallel processings in a high speed.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides specialized knowledge (
This invention relates to a parallel (fm logical list processing method) suitable for processing a large amount of list data in relation to each other in a knowledge-based system that makes inferences based on empirical rules and facts.

[Background of the invention]

The conventional knowledge-based system parallel inference method uses memory that can be commonly accessed by each processor (shared memory), and is a convenient method for this purpose, but the software and hardware that cannot handle conflicting accesses to the shared memory The overhead is high, and in a complex system of 10 or more computers, no performance improvement could be expected due to access bottlenecks. As conventional parallel inference methods, for example, R, D,
FENNELL.

V, R1, LESSER: Parallel i
sm in Artificia II Intellig
ence Problom Solving: A
Ca5e -5tudy of Healthy I
LIF5. Trans, ComputlFeb,
1977 is known.

[Purpose of the invention]

An object of the present invention is to provide a list processing method that can achieve ultra-high speed by processing inferences in a knowledge base system written in LISP in parallel using several dozen microcomputers.

[Summary of the invention]

In order to achieve these objectives, the present invention expands the memory of each processor, eliminates shared memory, stores fact data in the memory of each expanded processor, and sends only new facts to all inference processors at once. It is distinctive in that it is made to do.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIGS. 1 and 2 show the system configuration of an embodiment of an apparatus that implements the method of the present invention. Figure 1 is a schematic diagram of the overall configuration.
FIG. 2 is a detailed configuration diagram of the system. Reference numerals 1 and 2 are microcomputers called an interpreter computer and an inference computer, respectively. A computer 1 is connected to an input/output device 3, such as a console, a disk, or a process human output device called an inference data human output device.

The bus may be connected in other shapes such as a rectangular shape.

In addition, HMC86 is the microcomputer 1.2.
8000 etc. can be used.

As shown in FIG. 2, the interpreter computer 1 includes an interpreter processor 11 and its local memory 1.
The inference computer 2 is composed of an inference processor 21 and its local memory 22.

FIG. 3 shows each processor 1 in the system of the embodiment.
1 or 21, and interpreter processor 1
1 and the inferred data output device 3.

The interpreter processor 11 manually inputs inference data 51 through the inference data input/output device 3, and outputs an inference result message 55.

In order to perform parallel inference processing, an interpreter processor 11
transmits an inference request message 52 and, if necessary, an inference data message 53 to all inference processors 21 in a broadcast manner.

The inference processor 21 returns the inference result as an inference response message 54.

FIG. 4 is an example of the format of the inference request message 52.

The request message lag 521 is the inference request message 5
This is a flag indicating that the number is 2. The request message serial number 522 is a serial number assigned to the inference request message 52.

The inference data type 523 indicates the content of the inference data 525. For example, the inference data 525 indicates whether a known fact (a pointer to) 62 is a empirical rule (a pointer to) 64.

The inference data length 524 indicates the length of the inference data, the length, and the number of data of the known facts 62 and empirical rules 64 transmitted in this message.

FIG. 5 shows an example of the format of the inference data message 53.

The data message flag 531 is a flag indicating that the message is an inferred data message 53.

When the amount of inference data 525 required for inference is large, the inference data message 53 sends the inference data that has reached a certain amount,
Each time it is sent, it supplements the function of the inference request message 52 in the inference request. The correspondence request message serial number 532 has such a relationship (the inference data message 53 sends a certain amount of inference data 536 in advance, and attempts to supplement its function). 52 serial number 5
It is 22.

The data message serial number 533 is a serial number assigned to the inferred data message 53.

This is reset to 0 each time the response request message pass 532 is updated.

The inference data type 534, inference data length 535, and inference data 536 are exactly the same as those for the inference request message 52 already explained in FIG.

FIG. 6 is an example of the format of the inference response message 54.

The response message flag 541 indicates the inference response message 5.
This is a flag indicating that the number is 4. The response request message serial number 542 indicates which inference request the inference response message 54 corresponds to by the serial number 522 of the inference request message 52 corresponding to the inference request.

The response processor number 543 indicates the ID (number) of the inference processor 21 that is the sender of this response message. The response message serial number 544 is a serial number assigned to the inference response message 54, and is a serial number assigned to the inference response message 54.
and is attached independently to each inference processor 21.

The response data type 545 indicates the contents of the response data 547 (new facts, termination information, etc.). The response data length 546 is
The length of the response data 547 indicates, for example, the number of new facts.

FIG. 7 is an example of a map of the local memory 12 of the interpreter processor 11.

The list area 75 is an area containing a list of facts, empirical rules, etc., that is, a pointer to the storage location of data such as known facts and empirical rules, and a group of pointers indicating the structure thereof (list structure). The full word area 78 is an area for storing the data body (for example, known fact data, heuristic data) pointed to by the list.

The new fact queue 76 is a queue for storing new facts transmitted by inference response messages from each inference processor 21 in the order of arrival.

The speculation result record position table 77u is a table for determining the relative position (rank) of the first new fact in the new fact queue 76 for the speculation request message 52.

FIG. 8 is an example of a map of the local memory 22 of the inference processor 21.

Fact group list (area) 611 Empirical rule group list (area) 6
3 is an area for storing lists of facts, empirical rules, etc. (a pointer to the storage location of data such as known facts and empirical rules, and a pointer group indicating the structure (list structure)). be.

FIG. 9 shows an example of the structure of the fact group list 61 and the empirical rule group list 63.

The fact group list 61 is a list of known facts (pointers to data)
62 one-way chains.

The empirical rule group list 63 is an empirical rule (pointer to data)
This is a one-way chain of 64. Furthermore, each empirical rule 64 consists of a condition part 65 and a conclusion part 66, and the condition part 65 has a condition (
A pointer to condition data) 651 is formed from a one-way chain, and the conclusion part 66 is a conclusion (pointer to concatenation data) 661
Consists of a unidirectional chain of.

FIG. 10 is a configuration diagram of an example of the new fact queue 76.

New facts (pointers to) 761 are queued in the new fact queue 76 (main body) in the order in which new facts are received through the inference response message 54.

FIG. 11 shows an example of the configuration of the inference result recording position table 77.

The inference result recording position table 77 shows the inference request message number 7.
70 and the relative position 771 of a new fact generated as a result of inference based on this message.

FIG. 12 and FIG. 13 show an example of the processing flow of the interpreter processor and the inference processor, respectively.

Below, five explanations of the operation of the embodiment of the present invention will be given.

■Explain forward inference for simple reasons.

Forward inference processing is performed as follows.

(1) Search a group of empirical rules in order to find an empirical rule that makes known facts satisfy the conditional part.

(2) Extract the conclusion part of the applicable rule of thumb and examine the group of facts to see if it is a known fact, or in other words, whether a new fact has been discovered.

(3) Store the new fact in the new fact group, add it to the fact group as a known fact, and return to (1).

(4) If no new facts are found or if the conclusion part requests a stop, the process ends.

The operation of the embodiment of the present invention in forward inference (hereinafter referred to as inference) is as follows (see FIGS. 12 and 13).

(1) When the inference data 51 is manually input from the inference data output device 3 (step 201), the interpreter processor 11 generates an inference request message 52 from this data.
202) and sends -M to all inference processors 21 (step 203). In order to perform inference all at once and increase inference efficiency, it is also permissible to send inference request message 52 after transmitting intervertebral data message 53 several times.

(2) When the inference processor 21 receives the inference data message 53 (step 301), it stores the known facts (pointers thereof) 62 in the fact group list 61 (step 302). When the inference request message is received, the known facts (pointers thereof) 62 are stored in the fact group list 61, and inference is started (step 303).

(3) The inference by the inference processor 21 is as follows.

(1) Starting from the beginning of the empirical rule group list 63, the empirical rules 64
is extracted (step 304).

When the final rule of thumb 64 is reached (process step 1).

(II) The condition part 65 of the extracted empirical rule 64 is extracted in order from the first condition 651 and checked to see if it is true (step 305).

That is, the Akatsuki fact (
Extract the pointer) 62 and set the condition (pointer) 65
Check if it matches 1. fact list 6
If the condition 651 is to match any known fact 62 in 1, the process returns to step 304 (1) and the next empirical rule 64 is extracted. Known facts 62 that match the first condition 651
If so (if the first condition 651 is true), all the conditions 651 in the condition part 65 are checked one after another.

If there is a condition 651 that is not true, the process returns to step (1) (step 304) and the next empirical rule 64 is extracted. Condition part 65
If all of the conditions are true, then process (iii) is performed.

(ri) All the conclusions 661 are extracted from the conclusion part 66 of the rule of thumb 64, which has been checked to see that all the conditions 651 in the condition part 65 are true, and a new fact 547 is found (step 306).

That is, the conclusions (pointers) 661 are taken out in the order of the beginning of the conclusion section 66, and checked against all known facts 62 in the fact group list 61 to see if they match the known facts (pointers) 62. Fact 62
If it does not match, it will be treated as new fact 547.

If no new facts are found, process (1) (step 3)
Return to step 04) and take out the next empirical rule 64. If found, the process (1v) (step 308) is performed.

(1v) The discovered new fact (pointer) 547, its number 546, and the empirical rule (pointer) 64-+ from which the new fact 547 was derived are set in the m-logic response message 54 and transmitted (step 308). If no new facts are found, the inference response message 54 is returned with the number 546 of new facts set to 0 (step 307).

(4) The interpreter processor 11 receives the inference response message 54 from each inference processor 21 (step 204), and if there is a new fact, puts it in the new fact queue 76. However, the relative position in the new fact queue 76 of the first new fact 761 for each inference request message 52 is recorded as the new fact relative position 771 in the inference result recording position table 77 (step 205).

When the inference response message 54 to the sent inference request message 52 has been received from all inference processors 21 (step 206), if there is no new fact 761 corresponding to this inference request, the process of (5) is performed (step 209). I do.

If there is this new fact, the inference request message 52 is assembled from all the corresponding new facts 761 based on the new fact queue 76 and the inference request corresponding new fact table 77 (step 207);
Send all inference processors 21 at once (step 203
).

In order to improve efficiency, the new facts 761 are sent all at once to the inference processor 21 as an inference data message 53 when a specified number of new facts 761 are collected, and the inference request message 5 that has already been sent is
It is also conceivable that when the inference response messages 54 for 2 have been received from all the inference processors 21, the inference request message 52 is assembled from only the unsent new facts 761 and sent all at once. However, in this case, inference processor 2
1 is a new fact (i.e., known fact 536) in the inference data message 53 received during the inference request message 52 processing.
is not incorporated into the fact group list 61 as in (2), and after the inference request process is completed and the inference response message 54 is sent back, the above known fact 53 is added.
6 is added to the fact group list 61.

(5) The interpreter processor 11 outputs the inference completion status information and, if necessary, the inference result message 55 in which the contents of the new fact queue 76 are edited to the inference data output device 3 (step 209).

FIG. 14 is a diagram showing another embodiment of the system configuration for realizing the method of the present invention.

1001 is a processing device called an interpreter processor, and 1002 is a processing device called an inference processor. These processors are coupled by a message transmission node 1061.

1009 is a console typewriter, display,
An input/output device such as a process human output device, hereinafter referred to as an inference human output device. The interpreter processor 1001 is
It is connected to the inference user output device 1009 via a bus 1062.

Interpreter processor 1001 has memory 1003. The memory 1003 consists of an interpreter-only memory block 1030 and a knowledge list block 1041.

Interpreter-only memory block 1030 is a memory block that is read and written only by interpreter processor 1001 via dedicated memory access bus 1070.

Inference processor 1002 has inference memory 1004. The memory 1004 consists of a memory block 1040 dedicated to the inference processor and a knowledge list block 1041.

The knowledge list block 1041 is read from the bus 10.
71 locally from each processor,
Writing is performed by the interpreter processor 1001 to all inference processors 1002 simultaneously through a common write bus 1008. Arbiter 1005
performs contention processing between reading and filtration for the knowledge list block 1041 (writing cannot be performed during reading; the reverse is also true). This is realized using dual port memory, etc.

The contents of the knowledge list block 1041 of each processor are all the same.

The operation shown in FIG. 14 will be explained below.

When an inference command is input manually from an input/output device (referred to as an inference output device) 1009 such as a console typewriter, display, or process output device, the interpreter processor 1001 creates inference data from this and sends it to the bus 1008. Knowledge list block 1041 of all processors 1001 and 1002 (control line)
After issuing a simultaneous write request to the knowledge list block 1041 of all processors 1001 and 1002 via the bus 1008 (data line), after writing all the necessary inference data, the bus The inference request is output to all inference processors via (the control line of) 1008.

Note that the inference request may be written as a fact (that is, as a piece of data) in the knowledge list block 1041, and this may be used as drive start data based on the empirical rule stored in the inference processor dedicated memory block 1040.
Is the common bus 1008 an integral processor? 100L
Reasoning process? 1002 via a DMA bus. Therefore, the transmission overhead from the interpreter processor 1041 to each inference processor 1042 is extremely small, and performance can be significantly improved.

All inference processors perform inference in parallel by simply referencing the knowledge list block 1041, ie, without competing memory accesses, and return the results as inference response messages.

The interpreter processor 1001 checks all inference responses returned to the inference request message after responses have been returned from all inference processors or after a certain period of time has elapsed, and if it determines that inference has been completed, the inference processor 1001 outputs an inference result. is output to the inference user output device 1009 as an inference result message. If it is determined that the inference has not been completed, an inference message is created from the inference response message, the inference request to the inference processor is repeated, and necessary information is saved as the inference result.

FIGS. 15 and 16 show an example of the flow of processing in the interpreter processor and inference processor shown in FIG. 14, respectively.

The differences from the process 70- in FIGS. 12 and 13 are as described above, and the other points are the same as those in FIGS. 12 and 13, so a description thereof will be omitted here.

〔Effect of the invention〕

According to the present invention, multiple microcomputers are connected, list-format knowledge data is distributed in the local memory of each processor, and inference processing using this knowledge data is performed in parallel to avoid memory and bus contention. Because LIMP machines can be configured with built-in functions for knowledge bases, practical-scale knowledge base systems (e.g., high-intelligence information processing such as Groduction/Systems with more than 500 rules of thumb) can be implemented using (1) High performance K. (Several ten times more than conventional minicomputers) (2) Flexible and efficient (3) It has the effect of being able to be manufactured at low cost (below the price of conventional minicomputers).

[Brief explanation of drawings]

Figure 1 is a schematic diagram of the configuration of an example of a system that implements the present invention, Figure 2 is a diagram of the configuration of an example of a system that implements the present invention, and Figure 3 shows the data on the bus in the system of Figure 1. Diagrams showing the flow, Figures 4 to 6 respectively show inference request messages,
The format of an example of an inference data message and an inference response message. Figures 7 and 8 are maps of an example of the local memory of the interpreter processor and inference processor, respectively. Figure 9 is the structure of an example of a fact group list and a heuristic rule group list. Figure 10 is a configuration diagram of an example of a new fact queue.
FIG. 1 is a block diagram of an example of an inference result recording location, FIGS. 12 and 13 are flowcharts showing an example of the processing flow of the interpreter processor and inference processor of FIG. 2, respectively, and FIG. FIGS. 15 and 16, which are block diagrams of other embodiments of the system to be realized, are flowcharts showing an example of the processing flow of the interpreter processor and the inference processor, respectively. DESCRIPTION OF SYMBOLS 11... Interpreter processor, 21... Inference processor, 12... Local memory 1 of interpreter processor 22... Local memory of inference processor, 52... Inference request message, 53... Inference data message , 54... Inference response message, 61.
...Fact group list, 62... Immediately known facts, 63... Empirical rule group list, 64... Empirical rule, 65... Condition part,
66...Conclusion part, 651...Condition, 661...Conclusion, 76...New Figure 4 Figure 5 Figure 1 2 Day Z 7 Figure %B Figure q Figure ■ 10 Figure 6 % jl Figure 7 % rz Diagram No. 73 Diagram C ``D'' Name of the person making the amendment (510) Manufactured by Hitachi Co., Ltd. New model Tokyo 212-111.1 (main representative) Subject of amendment 417 of “Detailed description of the invention” in the specification
4 and drawings. Contents of amendment 1, specification, page 7, line 11, “corresponding j is changed to “
I'll take action," he corrected. 2. Same, page 12, line 18, change “if you want to” to “
"Don't do it," he corrected. 3. Same, page 19, line 4, “Processor” 041
Correct J to "Processor 100IJ. 4. Same page, same page, 5th line r104.2" as rl O
Corrected to O2J. 5. In the drawings, Figure 14 is amended as shown in the attached drawings.

Claims (1)

[Claims] 1. In a complex computer system consisting of a plurality of bus-coupled processing units and memory attached to each processing unit, a specific processing unit receives an inference command, and other processing units process the inference command in parallel. Convert it into an inference request so that - Intervention 1
However, in another processing device, a pre-assigned part of the empirical rule data and all the fact data are stored in the memory in the form of a knowledge list connected by pointers, and when the above inference request is received, , check and apply factual data, look for and apply re-emerging rules of thumb, find out whether new facts exist,
A parallel speculative list processing method that returns results. 2. The memory of each processor is divided into memory blocks that only it can read and write, and memory blocks that only it can read and write, but in blue writing, there are memory blocks that only one specific processing device can read and write into the entire memory at once. 2. The parallel speculative list processing method according to claim 1, wherein the knowledge list is placed in the latter memory block.