JPS59157750A - Control system of instruction read - Google Patents

Abstract

PURPOSE:To prevent the degradation of the capacity for branch instructions by suppressing decoding of following instructions and reading out instructions of a branch destination continuously only when these operations are truely necessary in an instruction read controller. CONSTITUTION:A control line 27, which indicates that the instruction stored in an instruction register (IR)5 is a branch instruction, and a control line 29 indicating that the instruction read address indicated by an address adder output latch (AAL)9 is the last 8-byte of a block are inputted to an instruction read control part (IF control part) 15, and the IF control part 15 controls the instruction read operation through IF requests 18 and 19 and selector control signals 22 and 23. If the branch destination instruction address does not exist in the last 8 bytes of the block, 16 is added to the preceding IF address to attain the IF address; and if the branch destination instruction address exists there, 8 is added to the branch destination instruction address to attain the IF address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an instruction read control system. More specifically, the present invention relates to an instruction read control method having a feature in address calculation at the time of a branch destination instruction.

[Prior art]

Generally, in a data processing device, the operand address part of the instruction word set in the instruction register is used by an address adder (AA) to obtain the operand address and the branch destination instruction address at the time of a branch instruction, and these are sent to the storage control device. give to Furthermore, this branch destination instruction address is processed by an address incrementer (AI: Address Increment) in the next cycle.
er ), the instruction read width is increased by the instruction read width, and the address of the branch target subsequent instruction read subsequent to the branch target instruction read is busy being obtained. This method has the disadvantage that one cycle is left until the address of the branch destination subsequent instruction is determined in AI, and reading of the branch destination instruction and reading of the next branch destination subsequent instruction cannot be continued. This problem will be explained later, but if the address of the branch destination instruction determined by AA is the last 8 bytes of a block (for example, 64 bytes) in memory, the address of the branch destination instruction determined by AA is read. There may be cases where the entire branch destination instruction is not included in the 8 bytes to be received, and only the first half of the branch destination instruction is obtained. Therefore, when a branch is established by a branch instruction, there is a problem in that execution of the branch destination instruction cannot be started until the instruction is read by the next address calculation by AI.

As a method to solve this problem, there is a method in which the address for reading the subsequent instruction at the branch destination following the reading of the branch destination instruction is found once using 1iAA, and the address for reading the subsequent instruction is found using AI. This method has the advantage that reading of the instruction at the branch destination and subsequent reading of the instruction can be performed consecutively. Since the instruction at the branch destination is read using the AA in two consecutive cycles and the read request is issued, there is a drawback that decoding of the subsequent instruction following the branch instruction is stopped and performance is degraded.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide an instruction read control system that reduces performance degradation during branch instructions.

[Summary of the invention]

The present invention provides the branch instruction address obtained from the adder for obtaining the operand address including the branch destination instruction atbis again to the adder and adds the instruction read width to obtain the address for reading the branch destination subsequent instruction. It is characterized by providing a previous succeeding instruction address to an incrementer and selecting whether to change the instruction read width to be added to the incrementer or to obtain a branch destination subsequent instruction address in the incrementer based on the branch destination instruction address from the adder. shall be.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to one side.

FIG. 1 does not show a block diagram of a portion of the data processing device related to instruction reading.

Storage control unit (SCU)
ol[Jnit) 1 is used to read instructions from the storage device 2. 5CU1 sends an instruction read request (
IF request) 18 or IF request 19. When an IF request 18 is issued, 8 bytes or 16 bytes of instruction data specified by an instruction read address (IF address) 16 is read from the storage device 14. When the IF request 19 is issued, the instruction data specified by the IF address 17 is
It is read from the storage device 2.

The read instruction data is sent to the instruction buffer 3 via the data line 6.

FIG. 2 shows the lower bits 26 to 26 of the 32 bits of the instruction read address. 31 is a diagram showing the relationship between command data read out and command data read out. Access to storage device 2 from 5CUI is as follows:
This is done in units of blocks, for example 64 bytes. When the instruction read address is not in the last 8 bytes of the block, 16 bytes of instruction data including the instruction read address are read from the 8-byte boundary. When the instruction read address is in the final 8 bytes of the block, the final 8 bytes of instruction data are read. For example, bits of the instruction read address are "0OOxxx""110xxx"(x&
! "O'.

``1'' indicates that the instruction data to be read does not change no matter which one is taken) indicates that 16 bytes of instruction data within the 16-byte boundary including the byte position of that address will be read, and the final block of the block will be read. Indicates 8 bytes'
"IIIXXX" indicates that 8 bytes of instruction data within the 8-byte boundary including that byte position will be read. Since the instruction length of one instruction is various such as 2 bytes, 4 bytes, 6 bytes, etc., the instruction read Bits 26-31 of the address
If the command is 111XXX'', there is a case where one instruction is not entirely included in the 8-byte instruction data that has been read.

For example, a 6-byte long instruction starting from "111010" reads only the first 4 bytes, and after address calculation, one instruction is completed by reading from the next block.

Referring again to Figure 1, the trap, instruction buffer (from: In
5truction Buffer) 3 is 5CU
This is a register for temporarily storing instruction data read from I. The shifter 4 shifts the next instruction to be decoded to the left, and passes the instruction register (I) through the data line waste.
R: Induction Register)
Transfer to 5. In5 takes in instructions one by one from In3 and holds the instructions during instruction decoding and operand address calculation. The operation field of the In5 instruction is data, 1! The signal is sent to the decoder 6 via the Chinese character. The decoder 6 decodes the operation field of the instruction from In5 and outputs a control signal according to it.

Particularly relevant to the present invention, the control signal n is turned on at the time of a branch instruction.

Atto v, x adder (AA: Address Add
er) 8 is when the selector control signal n from the instruction read control unit 15 is on, game) 20a, 20b, 2
0c selects the input on the left side of the figure and outputs the address adder output launch (AAL: Address Adder
The address of Latch ) 9 is input to AA8 via address adder output launch 10 and 8 is added to it. The addition result is stored in A and AL9 again. When the selector control signal n is off, G) 20g, 20
b, 20c select the inputs on the right side of the diagram, and input the IR
Generates the index register and base register specified by s into a general shifter (GR).
l Register) 7 and set these values and the displacement value specified by In5 to A.
The operand address or the branch destination address of the branch instruction is obtained by addition at A8. The addition result is AAL9
is stored in

The gate 21 selects the input on the left side in the figure when the control signal from the instruction readout control section is on, and selects the input on the right side in the figure when it is off. Instruction read register (IFR: I
n5truction Fetch Register
) 11 is an address register for reading out instructions continuously. Instruction read address incrementer (IFAI:
IF Address Incrementer)
12 adds the instruction read width of 8 or 16, or the instruction read width of 2 times, to the instruction read address specified by IFRII, and updates the instruction read address. IPA
The output of 112 is the instruction read incrementer output latch (IFAI
L: I FA I Latch) 13, I
Stored in FRII. The last 8 bytes of the block detection logic has the same configuration as the detection logic 14, and detects that the address in IFRll points to the last 8 bytes of the block.
I F'A I 12 adds 8 to the address of IFRll when the detection logic output 31 is on, adds 8 to the address of IFRll when the control signal n is on, and adds 8 to the address of IFRll when the detection logic output 31 is on;
Add.

Block last 8 byte detection logic (L, DWDL: La
5t Double Word Detection
The details of Logic ) 14 are shown in FIG. 3, and detect that the address indicated by AAL 9 is in the last 8 bytes of the block. The fact that the instruction read address is in the last 8 bytes of the block means that the 6th to 4th bits from the lower order of the instruction read address (in this example,
It is detected that bits 26 to 28) are all 1, and it is detected by the AAND gate 140, and the condition jJ
'- When established, the output line 29 is turned on.

In this embodiment, the effective instruction length to be read in the first branch destination instruction read is small, and the second instruction read must be performed as soon as possible. This is detected by the fact that the branch instruction read address is in the last 8 bytes of the block.

Referring again to FIG. 1, the instruction read control unit (IF control unit) 15 performs control to indicate that the instruction stored in In5 is a branch instruction. tM27 and the control [29 indicating that the instruction read address indicated by AAL9 is in the last 8 bytes of the block are input, and the instruction read operation is controlled via ■F request 18.19 and the selector control signal η, etc. .

Setting the instruction read address to AAL9 by AA8,
Setting of the instruction read address to IFRII by the IPAI 13 can be performed in parallel.

Details of the instruction read control section 15 are shown in FIG. The instruction read control unit 15 receives a control f indicating a branch instruction from the decoder 6.
#A27 Flip-flop 1 set by signal
50, AND gate A1Fl”151 connected to it
~154 serial connection and block last 8 byte detection line 4 from block last 8 byte detection logic 14 NOT
It is composed of a series connection of AND gates FF155 to FF158. I F IJ Quest 18 is F
This is the OR output from the OR gate of the F150 and FF152 outputs. This is the OR output of IF request H"1 FF154 and 'F'F158FF151 output OR. The select control signal 22 is the FF151 output,
Select control signal 23&”!, FF 151 and FF
This is an OR output from an OR gate with 155 outputs.

FIGS. 5(a) and 5(b) are diagrams showing the instruction read operation. FIG. 5(a) shows the case where the branch destination instruction address is not in the last 8 bytes of the block, and FIG. 5(b) shows the instruction read operation of the block. Each case in the last byte is shown.

First, the case where the branch destination instruction address is not in the last 8 bytes of the block will be explained with reference to FIG. 5(a). If the instruction set in R5 is a branch instruction, the control line 27 is turned on, F F 150 is set, and IF request 1
An 8 is rolled. In parallel, the branch destination instruction address is obtained in AA8, and IF'FF reply 16 is obtained from AAL9 at the same time as 5.
Sent to CUI. Since the control line drawing is off, F F
155 is set and the AAL9 branch destination address is I.
Transferred to FRII.

When FF155 is reset, FF156, 157, and 158 are set in sequence. Since both the output between the detection logics and the control line η of IFAI12 are off, the contents of IFRII are added by 16 and set to IFRII again. FF158
With this set, IF request number 9 is sent to 5CUI. The IFFF reply at this time is the IF which is the output from IFRII.
FF less 17, +16u to previous IFFF less 16
address. As shown in FIG. 5(a), in this case, one cycle is left between the IF request 18 and the next IF request 190, but decoding of the subsequent instruction can be started at this time.

Next, the case where the branch destination instruction address is in the last 8 bytes of the block will be explained with reference to FIG. 5(b). In this case, F
IF request 18 is issued by setting F150, but since the branch destination instruction address requested by AAL9 is in the last 8 nodes of the block, the control line drawing is also turned on, and FF151 is set. . FF
With the setting of 151, both the control line 22 and the line A are connected, and the branch destination instruction address obtained from AAL9 is added by 8 by AA8 and transferred to IFRII. F
When F 151 is set, F F 152 is set, and I'F request 18 is issued again, and the address for reading the subsequent branch destination instruction of AAL9, which is added by 8 to the previous branch destination instruction address, is sent to the SCU as I" address 16. Since the control line n is on, the process F' A I 12 modifies the address of IFRII (equal to the IFFF reply 16 issued at the first branch destination instruction address), and transfers IFRII. By setting FF152, FF153.154 is set, IF request 19 is issued, and the address of IFRII is transferred to 5CUI as IFFF reply 17. Subsequent command reading updates the address of IFRII sequentially. In this case, the subsequent instruction is decoded after IF request 19 in FIG. Even if the address is in the last 8 bytes of the block, there is no delay in starting execution of the branch instruction.

〔Effect of the invention〕

According to the present invention, it is possible to suppress the decoding of subsequent instructions and to continuously read instructions at the branch destination only when it is truly necessary. It is possible to simultaneously minimize two types of performance degradation caused by a delay in decoding due to the absence of an instruction or a subsequent instruction at a branch destination in the instruction buffer. This makes it possible to improve the performance of the instruction readout control device as a whole.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram explaining the relationship between the instruction read address and the instruction data to be read, and FIG. 3 is the details of the logic for detecting the last 8 bytes of the block in FIG. 1. FIG. 4 is a diagram showing details of the instruction read control section of FIG. 1, and FIG. 5 is a diagram for explaining an embodiment of the present invention. 1... Storage control device, 2... Storage device, 3...
- Instruction buffer, 4... Shifter, 5... Instruction register, 6... Decoder, 7... General purpose register, 8... Address adder, 9... Address adder output latch, 11. ...Instruction read register, 12...Instruction read address incrementer, 14.
...Block final 8 byte detection logic, 15...Instruction readout control unit, 16-17...Instruction readout address,
18-19...Instruction read request. Figure 1 Figure 2 Figure 3 Figure 5 (α) (1))

Claims (1)

[Claims] (11) Obtain the operand address including the branch destination instruction address using an adder and use it as the read address, and receive the address from the adder to read instructions continuously, such as reading the branch destination subsequent instruction following the branch destination instruction. In an instruction read control device that uses an incrementer to obtain an address for a branch destination as a read address, a selection means responsive to the branch destination instruction address obtained from the adder is provided, and the selection means causes the instruction address obtained from the adder to be read. An instruction to give the branch destination instruction address again to the adder, add the instruction read width to obtain the address for reading the branch destination subsequent instruction, and give the branch destination subsequent instruction address to the incrementer, and add it to the incrementer. An instruction read control system characterized in that it is selected whether to change the read width or to obtain the branch destination subsequent instruction address in the incrementer based on the branch destination instruction address from the adder.