JPS59156033A - Variable delay equalizer - Google Patents

Abstract

PURPOSE:To decrease change in amplitude even when an amount of delay is changed by connecting a delay section and an amplitude correcting section in cascade and setting a weight coefficient value at the amplitude correcting section to a square of the weight coefficient value of the delay section so as to correct an amplitude distortion generated at the delay section by the amplitude correcting section. CONSTITUTION:The amount of delay of delay lines 3, 4 of the delay section 10 is set respectively to T, 2T and the amount of delay of delay lines 13, 14 of the amplitude correcting section 20 is set respectively 2T, 4T being two times those of the amounts T, 2T. Suppose that no signal delay exists other than coefficient weight circuits 7, 17a, 17b and a fixed attenuator 15, no time delay exists other than the delay lines, and let the coefficient of the coefficient weight circuit 7 be (l), and the coefficient combining the coefficients of the circuits 17a, 17b and the fixed attenuator 15 be (k), then the overall amplitude characteristic is the addition of the amplitude characteristics of the delay section 10 and the amplitude correcting section 20. The coefficient weight circuits 7, 17a, 17b are interlocked mutually and have the same coefficient (l), then the relation of k=l<2>/2 is obtained when the coefficient of the fixed attenuator is 0.5. Thus, the term in which the amplitude is changed against frequencies in the range of l<1/2 becomes very small. Then, only the amount of delay is changed without amplitude change.

Description

[Detailed description of the invention] This release F! A generally relates to variable delay equalizers, and more specifically to l using transversal filter theory.
Regarding variable delay equalizer.

FIG. 1 is a conceptual diagram showing an example of T i) MA communication which is the background of this invention. TL) MA communication is used, for example, in satellite communication, such a satellite communication system comprising a plurality of earth stations ES, ES, . . . and a common communication satellite C8. The earth station ES includes a transmitting device TRA and a receiving device REA. To the modulator included in the transmitter'f RA (OL)
The signal modulated by equalizer EQL and transmitter T
It is sent from antenna AE to antenna AS of communication #Mcs via R. The signal is frequency-modulated within the satellite and sent to another earth station ES-. Similarly, a signal from another earth station ES- is received by the antenna AE of the earth station ES through the communication satellite C8, and the received signal is transmitted to the receiving device R.
Given to EA. The receiving device REA passes through the receiver ME, the equalizer stopper L, and the demodulator DEN with 4! will be adjusted. It is known that the transmitter 7rR and receiver RE of the earth station ES and the transmission line and transmission system of the communication satellite produce &width distortion and/case or group delay distortion, respectively. In particular, the high-power amplifier (not shown) included in the communication satellite C8 is used in a highly saturated state due to size, cost, stability, and other reasons. Therefore, AM-PM conversion occurs in this high-power amplifier, resulting in a phase change as shown by line A in FIG.

Incidentally, in FIG. 2, the line B indicates the outgoing camber T0.The above-mentioned phase change results in group delay distortion.

These amplitude distortions and group delay distortions are each subjected to amplitude equalization or delay amount equalization by transmission system EQL. Conventionally, such an equalizer f>QL is generally constructed to include an 118fl constant amplitude equalizer FAE, a defined delay equalizer FDE, and a variable equalizer ME, as shown in FIG. ing. Depending on the actual amount of distortion or group delay distortion,
Fixed amplitude equalizer FAE or (b) delay equalization sense FL
) Either or both of E is omitted.

T1) In the MA communication system, which is the background of this invention, the signal is transmitted and received after the start of the test, and the amplitude characteristics and group delay characteristics as described above are measured. It is impossible to measure the transformation type. This is because such communication systems are time-divided so that one earth station is connected to I! l! This is because the time that the I line is occupied is extremely short.

Therefore, when a new earth station joins such a communications satellite system, it is necessary to search for the optimal point where the amplitude distortion and group delay distortion are minimal, and therefore the BER (sign error 4) is minimal. For this purpose, a blow-off device ME as shown in FIG. 3 is used.

FIG. 4 shows a conventional variable equalizer ivl which is the background of this invention.
This is a circuit diagram showing an example of E. In the fourth case, the input signal applied from the input terminal 1 is distributed by the distributor 2. The @-signal distributor 2 uses, for example, a known hybrid circuit or the like to distribute each bias into three signals of the same level. A delay line 3 that seals the delay amount T is inserted in one of the three signal paths, a delay line 4 having an Ii delay line 2T is inserted in the other signal path, and the remaining 1
A polarity inverter 5 is inserted in one path. Polarity reversal H
85 is a known transformer, transistor, etc.
Onsei Awa, move 5 gills h6 signal 180・□. The signal from the delay line 4 and the signal from the polarity inverter 5 are combined by a combiner 6 and then applied to a variable coefficient loading circuit 7. The variable coefficient loading circuit 7 is composed of a double-balanced mixer having a polarity inversion function, and the output signal therefrom is combined with the output signal (main signal) from the delay line 3 in a combiner 8.

Here, it is assumed that there is no signal attenuation except for the variable coefficient loading circuit 7, and that there is no time delay except for the delay lines 3 and 4.
If the delay of No. 8 is used as a reference (0), the output signal B (b) obtained at the output terminal 9 is expressed by the following equation (1).

B(Q))=cnsωt-/Cogω(t+T)+z
cosω(t-T) Xcos(ωt-π/2 +jan-1(l/2t s inωT))
...(1) The characteristic GB(
The characteristics τB of delay amount and delay amount with respect to frequency are given by the following equations (2) and (3), respectively.

GB(-2201og((1+2z2)-2z2cos2ωt)・
(2) τB (b) = -2iT (3) However, ω is the angular frequency, and ω = 2πf (f is the frequency &). The change characteristics of the amplitude characteristic GB) and the delay characteristic τB (→ when the coefficient l is 0 are shown in FIG. 5.
Figure ^ shows the amplitude characteristics, and Figure 5 (B) shows the delay characteristics, which change in the direction of the arrow when the coefficients #: and 1 are increased, respectively. In other words, as shown in Figure 5, the fourth
In the illustrated example, if the coefficient l is changed in the coefficient loading circuit 7, the amount of delay also changes. However, in the example shown in Fig. 4 as well, not only the delay amount but also the amplitude changes as the coefficients # and l change, making it extremely difficult to use it as a variable equalizer in a TDMA communication system. It was a cone.

Therefore, the main object of the present invention is to develop a variable delay system that can be used effectively in, for example, a '1'' DMA communication system, in which the change in amplitude is extremely small even when the amount of delay is changed. The aim is to provide a means to transform the situation.

To summarize, the present invention includes a delay unit that combines a signal that is advanced by a certain time and a signal that is delayed with different polarities when the absolute amount of delay of the main signal is used as a reference, and adds a weight with a first coefficient; an amplitude correction section that combines a second predetermined time advance signal and a delay signal based on the absolute delay amount of and adds a second coefficient as a load, and the delay section and the amplitude correction section are connected in cascade. In addition, the amplitude distortion generated in the delay section is corrected by the amplitude correction section by setting the weighting coefficient value in the amplitude correction section to the square product of the loading coefficient value of the delay section.
This is a variable delay equalizer.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to sections.

FIG. 6 is a block diagram showing a variable delay equalizer used in a TDMA communication system as an embodiment of the present invention. In FIG. 6, a signal from an input terminal l is applied to an output terminal 9 through a delay section 10 and an amplitude correction section 20. If this iT variable delay equalizer is used, for example, in a TDMA communication system as shown in FIG. , if it is included in a communication system, one input terminal will be connected to the receiver WE, and the output terminal 9 will be connected to the demodulator υzMK.

In this FIG. 6, the configuration of the delay section lO is as shown in FIG. 4 00T.
Since it is the same as the variable equalizer ME, its explanation will be omitted. On the other hand, the amplitude correction s20 cascade-connected to this delay unit 1O includes a divider 12 that divides the input signal into three parts, and two signals of the divided outputs are each 2T.

Delay that delays by 4T,! 13 and 14, delay line 1
a combiner 16 that combines the signal passed through 4 and the undelayed signal, and two series-connected coefficient loading circuits 17a that add a coefficient l to each of the combined outputs.

17b1 A fixed attenuator 15 that fixedly attenuates the output of this coefficient loading circuit (17b), and a synthesizer that synthesizes the output signal of this fixed attenuator 15 and the signal that has passed through the delay line 13, and outputs it to the output terminal 9. It is composed of 18 parts.

Note that the coefficient loading times of this amplitude correction section 20 @ 17a%
The settings of the coefficients /, / (i.e. /2) of the delay unit 17b are linked with the settings of the coefficient &l of the coefficient loading circuit 7 of the delay unit 10. In other words, if the delay unit 10 sets tt-, the amplitude correction unit 20 automatically adjusts the coefficient 12. is configured to be set to .

Here, the principle and operation of the amplitude correction section 20 shown in FIG. 6 will be explained using a known variable amplitude equalizer.

FIG. 7 is a circuit diagram showing an example thereof, and is substantially the same as the delay section 10 shown in FIG. 6 except that the polarity inverter 5 is omitted.

That is, the input signal from the input terminal l is distributed by the distributor 2. The signal passing through the delay line 4 is combined with the signal not passing through the delay line by a combiner 6, and is applied to a combiner 8 through a variable coefficient loading circuit 7 having a coefficient k. In this way, in the synthesizer 8, the delay line 3
The main signal passed through the variable coefficient loading circuit 7 and the sub-signal passed through the variable coefficient loading circuit 7 are combined and output to the output terminal 91.

Here, assuming that there is no signal attenuation except for the coefficient loading circuit 7, and that there is no time delay except for the delay lines 3 and 4, and the delay of the main signal is set to 0, the output signal A derived to the output terminal 9' (e) is given by the following equation (4).

A(o)=cos (11t+kcosω(t)kcosω(t-T) =(1+2kcosωT)cosωt −・
-.-(4) Also, the frequency characteristic GA (RI) of the output signal A is given by the following equation (5).

GA ((=1)=20top(1+2kcosωt)
--(5) However, the delay characteristic τA) is flat. The change characteristic of this amplitude characteristic GA (-) with respect to the coefficient k is shown in FIG. 8. If the coefficient k is increased, the amplitude changes in the direction of the arrow. That is, in FIG.
By changing the coefficient k of the variable coefficient loading circuit 7, a variable amplitude equalizer in which only the amplitude changes without changing the amount of delay can be obtained.・Also, as shown in FIG. 8, the amplitude repetition period of this variable amplitude equalizer is 1/'r, and on the other hand, the amplitude repetition period of the delay unit lO, that is, the delay equalizer of FIG. The period is 1/2T as shown in FIG. 5(8).

Therefore, if the repetition period of the amplitude characteristic of the amplitude correction section 20 is halved to be the same as the period of the delay section 10, and the amplitude polarity is reversed, the amplitude distortion generated in the delay section 10 can be corrected by the amplitude correction section 20. Now that you understand what can be done, the operation shown in FIG. 6 will be explained. In FIG. 6, the delay lines 3.4 of the delay section 10 have delay amounts T and 2T, respectively, and the delay lines 13.14 of the amplitude correction section 20 have delay amounts of 2 r and 4T, respectively, which are twice the delay amount of the delay section 10. Denotes the delay setting.

In this state, the coefficient loading circuits 17.17a, 17
It is assumed that there is no signal attenuation except for the fixed attenuator 15 and the fixed attenuator 15, and that there is no time delay except for the delay line.
If the coefficient - which is the sum of 5 is k, then the delay s10 and the output signals GB (b) and GA (b) of the amplitude correction section 20, respectively.
is expressed by the above-mentioned equations (2) and (5). In this case, since the delay section 10 and the amplitude correction section 20 are connected in cascade, the overall amplitude characteristic Gc (cu) is the sum of these amplitude characteristics and is expressed by the following formula.

GC (b) = GB ■) 10 GA (b))
...(6)=201oP(1+2kco
s2ωT)v'(1+2/2no2i2cospfr=
201oyJ[1+2z2)+(4k(1+212)−
2z2) cos2ωT+(4 to 2(1+272) -8
kz2) cos22ωT-8 to 212cos32ωT]
(7) Here, the coefficient loading circuits 7.17a, 17b are interlocked with each other and have the same coefficient l, and the fixed attenuator 15 has an attenuation of 6 dB or a coefficient of 0.5. Then k=0.5
X/X/=H. Substituting this into equation (7) gives GC)=201oyV-[(1+212)+4z2-
j-voice 2ωτ10+(216-31')cos22ωT-
2/”cos32ωT], (8).Compared to the conventional equation (2), the term that changes with the amplitude frequency in the range z<1//r is very small. .

On the other hand, the delay characteristic τC in this case is the addition of the delay section 10 and the amplitude correction section 20, but since the amplitude correction section 20 has no delay characteristic, the overall delay characteristic τC (c) is the same as the above-mentioned (3).
τB shown in the formula becomes). That is, τC(to) = τB
(b).

FIG. 9 shows the amplitude characteristic Gc(
b) and delay characteristic τC).

Note that this Fig. 9 shows the change when i > 00, but when t < 0, the sign of τB in equation (3), that is, τC, is reversed, and the advance of the delay amount and the delay become the standard. It is opposite to the value. Also, for Gc in equation (8)), ! Even if <0, if the absolute values of l are equal, the same f+& will result.

In other words, when l changes from the + side to one side, the delay changes as shown in the arrow in Figure 9, but the amplitude characteristic (to JC) changes from the characteristic of No. 9181 (5). Just give it back.

As explained above, the embodiment of FIG. 6 can change only the delay amount without changing the amplitude. That will be understood. Therefore, such a variable delay equalizer has T
If used as a Machichi equalizer in a DMA communication system,
Since only the degradation in BER due to group delay distortion can be equalized independently, it is easier to operate to find the optimal point than in the conventional case where the amplitude and delay part vary all at once. is extremely easy to do.

In addition, in the above embodiment, the coefficient loading circuit 7.17a,
17b is constructed with a double balanced mixer or the like that includes polarity inversion, but if the variable range is limited depending on the application, it may also be constructed with a variable attenuator or the like that does not include polarity inversion. Further, the polarity inverter 5 is not limited to a 180° phase shifter, but may also be a 180° combiner, a divider, or a 90° combiner/divider. For example, by arranging a 180° combiner in the combiner 6, the functions of the polarity inverter 5 and the combiner 60 may be provided.Similarly, the input side of the combiner 6 and the output side of the distributor 2 can each have a 90° combiner. A container or distributor may be used.

In addition, the amplitude of the signal input to the coefficient loading circuits 7.17a, 17b and the fixed attenuator 151d combiner 8.18 may be made to have a constant northing ratio, and the insertion position may be any position as long as the requirements are met. Often, for example, 15 fixed attenuators can be provided between the distributor 12 and the combiner 16.

11 to 14 show other embodiments of the present invention.

In the embodiment shown in FIG. 6, the delay section 10 and the amplitude correction section 20 each have one stage, but as shown in FIG. is also possible.

Further, as shown in FIG. 12, an n-stage delay section 10 and a one-stage) Y width correction a. . , Yo□1sei. By setting the fixed attenuator 15 in the vibration correction section 20 to a value that minimizes the amplitude characteristics, interlock compensation of the coefficient loading circuit is possible. Although FIG. 12 shows the one-stage amplitude correction section 20, the same applies to the m-stage amplitude correction section 20 by simply setting the value of the fixed attenuator 15. The embodiments shown in FIGS. 11 and 12 are also effective as means for widening the variable range of the variable delay equalizer.

In the embodiment shown in FIG. 6, a delay line is provided after distributing the input signal, but as shown in FIG.
．． It is also possible to provide 13 alternately.

Further, as shown in FIG. 14, the delay line 3.4.13.14, polarity inverter 5, and synthesizer 6 can be configured in two stages or in n stages. Here 31.32 is a fixed attenuator and 3
2 is set to the square of 31, and (33) to (40
) is a delay line.

As described above, according to the present invention, the delay section and the amplitude correction section are connected in cascade, and the amplitude distortion generated in the delay section is corrected by the amplitude correction section, so that the desired amplitude characteristic can be maintained without changing. The amount of delay can be set variably, and if the coefficient loading circuits of the delay section and amplitude correction section are linked, the amount of delay can be easily adjusted and the delay equalizer with high accuracy can be set. It can be served cheaply.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram showing the concept of a TDMA satellite communication system, Figure 2 is a characteristic diagram showing the characteristics of a high-power amplifier included in a communication satellite, and Figure 3 is an example of an equalizer used in a TDMA satellite communication system. 4 is a circuit diagram showing an example of a conventional variable delay equalizer, FIG. 5 is a characteristic diagram showing the amplitude and delay characteristics of FIG. 4, and FIG. 6 is an embodiment of the present invention. 7 is a circuit diagram showing an example of a variable delay equalizer, FIG. 8 is a characteristic diagram showing the amplitude characteristics of FIG. 7, and FIGS. 9 and 10. FIG. 6 is a characteristic diagram showing the amplitude and delay characteristics of the embodiment, and FIGS.
FIG. 4 is a diagram (!27 diagram) showing another embodiment of the present invention. In IA, 2.12 is a distributor, 3.4.13.14 is a delay line, 5 is a polarity inverter, 6.16.8.18 is a combiner, 7
．． 17a 117b coefficient loading circuit, io is delay section,
20 is an amplitude correction section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Id Kuzuno - Figure 9 Figure 10

Claims (1)

[Scope of Claims] (1) A synthesizer that combines two sub-signals that are delayed by one hour each in the leading direction and the lagging direction with respect to the main signal, and one of which has the polarity inverted. , has a coefficient loading circuit that adds a first coefficient to this composite output signal, and a synthesizer that combines the output of this coefficient loading circuit with the main signal, and by changing the first coefficient, A delay unit that controls the amount of delay, a synthesizer that combines two sub-signals that are delayed by 2T time in the leading direction and the backward direction based on No. 14g, and adds a second coefficient as a weight to the combined output. It has a coefficient loading circuit, a synthesizer that combines the output signal of the coefficient loading circuit and the main signal, and an amplitude correction section that controls the amplitude by changing the second coefficient, the delay section and the amplitude The correction section is connected in cascade, and the above-mentioned second
A variable delay equalizer characterized in that the coefficient a: is set to the square of the first coefficient. (2) The variable delay equalizer according to claim 1, wherein the coefficient loading circuits of the delay section and the amplitude correction section are connected to each other and load the twelfth and second coefficients. .