JPS59154875A - Absence communication system of picture signal - Google Patents

Abstract

PURPOSE:To realize absence communication with the remarkable flexible use of termial device and reliability by discriminating whether or not a picture terminal device is in the state possible for absence communication in case of absence communication, occupying selectively a field and transferring a picture signal. CONSTITUTION:When an incoming call exists from other node and an information processor with a terminal device in the state of absence reset 6, the mode transits to a state 7 preparing an absence response. The self-closing of the power supply of the terminal device and the self-diagnosis whether or not the preparation of receiving such as receiving recording paper or the like is finished are checked at the state 7, and when the reception is possible as the result, a corresponding control code is transmitted to transmit to a receiving state 8. If the receiving is disable, a control code signifying it is transmitted to restore to the absence reset state 6. The terminal device performs the receiving or the standby of receiving and when the received message block is excellent, the control code requesting the next block is transmitted to transit to the standby state 10.

Description

[Detailed Description of the Invention] The present invention relates to an absent communication method for image signals, and in particular to an absent communication method for image signals that transfers image signals from a processing system to a remote image terminal device by absent communication. .

Conventionally, facsimile communication has been carried out by switching lines between facsimile terminal devices. Transmitting an image signal stored in an image information file of a central processing system from the processing system to a facsimile terminal, or transmitting a facsimile signal from a sending facsimile terminal to a receiving facsimile terminal by storing and forwarding. was not carried out.

An image signal in which image information is encoded as a mere surface pattern has an extremely large amount of signal compared to a data signal in a narrow sense in which the meaning of the information is encoded. In a system in which a plurality of facsimile terminal devices share image information files of a central processing system, the amount of accumulated image information becomes enormous. One advantage of shared use systems is that they increase the efficiency of hardware and software utilization;
In a file system for shared use of image information, this enormous amount of information makes it difficult to provide diversity in applications by users, and this advantage is not fully utilized.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal absent communication system that can transfer an image signal such as a facsimile to a terminal device by absent communication.

Note that in this specification, the term "code" is interpreted in a broad sense to include not only data that encodes a meaning, but also data that encodes a mere superficial pattern such as image information.

1--1 The configuration of the present invention will be described below based on examples thereof.

Referring to FIG. 1, a loop-shaped data communication network α is shown. The loop α includes nodes Tl, . . . , Ti, . Note that the information processing device S also functions as a node in this loop α.

The code format flowing through this loop-shaped transmission link consists of repeated transmission frames of fixed length, each frame consisting of a code sequence or codeword according to algebraic laws. Each node T
i shares one transmission frame, and the information symbol part of the transmission frame circulates among the stations in the loop α.

The information symbol portion of the transmission frame consists of a plurality of parts as shown in FIG. That is, a communication information section 100 that includes communication information, and a control section 1 that forms a control channel that includes control information such as call information of the transmission frame 102.
It is 04. As shown in the same figure, this starts with the reference numeral 101.
3, a redundancy cyclic check (CRc) code 10B and a termination code 110 are added to form a transmission frame 102. Transmission frame 102 (7) Each part is divided into a plurality of fields, and each field forms a communication channel between each node and information processing device.

The nodes Tl, , , , Ti, , , TN are generally shown as nodes Ti in FIG. It has a register RD. These terminal devices include image terminals such as facsimiles that transmit and receive image signals. Therefore, the code word, that is, the code sequence included in the transmission frame 102 includes a signal obtained by encoding this image information. Note that it is advantageous if these image terminals are configured to allow absentee communication.

The transmission path from the upper station Ti-1 of the loop α is the demodulator DEH.
The transmission path to the lower station Ti11 is the modulator NOD.
be accommodated in. As shown in the figure, this node includes a receiver R2 that receives signals from an upper station, a decrambler DS that descrambles the received scrambled signal, and a transmitter that transmits whether or not the received code complies with algebraic coding rules. A checker PR1 inspects the function code of the frame 102, for example the starting code 10B, and corrects errors. A shift register SR1 serves as a buffer for temporarily accumulating code words. 102, and a scrambler SC for scrambling code words of this frame. These circuits are made up of a series of shift registers.

This circuit configures a transmission frame and performs encoded transmission, and reliably maintains synchronization and self-corrects errors to reduce the bit error rate. If self-correction is not possible, retransmission will be performed.

The transmission and reception of signals with the terminal device is carried out in the shift register SR.The contents of the shift register SR are transferred to the reception register R1) at the timing determined accordingly, and then the contents of the shift register SR are transferred to the transmission register S.
This is done by updating the contents of shift register SR with the contents of D.

More specifically, the checking unit PR responds to a bit clock supplied from a clock source CLK, which will be described later, and checks whether the code word descrambled by the descrambler DS complies with the law of algebraic encoding. and save the results. This is transferred to shift register SR.

Shift register SR consists of a register circuit (not shown) that stores this code word and a clock circuit (not shown) that controls its contents. This clock circuit is reset when the checker PR determines that the code word follows the algebraic coding rule, thereby synchronizing the transmission frame.

The shift register SR realizes a buffer function between the transmission system and the terminal device, and forms an information symbol portion of the transmission frame 102 transmitted from the transmission path 212. Of the information symbol part input from the inspection unit PR to the shift register SR, the part to be received by the terminal device is specified by the clock circuit of the inspection unit PR, and this part is transferred to the terminal device and Transmission information from the device is input and the contents are updated. Therefore, the information symbol portion output from the shift register SR is partially updated by the terminal device, and the frame forming unit PS performs algebraic encoding processing to form the transmission frame 102. This is scrambled by the scrambler SC and sent to the transmission path 212.

The receiving register R0 is connected to a terminal device (not shown),
The contents of the shift register SR are transferred to the receiving register R[l at the time when the transmission frame forming the codeword is formed in the shift register SR. Also, the transmission register SD
transfers the transmission information prepared from the terminal device at the same time to the shift register SR. Although these transmitting and receiving registers SD and RD have the same configuration for each station on the loop α, the method of using these registers may differ depending on the terminal device, node, and information processing device used by the user.

In this embodiment, the transmission frame 102 has a function code at the beginning. This is detected by the inspection unit PR, and the contents of the register that stores the inspection result as to whether or not the code word conforms to the algebraic encoding rule is transferred to another register. The above-described error correction is performed based on the contents of the latter register, and the contents of the former register are reset in preparation for the next transmission frame. This improves transmission efficiency. The transmission link in the loop network α transmits such a codeword sequence, and this transmission frame 1
02 is divided into multiple fields as described later.

The line sides of the modulator MOD and the demodulator DE may be connected to a two-wire line through a two-wire/four-wire conversion circuit (not shown). In that case, the balance of the conversion circuit is maintained by automatic control and bidirectional transmission is possible.

Node Ti has a master clock source CLK, which has a voltage controlled oscillator whose fundamental frequency is automatically adjustable. Further, a sample value data processing system TI is provided, which detects a signal approximately proportional to the timing shift of the received bit clock from the baseband signal received by the receiving section R. The sampling clock is a bit clock, and the master clock source CL outputs a voltage that controls the phase of the clock in a direction in which the timing deviation is 0.
It is supplied to the oscillation control terminal 200 of K. The master clock source CLK supplies a bit clock from an output terminal 202 and a multiphase operating clock from an output terminal 204 to each circuit as shown.

In the loop α in FIG. 1, node Ti is a clock master station for synchronizing the operating clocks of each station in the entire system, and is also a control station for allocating transmission channels. When the node Ti shown in FIG. 3 is used as a clock main station, the connection 200 from the sample value data processing system TI to the clock source CLK is deleted, and the connection 208 from the sample value data processing system TI to the demodulator DEN is used. Information regarding the timing deviation is received by a delay adjustment circuit (not shown) of the demodulator DEH to extract synchronization of the bit clocks.

Furthermore, in the case of becoming clock dependent due to timing, the clock source CLK has a voltage controlled oscillator, and the connection 208 from the timing circuit TI to the delay adjuster DEN is deleted.

The information processing device S is an information processing system that is shared by each node. This allows all the information channels of transmission frame +02 to be used, and time-division multiplexing is performed on tasks using the information channels used by each node. The number of information channels is given by each node Tl, , , Ti, , ,
, , may be less than the total number of terminal devices connected to the information processing device S, each terminal device selecting one of the information channel fields available in the node in which it is accommodated communication.

Each node Ti other than node T1 in loop α uses one field 104 in the same manner. The main station node T1 transmits a code 1 (18) starting at a predetermined time interval τ according to the control channel field of the sending register SD, and examines the signals from each node sent back on the control channel of the receiving register RD.

Therefore, the starting code 10B is divided into fields corresponding to each node. Therefore, nodes other than node T1, that is, slave nodes, count the timing of these start codes to detect their own field and identify their own information channel.

A node that needs to communicate with the information processing device S first checks the connection code (described later) in the control channel field of the reception register RD, and if the connection code specifies an empty information channel, it uses the control channel of the transmission register SD. Record the calling code in the field and send it. If it's busy, I'll go to the waiting room.

The main station node T1 detects the received calling code in the control channel 2 field of the reception register RD. This detection is accomplished by detecting the start code and identifying the time slot or field that corresponds to each station. Therefore, the main station 〒1 selects an available information channel. If there is a free information channel, a connection code indicating the number of the information channel is recorded in the time slot of the detected node; if there is no free channel, a connection code indicating busy is recorded and transmitted. Communication between the information processing device S and its 7-board is performed using the information channel designated by this connection code.

As shown in FIG. 4, the information processing device S (FIG. 1)
It has a block TB having the same function as Tf shown in the figure. It is connected to registers SD and RD similar to those of FIG. 3 and has associated parts O9, PR, SR, PS, SO (FIG. 3), etc. These parts have the number of bits equal to the number of input/output channels CHO to CH3 of the information processing device S. In other words, the number of channels (
In this example, the number of bits is equal to 4) multiplied by the number of bits of one channel, and consists of digits corresponding to each input/output channel. In this embodiment, channel CHO is a control channel, and CII to CH3 are three information channels.

As shown in FIG. 4, the information processing device S includes processing devices such as a central processing unit CG, a common memory RES, a multiplexer MPX, and a common file F around a bus 400.
, a voice response file RE, and peripheral devices such as a clock generator RT for generating interrupts. There is no difference in the configuration of the information processing device S depending on its application, except for the content of the program executed by the central processing device CC.

The information processing device MS has three information channels CHI to CH3.
It is logically connected to the three information channels used by each node via. The central processing unit CG multi-processes tasks in response to messages sent from each node.

The common file F, which is one of the external storage devices, is a storage area for programs and data. In this embodiment, in particular, it is also used as an image information file, and this data may include an image signal. That is, in processing such as forming and exchanging materials, searching and recording information, etc.
Used for temporary storage, mail storage, facsimile files, etc. The voice response file RE is a storage device that records fragments of voice signals for voice responses to the terminal device.

The speed conversion device M is a speed conversion storage device that inputs/outputs a high bit rate signal such as an image signal to/from a file storage device F at high speed, and transmits/receives it to/from a node at a low speed.

This will be explained in more detail later.

By optimizing the arrangement of each block of the information processing device S and the functions of the interrupt processing program, these functions, related software, and the storage area of the work memory of the central processing unit CC can be effectively utilized.

In this embodiment, blocks and lines other than the central processing unit CC operate according to program instructions executed by the central processing unit CC, but these operations are performed by the central processing unit C.
It is done in parallel in each block without C's involvement. Only when this operation is completed, each block notifies the central processing unit CC of its completion by means of an interrupt signal.

The central processing unit has a work memory WM as shown in FIG. 5, and processes the operation results of each block and line using this memory area. Information transfer between this work memory area and each block of the information processing device S is performed by the input/output unit 0 of the central processing unit CC. Further, program instructions are executed by an instruction execution unit PU.

The instruction execution unit PU and the input/output unit (2) 0 each have their own entrance/exit to the bus 400. However, the work memory W M t-1 is shared. Explain how to share it.

The central processing unit CG has an address decoder AD, which decodes the signal on the address bus 400-1 and determines the time and input/output unit for allocating the work memory WM to the instruction execution unit PU.
This is to detect the time allocated to 0. The address signal from the instruction execution unit PU and the input/output unit 0 is gated by the output of the decoder 80 and is applied to the work memory WM as an address signal ADD. Work memory WMt* The data read from the storage location specified by the address signal ADD is output to the signal line R, and the write data is given to the signal line W from the instruction execution unit PU and the input/output unit IO, and is specified by the address signal AlIn. stored in the specified storage location.

Information transfer between each block of the information processing device S is performed via the common memory RES. Each block has a common memory R
The right to access the ESs is granted by supplying them with time-sharing time slots from the multiplexer MPX. The time slots for the central processing unit CG are allocated to the instruction execution unit PU and the input/output unit IO, respectively.
The work memory WM can be accessed in each time slot.

As shown in FIG. 6, the common memory RES includes a main memory section, that is, an internal memory MW, address registers R1 and R2,
It includes comparison circuits CI and C2, a mask change circuit MAS, and the like. In addition, in the same figure, double lines indicate multi-line signals,
- Double lines indicate multi-line signals, "11" indicates prohibited input,
Squares indicate mask signals.

An address bus AA is connected to the main memory section MM, and a partial address PA etc. are given thereto.

The address area of the common memory RES, that is, the main memory section M
The storage area is divided into a plurality of partial address areas 500 as shown in FIG. 7, and these partial address areas 500 are provided corresponding to each block in the information processing apparatus S, that is, each device. Each partial address area
500 has a partial address PA at a specific address location, which is a read address 502R and a write address 50
It consists of 2W. The read address 502R is the address pointer of the storage location from which the partial address area is read, and the write address 502III is the address pointer of the storage location from which the partial address area is written. This allows the partial address area 500
The addresses within are logically concatenated so that reading is performed cyclically in the order in which they were stored. Therefore, each time partial address PA is applied to the common memory, reading and writing are performed according to this cyclic concatenation order. A write address pointer 502W for the central processing unit CC is given to the input/output section (2)0, and a read address pointer 502R is assigned to the instruction execution section PU.

For example, as shown in the figure, the read address 502R points to the address n+ml from which the partial address area 500 is read, and the write address 502W points to the address n+m from which the partial address area 500 is written.
Pointing to 2.

By the way, the bus 400 of the information processing device S is occupied by each block in a time-sharing manner. This time-division time slot is allocated by changing the logical combination of each bit using the several-bit address line 400-1.

Bus 400-2 is an input to common memory RES, and is composed of the logical sum of output lines from each block.

Bus 400-3 is a parallel output line from common memory RES to each block. Bus 400-4 is common memory RES
9 Consists of logical sum. Buses 400-2 to 400-4 are gated only for the blocks addressed by bus 400-1, and characters are transferred between each block in the following manner.

In the time slot assigned to each block,
In the first half, the partial address P^ of the transfer destination block is designated and written, and in the second half, the partial address of the own block is designated and read. By specifying the partial address in this manner, it is possible to read from the partial address area 500 in the order in which it was written.

As shown in Figure 6, there are 3 time slots on the Kinomi flow side.
It is divided into phases φ1, φ2 and φ3. The address AA is gated into the main memory portion MW by the l-phase φ1 to designate a storage location. As a result, the read address 502R and the write address 5 of the partial address PA of the storage location are
02W is the segment of register R1) 430R and 4
30W, respectively. In the two-phase φ2, data is input/output from the input/output data terminals 0, 2 and 0 of the main memory section MM to the heel of the main memory section M. The signal line A determines whether to perform input/output to or from the main memory MM
Determined by the logic value applied to ct and AC2. If the signal line AC1 is energized, the write address is supplied from the register segment 430W to the address bus AA in phase φ2, and if the signal line AC2 is energized, the read address is supplied from the register segment 430R to the address bus AA in phase φ2. Depending on each case, data is gated from data line I to main memory section M or from main memory section M to data line O in phase φ2.

On the other hand, the read address and write address of register R1 are input to adders 432 and 434 in phase φ2 according to the activation and deactivation states of signal lines AC1 and AC2, respectively.
adds one, which is stored in corresponding segments 43EIR and 43BW of register R2. This addition is carried out modulo a predetermined number, but the modulus is changed depending on the partial address added to the mask circuit MAS. This is done by changing, or masking, the number of bits processed in adders 432 and 434. The mask circuit ^S converts a partial address into a mask signal.

In the three-phase φ3, the recording and reading addresses of the register R2 updated in this way are stored in the storage location in the main storage section M specified by the partial address PA.

By the way, when the read address 502R (FIG. 7) exceeds the write address 502W, there is no instruction to be read. When comparator C1 detects the read address segment 430R of register R1 and the write address pointer, it energizes output 440, outputs signal AC3 in phase φ2, and AND gate 442.
Prohibits the operation of As a result, the operation of storing data in segment 438H of register segment register R2 is prohibited.

To perform addition modulo a predetermined number as described above,
This means that storage locations in the partial address area 500 are always addressed in a circular manner. Therefore,
For example, if an instruction has been written to all memory locations contained in partial address area 500, then the contents of write address segment 430W of register R1 are equal to the contents of read address segment 43OR minus one. In this case, the partial address area 500
writing to must be prohibited. This subtraction is performed by the adder circuit 445, and the comparator circuit C2 compares the two, and when a match is detected, output 442 is activated. In response, AND gate 444 outputs signal AC4. Other circuits respond to signal AC4 to stop signal AC4. As a result, writing to that partial address area 500 is not performed.

By specifying the partial address in this manner, it is possible to read from the partial address area 500 in the order in which it was written.

The input/output section IO of the central processing unit CC is also regarded as one block, and when transferring between two blocks, the instruction execution section PU stores a control word specifying code transfer between both blocks in the main storage section RES. Write to the corresponding partial address PA. Each block reads this control word or instruction from the corresponding partial address PA in the time slot assigned to it and executes the corresponding operation.

When each block completes the operation specified by the control word, it accesses the partial address 500 corresponding to the instruction execution unit Pυ of the central processing unit CC and writes an interrupt signal there. Note that the interrupt signal is also written to its own partial address by the instruction execution unit PU when an interrupt request instruction is executed by the instruction execution unit PU.

The instruction execution unit PU of the central processing unit CG increments an instruction counter (not shown) therein and executes the instruction at the storage location of the work memory WM specified by the instruction counter. When the execution of the instruction is finished, just before incrementing the instruction counter, it specifies and reads its own partial address 500.

When the interrupt signal is read out by this, the instruction counter is jumped to the address where the interrupt processing program is stored in the work 4 memory WM, and interrupt processing is performed according to the contents of the interrupt signal. Note that while the interrupt process is being executed, reading from its own partial address 500 is not performed, but writing to it continues.

By providing sufficient storage locations in the partial address area 500 of the common memory RES corresponding to the instruction execution unit PU, interrupt processing can be performed reliably without loss of interrupt signals, and the interrupt processing program can be By providing an interrupt processing function, flexible multiprocessing becomes possible.

When a functional character is received from a terminal device, it is stored in the partial address area 500 of the common memory RES corresponding to the input/output section IO, and at the same time stored in the partial address area 500 of the common memory RES corresponding to the instruction execution section Pu.
Interrupt signals are accumulated in . As a result, transmission control can be performed on a character-by-character basis, and even if the frequency of interrupts increases, these interrupts will not be lost. Therefore, it is particularly advantageous when programming, etc., which involve frequent conversational communication, is performed using a remote terminal. however,
The instructions sent to the line must not be completed with an interrupt, but must be completed with an instruction issued later by the instruction execution unit PU, so that characters are not lost. Multi-processing is performed by an interrupt processing program, which manages a task table consisting of many items. A task corresponds to a channel in a time-division multiplex line, but instead of performing multiple processing by periodically assigning time slots as in the case of channels, tasks are performed by referring to items in a task table using an interrupt signal. That is, the interrupt processing program reads the interrupt signal, updates the associated task table item, and searches for a task table item that is not executing an input/output instruction.

This task table records the contents of the instruction counter of the program interrupted by an interrupt, and according to the priority of the items, the instruction counter of the interrupt processing program is changed to the instruction counter of the interrupted program, and control is controlled by that program. to move to. In this way, the interrupt processing program plays the role of effectively utilizing the time during input/output operations for other tasks.

In this embodiment, as shown in FIG. 6, an interrupt clock generation circuit RT is provided, which generates an interrupt clock at a predetermined period, for example, every 1 to 2 seconds. If there is no interrupt clock generation circuit RT, if control is transferred to another program as described above, it will not be possible to manage it unless an interrupt signal is detected. Since interrupts in this case are independent of task item priorities, tasks waiting for control may be ignored. To prevent such a situation, the interrupt clock generating circuit RT generates an interrupt signal at a predetermined period.

By the way, the speed conversion device M shown in FIG. 4 is a speed conversion device that inputs and outputs an image signal to a temporary storage file F at high speed, that is, a high bit rate, and transfers it to an image terminal at a low speed, that is, a low bit rate. be. The operating speed of an image terminal device, such as a facsimile terminal device, located at a remote node is much slower than that of the central processing unit CC. Therefore, if the file F and the central processing unit CC were to transfer image signals directly to and from such a slow terminal device, they would be tied to this transfer operation for a long time, which would interfere with the processing of other jobs. This will cause In this embodiment, this is prevented by the speed conversion device M.

The speed conversion device M is a storage device in which information is input and output in response to an external clock supplied from the outside. On the other hand, the image storage file F is a file storage device in which a clock signal unique to the file storage medium, ie, a medium clock, is output when information is read from it, and writing is performed in response to an external clock.

Although it is possible to substantially match the frequencies of the medium clock and the external clock, it is extremely difficult to synchronize the phases. In order to read accumulated information from a storage device having such a functional configuration, firstly, a buffer register BF (FIG. 8) is provided on the output side of the image storage file F, and the buffer register BF (FIG. 8) is read out in the order in which it is stored. Second, the information block or storage unit stored in the file F needs to have a recording format of a predetermined length or less.

In this way, a buffer register with a relatively small storage capacity can be used.

Referring to FIG. 8, the configuration of the output section and its control section of the file storage device F is shown, and the control section is a circuit that controls reading out the image information stored in the file storage medium in the order in which it was stored. .

The file storage device F has a storage medium FO that stores image information as an image pattern. That is, when used as an image storage, it is stored not as an information signal that encodes the meaning of the information, but as an information signal that encodes a mere superficial pattern of image information. Such an information signal can be e.g. transmitted from a node Ti (FIG. 1) and can also be e.g. transmitted from another node Tj (not shown).
It is intended to be transferred to

The image information is stored in the storage medium FO with a header label associated with each record, that is, each storage unit. The central processing unit CC identifies this header label when reading out the image information stored in the storage medium FO. Further, there may be a plurality of storage media FO as physical media, and the central processing unit CC can selectively designate a specific medium among them via the bus 400 to access a desired record. .

The read information output 600 of the storage medium FO is sent to the buffer BF.
, and its input/output signal lines 5oft and 808 to the bus 400-3. Also, storage medium FQ
is driven by bus 400-4. bus 40
When 0-4 is activated, the medium clock of storage medium FO is output from signal 11802, and stored information is read out to output 600 in synchronization with this. In addition, an interrecord cap (IRG) is connected to the signal line 604 from the storage medium FO.
A signal is output, which indicates the delimitation of the aforementioned read information blocks.

A write or read address for the buffer BF is supplied to an address line 810 of the buffer register or pattern buffer BF. The write address is generated by counting the accumulated information read clock 602 by one in register L1. Further, the read read address is generated by counting the external clock applied from the bus 400-2 by the register 2, that is, the clock generated based on the signal of the multiplexer MPX (FIG. 4).

The external clock supplied from this bus 400-2 and the medium clock E102 generated from the storage medium FO have substantially the same frequency, but are generally not synchronized in phase.

In this embodiment, this phase asynchronization is resolved as follows.

The write address from storage medium FO to buffer BF is
Registers L1 and L2 are set so that they are ahead of the read address from buffer BF to bus 400-3. This setting is performed by releasing the reset I of registers 1 and L2 and starting counting at different times, making the former earlier than the latter. For this purpose, IR
A delay circuit is inserted in the G signal signal line 604, and a delay is given to the IRG signal supplied to the register L2. As a result, the reset of the register L2 is released later than that of the register L1.

2 Also, in order to prevent the buffer BF from being accessed simultaneously from the two address registers L1 and L2,
A clock input 612 to the flip-flop is provided with a clock signal having a frequency several times higher, for example about five times or more, than the medium clock 802 provided to register L1 or the external clock provided from bus 400-2 to register L2. This will be explained in detail later.

Flip-flop K and two pulse selection circuits N
1 and N2 has a time slot for accessing the buffer BF from the write register Ll, and a time slot for accessing the buffer BF from the write register Ll,
This is for alternately distributing the time slot 7 for accessing the buffer BF from the register L2.

The flip-flop is a circuit that generates a clock on signal lines 814 and 81B to create two time slots that occur alternately in response to high-speed clock 612. The two pulse selection circuits N1 and N2 may have the same configuration as shown in FIG. This is four flip-flops F1
˜F4 and a high frequency first signal (signal line 614
Or it is input from 616. The second signal (signal!! 1801
Or bus 4 (input from 1 (1-2). Same figure (F)
) is a circuit that selects and outputs the former pulse that is included in the pulse width of one pulse and is not separated by the rising edge of the latter pulse ((D) in the same figure).

The operation of the pulse selection circuit old or N2 will be explained with reference to the time chart of FIG. Flip-flop Fl is set when both the first and second signals are in the ON state by AND gate 700. Flip-flop F2 connects inverter 702 and AND gate 7
It is set when the flip-flop Fl is in the set state by 04 and the first signal is turned off. Assuming that flip-flop F4 is in the reset state, flip-flop F3 is activated when A) III gate 706 sets flip-flop F2 and the first signal is turned ON again, i.e., when the second signal is turned ON. The 6-flip-flop F3, which is set when the second first signal is turned ON, is reset when the first signal is turned OFF thereafter. Once the flip-flop F3 is set, the flip-flop F4 is set, and the inverted set output of the flip-flop F4 is used as the AND gate 708.
Therefore, flip-flop F3 then switches flip-flop Fl in the OFF state of the second signal.

Holds its reset state until F2 and F4 are reset. Therefore, the desired signal (FIG. 10(D)) is sent from the flip-flop F3 to the signal line 818 or 820.
) is output.

Signal lines 61B and 6 are connected to pulse selection circuits Ml and N2.
The pulse of the first signal applied from the flip-flop K through 14 is of course 180° inverted in phase, so that the AND gate 6 at the output of registers L1 and F2
32 and 630. and buffer BF input/output 80
AND gates 83B and 834 located at 8 and 808, respectively, output the output pulse (10th
(D)) are alternately energized. Therefore, there is no conflict between writing and reading of buffer BF.

5 Similarly, when storing image signals from the image terminal device of node Ti (FIG. 1) to the file storage device F of the information processing device S, speed conversion is performed from a low speed signal to a high speed signal via the speed conversion device M. do. However, in this case, the internal clock of the file storage device F, ie, the media clock, is not used, but the operation is performed in synchronization with the external clock supplied from the bus 400, so a circuit as shown in FIG. 9 is not required.

In this way, the image signal input from the terminal device at a relatively low speed is converted to a high-speed signal and stored in an image file, and the image signal is read out from the image file at high speed and converted to a low-speed signal for the terminal device. Since the central processing unit CC and file storage device F of the information processing apparatus S are not occupied by the operation of individual low-speed image terminals, they can effectively perform other processing.

Incidentally, the operation of storing an image signal from an image terminal device such as a facsimile of node Ti to file storage device F is executed by a service program of central processing unit CC. The central processing unit CG uses the IRG signal obtained from the storage medium FO to separate records or storage units (inter-record gap).
is detected, and the free storage area is searched by checking the header label of the record. When a free space is detected, the image signal received from node Ti is stored therein.

Therefore, the service program of the central processing unit CC is
A task table is created and managed to manage tasks performed by users of terminal devices. As mentioned above, items corresponding to the user's tasks are created in this task table, and the status of task processing, such as the operation of the storage file F and the exchange of control signals with the terminal device user, is detailed for each step. recorded. Thereby, the central processing unit CC can control the service program and perform multiple processing for users of a large number of terminal devices, that is, tasks.

That is, MI control can be transferred from one task item to another and back again.

When the image signals received from node Ti for a certain task item are stored in the file storage device F and ready to be transferred, the service program lowers the processing priority of that task item and transfers the message, i.e., the destination of the image signal, to the destination of the image signal. Waits for another node Tj to become ready for reception.

Another mode of message transfer is to finish processing the task item when the storage of image signals from node Ti to the file storage device F is completed, and transfer the message to node Tj at the convenience of the user of destination node Tj. There is also a mode in which the record in the file storage device F is accessed and the image signal is received. Of course, in that case, a task item for the user of node Tj, ie, a task item for receiving records of file F, is created in the task table of that node.

In this way, the detailed record of the task table takes the form of a kind of finite automaton, and the communication control procedure is also a finite automaton. In other words, the latter is a state transition table that defines a finite number of states and events that cause transitions between them.

FIG. 11 shows the state transition from the establishment of the transmission link to the return to the reset state, and the central processing unit CC manages such state transition for each terminal device of the node.

States θ to 5 indicate states in conversational communication, and state 8
6 to 10 indicate the status of the missed communication format.

When a node is communicating, that is, in states 1 to 5, it transmits a code indicating that it is communicating at the time allocated to that node by the control channel formed by the control information section 104 of the transmission frame 102 (FIG. 2). Send.

As shown in FIG. 11, when communication is terminated or interrupted from the node side, the system is restored to the reset state WIAO. At this time, the communication display that was being transmitted on the control channel is stopped, and the communication control by the control node Tl (FIG. 1) is returned to the reset state. As a result, the communication display is no longer relayed to the information processing device S.

In state l, the node Ti calls the called node, ie, in this case the information processing device S, which is sent with a code, starting from the control channel, for origination. The control node T1 transmits the call code, the calling station name, and the name of one selected free information channel from the control channel to the information processing device S at the time assigned to it, and at the time assigned to the node Ti on the control channel. Also sends this availability information channel name. The calling node Ti receives the connection completion signal from the information processing device S through this channel and shifts to the transmission enabled state 2. Thereafter, the state transitions between states 83.4 and 5 according to the illustrated transition conditions.

When the terminal device is not used or when waiting to receive a message from the information processing device S, the terminal device shifts to the absence reset state 6 by turning on an absence key (not shown) on the terminal device. This is done by detecting the aforementioned connection code at the time allocated to that node by the control channel in the control information section 104 of the transmission frame 102.

In the absence reset state 6, when a call is received from another node or the information processing device S, the state changes to a state 7 in which an absence response is prepared. In state 7, a self-diagnosis is performed to determine whether the terminal device is ready for reception, such as automatic power-on and reception recording. Note that in reset state 0, in which the absent key is turned off, the device is powered on, and in that case, when an incoming call is detected from the control channel, the state changes to state 7.

As a result of the self-diagnosis, if reception is possible, the corresponding control code is transmitted and the state shifts to state 8. If reception is not possible, a corresponding control code is sent and the state returns to absence reset state 6. In the latter case, the central, for example, information processing device S (Fig. 1)
Then, lower the priority of the task and move on to processing other tasks. The central information processing device S monitors the time when a control response should be received from the node, and if a receivable signal is not received during this time, the same processing as if a control code indicating that the node is not receivable is received.

In state 8, the terminal device receives or waits for reception. If the received message block is good, a control code requesting the next block is sent and the process moves to waiting state 10; if it is bad, a control code requesting retransmission of the block is returned and the process moves to waiting state 9. In this embodiment, since there are two waiting states 9 and 10, it is possible to distinguish between errors in the signal itself requesting blow-off or retransmission. The central information processing device performs time monitoring after transmitting a message block and after transmitting an E) IQ code (to be described later), and monitors reception of a control code from the terminal to determine whether to broadcast or retransmit. If there is no response during this time, measures such as sending out the makeshift code ENQ on the control channel are taken.

When the terminal device receives the ENQ code, it retransmits or blows depending on whether it is in state 9 or 10. If block reception is started in states 9 and 10, the state shifts to reception state 8.

From each of these states, when the above-mentioned communication indicator code is stopped, the communication returns to the absent reset state 6 and ends the communication.

In terminal devices that are not commonly used, the power may be turned off when not in use. For example, in states 0 and 6, the power may be off. In a processing unit that operates only when the power is on, states other than state 2 are handled separately. For example, when the power is off, these states are distinguished depending on whether the absentee key is operated or not and whether the device is off-hook or not, and the power is turned on when a call arrives and the modem is switched to the modem side. This starts a timer which sets the state identification register to state 1 or 7 when it times out. This transitions to either the Out of Office response state 7 or the signal state I, depending on the state of the Out of Office key and telephone hook.

The terminal devices and the central information processing device S take the state transition shown in FIG. 11, but the central information processing device S manages the state by multiple processing corresponding to communication channels.

In other words, state management is performed not only for each communication channel, but also for each task. For example, in a system that allows multiple tasks to be performed on one communication terminal device, channels and tasks do not correspond one-to-one, and conditions are defined for each communication channel task rather than corresponding to communication channels. There must be. Therefore, state 3 in Figure 11 has two tables: a channel table that defines transitions for each channel, and a task table that defines each task.
That is, a status display is provided. Therefore the 11th
The state transition in the figure can be considered as the state transition of one task, and also the state transition of one channel.

For example, when one terminal device is used by two people, or when two different tasks are performed partially in parallel, two or more tasks may occur for one item in the channel table. be. For example, even if one task performs batch processing, another task may be performing conversational communication on the same terminal device. During this time, the batch processing will be completed and the results will be ready to be sent. In unimplemented embodiments, as soon as a task using a terminal device is completed, the batch processing results are transferred to that terminal.

This is managed by referring to the aforementioned channel table and task table in the central information processing device. Channel Tables and Task 4 Updating and saving of tables is performed by the operating system, which functions under the control of the interrupt handler previously described. This operating system includes a communication control program and other service programs. In the communication control program, each item in the channel table is
Control and processing are performed to satisfy the state transitions shown in the figure. Other functions of the operating system reference and process updates to both the channel table and the task table. More specifically, for example, when batch processing is completed for a certain batch processing task, the channel used by that item is identified in the task table, and the channel table is indexed to identify other channels that are using that channel. Know your tasks. If none of these tasks is currently using that terminal device, the tasks that have completed batch processing will access this terminal.

This allows the batch processing results to be sent to that terminal.

--1 According to the present invention, the status of one image terminal device is managed in a central information processing device, and absentee communication is also possible for image signal transfer. Furthermore, since this state management is performed not only for channels but also for tasks, an image communication system that not only allows absent communication but also has high flexibility and reliability in terminal use is realized.

As described above, according to the present invention, not only information encoded with meaning but also image information encoded with superficial patterns, such as facsimile information, is stored and managed in a central database, and can be accessed from a remote terminal device. It can be used and processed. For example, handwritten or printed materials and drawings can be stored in a central image file and shared by many terminals, for example, during missed communications. Therefore, ultimately, the image information stored in the central image file will be able to be used jointly by many image terminals, improving the efficiency of using image processing hardware and software, and improving the user's application. It can increase diversity.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a communication system that implements the absent communication method for image signals according to the present invention; FIG. 2 is a diagram showing an example of a format configuration of a transmission frame used in the communication system of FIG. 1; 3 is a block diagram showing a detailed configuration example of the node shown in FIG. 1, FIG. 4 is a block diagram showing a detailed configuration example of the central information processing device in FIG. 1, and FIG. 6 is a block diagram showing a specific example of the configuration of a common memory in an information processing device. FIG. 7 is a memory block diagram showing a part of a partial address area in the common memory. 8 is a block diagram showing the specific configuration of the information output section of the file storage device shown in FIG. 4; FIG. 9 is a block diagram showing the detailed configuration of the pulse selection circuit shown in FIG. 8; 7. FIG. 1O is a timing diagram used to explain the operation of the pulse selection circuit shown in FIG. 9, and FIG. 11 is a state transition diagram showing an example of channel and task state transition control. 1 CC, , Central processing units CHO to CH3, Channels F, , File storage device FO, , File storage medium In, , , Input/output unit M, , Speed conversion device M 900. Main storage unit PU, ,Instruction execution unit RES, ,Common memory S, ,Information processing device Ti, ,Node WM, ,Work memory 100, ,Communication information unit 102, , , ,Transmission frame 104, , ,Control information section 8 81 Figure 2 Figure μn, Figure 3 - Figure 5 Plan big 7 Figure 001. L.I.

Claims (1)

[Claims] 1. In an image signal absent communication system for transferring a transmission frame including an image signal between an information processing device having an input/output channel and a plurality of terminal devices, the transmission frame includes a plurality of fields. and the field is logically connected to the input/output channel, the plurality of terminal devices include an image terminal device capable of conversation communication and absent communication, and the information processing device is absent with respect to the image terminal device. An image characterized in that when performing communication, it is identified whether or not the image terminal device is in a state where absent communication is possible, and the image signal is transferred to the image terminal device by selectively occupying the field. Signal-absence communication method. 2. In the missed communication system according to claim 1, the information processing device has a first state indicating the state of the terminal device corresponding to the input/output channel. c) storing a display and a second status display indicating the status of each work performed on the terminal device, and the information processing device executes processing for each work with reference to the second status display; Identification of whether or not the image terminal device is in a state where missed communication is possible is performed in the first step.
An absent communication method for image signals, characterized in that the communication is performed by referring to the status display of the image signal.