JPS59153320A - Phase comparator - Google Patents

Abstract

PURPOSE:To obtain a suitable phase comparator for the tracking control of the CD system DAD reproducer especially with wide control band without adverse effect by noise by providing two detecting means and phase difference signal producing means. CONSTITUTION:Since phase difference signals U, D corresponding to the lag and lead of the phase of a detecting signal B to a tracking error detecting signal A are obtained respectively in this circuit, a tracking error control signal obtained by adding the phase difference signals U, D at an operational amplifier 32 via LPFs 30, 31 becomes a sawtooth wave and the control band is widened. Further, since the phase difference signals U, D are the comparison of areas in response to the phase lag and lead of the tracking error signals A, B substantially, even if pulsive noise is mixed at an optional time, almost no adverse effect is produced on the phase difference signals U, D, then the effect of noise is not received.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a CD (optical compact disc), for example.
The present invention relates to a phase comparator suitable for use in a tracking error control system of a digital audio disc (DAD) playback device.

[Technical background of the invention and its problems]

As is well known, as a phase comparator that compares the phases of two input pulse signals and outputs a phase difference signal corresponding to the phase difference component, an exclusive OR circuit (hereinafter referred to as A circuit using EX-OR circuit (EX-OR circuit) is known.

In other words, this is called the area comparison form,
When the input pulse signals shown in FIGS. 2(a) and 2(b) are supplied to the input terminals 12 and 13, the output terminals 14 output the input pulse signals as shown in FIG. 2(C). A phase difference signal that is at the H level is output only during the period when the signals are at different logic levels.

The phase difference signal is usually converted into a change in voltage level by a low-pass filter (not shown), and then supplied to a predetermined control system. Here, the voltage level (which corresponds to the phase comparison output) has triangular wave characteristics, as shown in FIG.

By the way, in the area comparison type phase comparator using the EX-OR circuit 11 as described above, even if a short-period pulse noise signal is mixed into the two input signals, x-'i4,
Although it has the advantage of not having a large influence on the phase difference signal 1f1w, it has the problem that the control band becomes narrow because the phase comparison output characteristic is triangular wave-like as shown in FIG.

Therefore, as shown in FIG.
A so-called edge detection type phase comparator using 15 to 18 pixels has been considered.

That is, this means that input terminal 19.20 has 81!5 figure (
a), fb) Input as shown in VC/9 pulse signal 1
1#I2 are respectively supplied, the human pulse signal 11
When the phase of I is delayed, a phase difference signal 01 as shown in FIG. 5(C) is output from the output terminal 21,
When the phase of input pulse signal ■2 is ahead of that of input pulse signal ■1V, the phase difference signal 0.2V as shown in FIG. is outputted from the output terminal 22.

Then, the phase difference signal 0. ．． 0. are each converted into a change in voltage level through a low-pass filter (not shown) or the like, and then the two voltage levels are added and supplied to a predetermined control system. Here, the added voltage level (which corresponds to the phase comparison output) has a sawtooth characteristic, as shown in FIG.

Therefore, in the edge detection type phase comparator, since its phase comparison characteristic is sawtooth-like as shown in FIG. 6, it can have a wider control band than the area comparison type. However, this edge detection type phase comparator, contrary to the area comparison type, uses two input signals I, , I
'.

When short-period pulse noise is mixed into the phase difference signal 01.0., the edge component of the noise is also detected and eliminated. There is a problem that does not represent the correct phase difference component.

[Technical background of the invention]

Incidentally, in recent years, in the field of Me devices, a digital recording and reproducing method using PCM (i+Russ code monolation) technology is being adopted in order to achieve high fidelity reproduction as much as possible. In other words, this is what is called digital audio conversion, and the audio characteristics are not dependent on the characteristics of the recording medium (VC), and are much superior to those using conventional analog recording and playback methods. This is because it is established in principle.

In this case, the system that uses a disk as the recording medium is called 1) AD system, and optical, electrostatic, and mechanical recording and reproducing methods have been proposed. However, no matter which method is adopted, the reproduction device that embodies it must be able to satisfy the control function and performance of the glaze system that is not found in conventional methods. requested.

In other words, if we take two examples of CD-based systems,
A transparent resin disk with a diameter of 12 [CnL] and a thickness of 12 Cmn' has bits (irregularities with different reflectances) corresponding to digital (1' CM) data wj@H'y.

A disk with a metal thin film coated with
The disk is driven to rotate at a variable rotational speed, and is reproduced in a linear tracking manner from the inner circumferential side to the outer circumferential side using an optical pickup containing a semiconductor radar and a photoelectric conversion element. 1,
The program area (radius 25 to
58 (FX”)), and their index data etc. are recorded in the lead-in area (radius 23~
25 [rlLm]), it can be easily learned.

By the way, in the above-mentioned CD-type DAD playback device (a), it is particularly important that the light beam irradiated from the above-mentioned pickup reads the bit string of the disk in order to clearly read out the digitalized data recorded on the disc. The objective is to perform tracking control (tracking servo) so that the bit string is accurately traced without deviation from the bit line, that is, without causing a tracking error.

FIG. 7 shows such conventional tracking error control means. In other words, 23 in the figure is a disk,
It is rotated by a disk motor (not shown) at the aforementioned variable rotational speed. A pickup 24 is installed at the bottom of this disk 23 in FIG.

The pick-up 24 is moved in the radial direction of the disk 23 by a pickup feed motor (not shown). In addition, the pickup 24
is the objective lens 24a.

It comprises a beam splitter 24b, a semiconductor laser 24C2, a photoelectric conversion element (hereinafter referred to as photodetector) 24d, and an actuator 24e for moving the objective lens 24ak in the radial direction of the disk 23.

First, when the original beam is emitted from the semiconductor radar 24c, the light beam is focused (spot) on the signal recording surface of the disk 23 via the beam sinter 24b and the objective lens 24a. Then, the light beam is changed and reflected by the disk 230 bit, travels backwards to the objective lens 24af, is reflected at right angles by the beam sinter 24b, and is received by the photodetector 24d.

Here, the photodetector 24d has a so-called four-division configuration in which four photodiodes PDa to PDdi are arranged symmetrically, and when the reflected light from the disk 23 is received, the four photodiodes PD
a to P I) d output signals fa) to (d) (having frequency components), respectively. This signal (,
) to (d) are supplied to the matrix circuit 25, and (
a-1-b+c+d), (a0d), (b0C
), (a-l-C), and (b+d). Of these, the signal at (a + C + d) 7' is converted into an RF multiplied signal and guided to a demodulation/reproduction system (not shown) via the output terminal 26 for demodulation/reproduction processing. Further, two signals (a+d) and (b+C) are guided as focus error detection signals to a focus servo system (not shown) through output terminals 27 and 28'f;i, and are used for focus error control.

The two signals (a+c) and (b+d) are then supplied to the phase comparator 29 as tracking error detection signals. When the signals shown in FIGS. 8(a) and 8(b) are supplied to the two input terminals of this phase comparator 17, the phase comparator 17 (see FIG. 8) corresponding to the phase lead and lag of both signals, C), two phase difference signals hT as shown in (d)
, DJ7 generates and outputs it, which is basically the error/zo detection type shown in FIG. That is, in the case of FIG. 7, there are two phase signals U corresponding to the phase lead and lag of the two signals (a+c) and (b+d).

D is what is output. Then, this phase difference signal U
, D are signals corresponding to the spot being shifted in the forward and reverse directions from the bit string, respectively.In other words, the phase comparator 29 is (a+C)-(b+d).
This means that a signal is generated.

Here, the phase difference signals U and D are filtered by the low-pass filter 3.
0.31, the operational amplifier 32 causes the voltage level corresponding to the phase difference signal U to have positive polarity, and the voltage level corresponding to the phase difference signal U to have negative polarity. Output. The output of this operational amplifier 32 becomes a tracking error control signal, and the tracking error control signal is supplied to the actuator 24e of the Ail pickup 24 via the phase compensation circuit 33 and the amplifier circuit 34. The objective lens 24B is moved so that the spot is accurately positioned on the bit string, and the tracking error is corrected (j).

That is, the tracking error control signal has a substantially sawtooth waveform as shown in FIG. and,
When the spot of the light beam is accurately positioned on the bit string NVC on the disk 23, that is, when there is no tracking error, the tracking error control signal is at O level. . The tracking error control signal also includes a bit string (N
+1) direction, the voltage level becomes positive, and the spot moves towards the bit string NO adjacent to the inner circumference of the bit string NO.
-1), the voltage level becomes negative polarity. Furthermore, the absolute magnitude of the voltage level of the tracking error control signal ω is determined by the bit string N of the spot.
This corresponds to the amount of deviation from . For this reason,
so that the spot is always located on the bit string N, that is, so that the tracking error control signal is at O level.
The objective lens 24a is moved and tracking error control is performed.

The phase comparator 29 used in the above-mentioned tracking error control means uses an error/zo detection type as described above due to the necessity of widening its control band. As mentioned above, if the phase difference signals U and D are mixed with noise in the tracking error detection signals (a+c) and (b+d), they will be affected by the edge components of the noise, so it will eventually become impossible to perform correct tracking error control. There is a problem.

[Purpose of the invention]

This invention has been made in consideration of the above-mentioned circumstances, and is extremely effective, making it possible to widen the control band, and also being particularly suitable for use in tracking error control of CD-based DAD playback devices, which can also cause adverse effects due to noise. The purpose of this invention is to provide a phase comparator.

[Summary of the invention]

That is, the present invention provides a first input signal and a second input signal having alternately first and second logic levels, respectively.
In the phase comparator, the phase comparator compares the phases of the first and second input pulse signals with an input pulse signal and generates an output corresponding to the phase difference between the first and second input pulse signals. a first detection means for detecting that the first and second input pulse signals have both reached a second logic level;
State holding means that is brought into a first state by being supplied with a detection output signal from the first detection means and brought into a second state by being supplied with a detection output signal from the second detection means. and when the state holding means is set to the first state with the first and second input pulse signals at first and second logic levels, respectively, and the first and second input pulses The signals are the second and first respectively.
a first phase difference signal generation means that generates a first phase difference signal when the state holding means enters a second state with the logic level of 11JiiI2 first and second input pulse signals; are at the second and first logic levels, respectively, and the state holding means is set to the first state, and the first and second input pulse signals are at the first and second logic levels, respectively. The present invention is characterized by comprising second phase difference signal generation means that generates a second phase difference signal when the state holding means is brought into a second state in a state where .

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention applied to tracking error control of a 7CD type DAD reproducing apparatus will be described in detail with reference to the drawings.

In FIG. 10, the same parts as in FIG. 7 are indicated by the same symbols, and only the different parts will be explained here.

That is, 35° and 36 in FIG. 10 are input terminals to which the tracking error detection signals (a+c) and (b+d) output from the matrix circuit 25 are respectively supplied. Among these, the input terminal 35 is connected to the AND circuit 37
is connected to one input end of the knot circuit 38.
It is connected to one input terminal of the AND circuit 39 via. Further, the input terminal 35 is connected to the first input terminal of the AND circuit 40.
is connected to the input terminal of the AND circuit 41, and the second
is connected to the input end of the Furthermore, the above knot circuit 3
The output terminal of 8 is connected to the second input terminal of the AND circuit 42 and the first input terminal of the AND circuit 43.

On the other hand, the input ψ; Further, the input terminal 36 is connected to the first input terminal of the AND circuit 42, and the input terminal 36 is connected to the first input terminal of the AND circuit 42.
3 is connected to the second input terminal of 3. Further, the output terminal of the NOT circuit 44 is connected to the second input terminal of the AND circuit 40 and the third input terminal of the AND circuit 41.
is connected to the input end of the

Here, the output terminals of the AND circuits 37 and J9 are connected to chattering prevention circuits 45 and 46, respectively.
They are respectively connected to a set input terminal S and a reset input terminal R of a set-reset flip-flop circuit (hereinafter referred to as 8RFF circuit). And this SHF F circuit 47
The output terminal Qrri of is connected to the third input terminal of the AND circuit 42 and the first input terminal Kg of the AND circuit 41. In addition, the S RFP circuit 47
The inverting input terminal Q of the above-mentioned AND circuit 40.
are connected to the input terminals of each.

The output terminals of the AND circuits 40 and 42 are connected to both input terminals of the OR circuit 48, respectively. Also,
Each output terminal of the AND circuits 41 and 43 is connected to the OR circuit 4.
90 are connected to both input terminals, respectively. The output terminal of the OR circuit 48 is connected to the non-inverting input terminal (+) of the operational amplifier 32 via the connection terminal 50 and the low-pass filter 3012f made up of a resistor R1 and a capacitor C. There is. Further, the output end of the OR circuit 49 is connected to the inverting input end (-) of the operational amplifier 32 via the connection terminal 51 and the low-pass filter 31 made up of a resistor R and a capacitor C1. . The output end of this amplifier 32 is connected to the input end of the phase compensation circuit 33 via a connection terminal 52.

The operation of the above configuration will be explained below with reference to the timing diagram shown in FIG. 11. However, the 11th
Figures (a) and (b) show tracking error detection signals (a+c) and (
b + d), FIG. 11(c) shows the output signal of the output terminal Q of the 8RFP circuit 47, and FIG. 11(d) e (e
) indicate the output signals of the OR circuits 48 and 49, respectively. Here, the tracking error detection signals (a + C) and (b + d) supplied to the input terminals 35 and 36 are respectively denoted as +8), and when (A) is at H level, it is simply written as (A), (When (roll) is at L level, it will be written as w(A), and when (B) is at H level, it will be written simply as FB), and when (B) is at L level, it will be written as w (B). Then, the above AND times′#! r37 outputs an H level when input/B, and outputs an H level when the AND circuit 39-B is input. Further, the conditions for the output ends of the AND circuits 42, 40, 41, 43 to become H level are as shown in the following table.

With the above in mind, the operation will be explained below. First, as shown at time T1 in FIG. Since the output is applied to the reset input terminal R of the 5RFF circuit 47 via the chattering prevention circuit 46, the inverted output terminal Q of the 5RFFN circuit 47 is set at H level.

In this state, time T! When the tracking error detection signal input reaches level 1 with chattering, it ends up at -B, so the output of the AND circuit 40 becomes level 1 with chattering, and the output terminal of the OR circuit 48 has the level 1, as shown in FIG. A phase difference signal U as shown in (d) is output.

Then, at time T3, the tracking error detection signal B
When it becomes H level with chattering, it becomes -B, so the output terminal of the AND circuit 37 becomes H level with chattering, and the phase difference signal U
is made to the level. Then, the H level output of the AND circuit 37 is delayed by a predetermined period of time until it becomes stable by the chattering prevention circuit 45, and is output to the 5RFFl path 4 at time l114.
7, its output terminal Q is inverted to I (level). In this state, at time T,
When the tracking error detection signal A becomes L level with chattering, it eventually becomes -B, so the output of the AND circuit 42 becomes H level with chattering, and the phase difference signal U is output.

Then, at time T6, when the tracking error detection signal B goes to the L level with chattering, the output terminal of the AND circuit 39 goes to the I (level) with chattering, and the phase difference signal U is set to the L level.Then, the H level output of the AND circuit 39 is delayed by a predetermined period of time until stabilized by the chattering prevention circuit 46, and is supplied to the reset input terminal R of the 5RFF circuit 47 at time T7, so that its output End Q is L
be flipped to the level.

As is clear from the above explanation, the phase difference signal U is a signal corresponding to the phase delay when B lags with respect to the input of the tracking error detection signal. This corresponds to the spot being shifted in the positive direction from the bit string. Therefore, the phase difference signal U is output even during the period shown from time T to T in FIG.

On the other hand, at time T in FIG. As shown in , if the tracking error detection signals (A and B are both at H level), the I level output of the A/D circuit 37 is sent to the set input terminal S of the 5RFF circuit 470 via the chattering prevention circuit 45. As a result, the output terminal Q of the 5RFF circuit 47 is set to the H level.In this state, the tracking error detection signal B is output at time T+1.
When it goes to L level with chattering, it ends up being a person/stone, so the output of AND circuit 41 goes to H level with chattering, and the output terminal of OR circuit 49 has a voltage as shown in FIG. 11(e). A phase difference signal is output.

Then, at time Ill, when the tracking error detection signal becomes L level with chattering, it becomes -B, so the output terminal of the AND circuit 39 becomes H level with chattering, and the phase difference signal is set to L level. Then, the H level output of the AND circuit 39 is delayed by the chattering prevention circuit 46 for a predetermined period of time until it becomes stable, and reaches time T1. Since the signal is supplied to the reset input terminal R of the S RPF circuit 47, it is inverted to the output terminal QViL level. In this state, when the tracking error detection signal B becomes H level with chattering at time TI4, it ends up being -B, so the output of the AND circuit 43 becomes I (level) with chattering, and the phase difference signal B becomes H level. ■) is output.

Then, at time TI, the tracking error detection signal A
When it becomes I (level) with chattering, it becomes -B, so the output terminal of the AND circuit 37 becomes H level with chattering, and the phase difference signal becomes L level.
done to the level. Then, the H level output of the AND circuit 37 is delayed by a predetermined period of time until stabilized by the chattering prevention circuit 45, and is output to the 8RFF1m path 47 at time T1°.
is supplied to the set input terminal S of , so its output terminal Q is H
be flipped to the level.

As is clear from the above explanation, the phase difference nfi number is
When B is ahead of the tracking error detection signal A, this signal corresponds to the phase advance, and on the disk 23, this corresponds to the spot being shifted in the opposite direction from the bit string. It is.

Therefore, according to the configuration of the above embodiment, it is possible to obtain phase difference signals U and Di corresponding to the delay and lead of the phase of B with respect to the tracking error detection signal N, so that these phase difference signals U and Dli Operational amplifier 3 via the low-pass filters 30 and 311, respectively.
The tracking error control signal obtained by adding up the first
As shown in Fig. 2, it has a sawtooth shape, and the control band can be wider than that of the conventional area comparison type phase comparator. Also,
The phase difference signals U and D are tracking error detection signals A,
Since the area is substantially compared according to the phase delay and lead of Bi, for example, the tracking error detection signal A
(at an arbitrary time Ta in Fig. 11) (even if rusty noise is mixed in, it has almost no negative effect on the phase difference signals U and D, and is better than a conventional edge detection type phase comparator). It also becomes less susceptible to the effects of noise.

Furthermore, the signals supplied to the set input terminal S and the reset input terminal Rtic of the S RF F circuit 470 have their unstable regions cut by the chattering prevention circuits 45 and 46, so that the state of the S RF F circuit 47 is unnecessarily changed. In this respect, a stable phase comparison operation can be performed without being reversed. Regarding this point, even if [)f noise occurs in the tracking error detection signals A and B at the same time, this noise component will be cut by the chattering prevention circuits 45 and 46, so the m th operation will still be affected. This is something that can be prevented.

It should be noted that the present invention is not limited to the above-mentioned embodiment, and can be implemented with various modifications without departing from the gist of the invention.

〔Effect of the invention〕

Therefore, as detailed above, according to the present invention, it is possible to widen the control band, and it is particularly suitable for use in tracking error control of a CI) type DAD playback device, which may be affected by noise. An extremely good phase comparator can be provided.

[Brief explanation of drawings]

Figure 1 is a configuration diagram showing a conventional phase comparator, and Figure 2 is a diagram showing the configuration of a conventional phase comparator.
3 is a characteristic diagram of the phase comparator shown in FIG. 1, FIG. 4 is a block diagram showing another conventional phase comparator, and FIG. 5 is a timing diagram showing the operation of the phase comparator shown in FIG. Is the operation of the phase comparator shown in Figure 4? 6 is a characteristic diagram of the phase comparator shown in FIG. 4, FIG. 7 is a block diagram showing the tracking error control system of a D playback device based on the CD method, and FIG. 8 is a tracking error control diagram of the same. 9 is a characteristic diagram of the tracking error control signal, FIG. 10 is a block diagram showing an embodiment of the phase comparator according to the present invention, and FIG. 11 is a timing diagram showing the operation of the phase comparator of the system. Timing diagram for explaining the operation of the embodiment, No. 12
The figure is a characteristic diagram showing the phase comparison characteristics of the same example. 1 No... EX OR circuit, 12.13... Input terminal,
14... Output terminal, 15 to 18... DFF circuit,
19.20...Input terminal, 21.22...Output terminal, 23...Disc, 24...Pickup, 25
... Matrix circuit, 26 to 28 ... Output terminal,
29... Phase comparator, 30. 31... Low/f filter, 32... Operational amplifier, 33... Compensation circuit, 34... Amplification circuit, 35, ? 6... Input terminal, 37... AND circuit, 38... NOT circuit, 39 to 43... AND circuit, 44... NOT circuit, 45r46... chattering prevention circuit, 47...
・8 RIi' F circuit, 48.49...OR circuit,
50 to 52... Connection terminals. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 4 Figure 4 Figure 5 (b)

Claims (1)

[Claims] A first input pulse signal and a second input pulse signal each having a first and second logic level alternately are compared in phase, and an output corresponding to the phase difference between the first and second input pulse signals. a phase comparator that generates a signal, a first detection means for detecting that both the first and second input pulse signals have reached a first logic level; A second detection means detects that both have reached the second logic level, and a detection output signal from the first detection means is supplied, thereby entering the first state. a state holding means that enters a second state when the detection output signal is supplied; and state holding means that maintains the state when the first and second input pulse signals are at first and second logic levels, respectively. when the means is in the first state and when the state holding means is in the second state with the first and second input pulse signals at second and first logic levels, respectively; a first phase difference signal generation means that generates a phase difference signal of 1; and a state holding means that generates a first and when the state holding means is brought into the second state with the first and second input pulse signals at the first and second logic levels, respectively. A phase comparator comprising second phase difference signal generation means for generating a phase difference signal.