JPS59151453A - Semiconductor device - Google Patents

Abstract

PURPOSE:To operate the semiconductor stably, and to miniaturize a cell by forming a region combining a source in a transistor for writing and a gate electrode in a transistor for reading. CONSTITUTION:Gate insulating films 53a, 53b are formed in a cell region in a P type semiconductor substrate 51, and a gate electrode 54 in a first transistor TR exclusive for writing and a semiconductor layer 55 as source-drain in a second TR are formed. An inversion layer 58 is formed on the surface of the substrate 51 under the film 53b so as to be opposed to the layer 55. A drain 56 and a source 57 in the first TR are formed to the substrate 51 while using the electrode 54 and the layer 55 as masks. Impurity regions 55a, 55b are formed at both end sections of the layer 55. The drain 56 is connected to a writing bit wire WB, and the region 55a is connected to a reading bit wire RB. The layer 55 is a section functioning as an element region in the second TR, the regions 55a, 55b each serve as a source and a drain, and the layer 58 functions as a gate electrode. According to the constitution, an element isolation region is unnecessitated, and operation is also stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device used as a dynamic memory cell.

[Technical background of the invention Problems with Tochi]

Conventionally, as a memory cell of an MO8fi dynamic memory, an MO8 type field effect transistor 1 is installed at the intersection of a bit line 12 and a "7-)' line I!: as shown in FIG.
3 and a cell in which a capacitor 14 is connected are often used. i1 capacitor 14 in a memory cell such as
Information is stored depending on the presence or absence of an electric field stored in the □. In other words, the state where the capacitor 14 is charged is the state @l'
#, the state where there is no charge in the capacitor 14 is the state "O" left □ru1' To write information to the memory cell, the word line 1z
A specific potential is applied to the MO8 type field effect transistor 3 to make it conductive, and the potential of the bit line 12 is applied to one electrode of the capacitor 14 to make the MO8' type field effect transistor 13 to be cut off. . .

On the other hand, when reading information from this memory cell, the bit line 1B is set to a known potential (for example, ground potential), the MO8 field effect transistor 13 is made conductive, and then the potential of the bit line 12 is changed. - is detected to determine the accumulation of charge in the canopy sensor 14.

In such a memory cell, the stray capacitance 9B of the bit line 12 is larger than the capacitance CBK of the capacitor 14, and CB/c8 is about 10 to 20. Because of that,
Even if the information writing voltage is on the order of several volts, the signal amount on the bit line I2 when reading information is at most several hundred meters.
However, in order to detect this difference, a highly sensitive sense amplifier is required, and the operation of the memory is weak against noise and is cine-stable.

Furthermore, as the degree of integration of the memory increases, CB/cs also increases, which further reduces the signal amount on the bit line 1z.

As a solution to the above problems, a cell using two MOS transistors (hereinafter simply referred to as transistors) as shown in FIG. 2 is known. In particular, 21 is a write word line, 22 is a read word line, 23 is a write bit line, 24 is a read bit line, 25 is a first transistor for writing only, 26 is a second transistor for reading only, 27 is a main transistor. is the stray capacitance consisting of the capacitance between the f-) electrode of the second transistor and the semiconductor substrate,
ζ Accumulates charge and stores information.

In this type of cell, a read-only transistor 26, a read word #1122 serving as the source and drain, and a read bit line 24 are added to the cell shown in FIG. Similar to the cell shown in FIG. 1, the first transistor 26 is made conductive;
The potential of the write bit line 23 is applied to one electrode of the floating capacitor Jffk 27, the first transistor 25 is turned off, and charge is stored in the floating capacitor 27.

On the other hand, information is read depending on whether or not the second transistor 26 is conductive. That is, stray capacitance 2
Since the dirt potential of the transistor 26 changes depending on whether there is a charge on the transistor 7, the conductance between the source and drain of the second transistor 26 changes, and this change is read out as information.

Here, in the memory cell of FIG. 1, when reading information, the charge stored in the capacitor 14 escapes to the stray capacitance C connected to the bit line 11, and the stored content is erased (destroyed). In the memory cell of FIG. 2, the stored contents are not destroyed even when read, so the memory cell of the method shown in FIG. 2 is called a non-destructive readable memory cell. Further, since the charge of the capacitor 21 is not changed during reading, a signal with sufficient amplitude can be obtained even when the bit line capacitance is large, stable operation is possible, and the sense amplifier can be simplified.

5- FIG. 3 shows an example in which the memory cell of FIG. 2 is realized on a semiconductor substrate. In the figure, a dirt electrode 32 of a first transistor, that is, a write word and a write line, is formed on a semiconductor substrate 31 via a gate insulating film 30 made of a silicon oxide film, and a drain 33 is provided on an insulating film 30m. It is connected to a write-in line 35 via a contact hole 34a. In addition, the source 36 is connected to the dirt electrode ssK of the second transistor through the contact holes 34b, 34e and the aluminum wiring 31, and the electrostatic charge between the dirt electrode 38 and the semiconductor substrate 31 is reduced. The capacitance becomes a floating capacitance (27 in FIG. 2) that stores write information. The drain 3 of this second transistor
9 is connected to the read bit line 40 through a contact hole j (d), and the source 41 itself becomes a read word line. Note that the first and second transistors in the cell are separated by an element isolation layer made of a thick oxide film. separated by a region 42,
The cells are separated by an element 6-isolation region 43 having an anti-inversion layer 43a formed thereunder. Further, in the figure, details of insulating films such as an interlayer insulating film made of, for example, an oxide film or a PSG film (phosphosilicate glass film 4) on the semiconductor substrate 3 are omitted.

As described above, in the above memory cell, the stored contents can be read out non-destructively, and even if the capacitor section for holding the stored contents is relatively small, it can be operated stably. However, this memory cell includes two transistors, and requires diffusion regions to serve as the source and drain regions of each transistor, as well as an element isolation region 42 to isolate these transistors. There was a drawback that the planar area of each cell was large.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned idea, and its purpose is to provide a semiconductor device that is capable of non-destructive/destructive readout, operates stably, and has a structure with a small area per cell. This is intended to contribute to higher integration of devices.

[Summary of the invention]

That is, the outline of the semiconductor device according to the present invention is as follows. In other words, there is a write-only first memory on the semiconductor substrate.
A dirt electrode (write word line) of the transistor is formed, and a first region (write pit line) and a second region which become the drain and source are formed. This second
The region may be a region of the semiconductor substrate, an impurity diffusion region of the opposite conductivity type, an inversion layer, or a combination thereof, as long as it is a region in a hagiform state in which carriers of the conductivity type opposite to that of the semiconductor substrate can exist. Subsequently, a semiconductor layer is formed on at least a portion of the second □ region with a y-t insulating film interposed therebetween. Then, a first impurity region and a second impurity region are respectively formed in separated parts of this semiconductor layer, and the first and second impurity regions are used as a source and a drain, and a second impurity region is formed opposite to the dirt insulating film. A second read-only transistor is formed in which the region serves as an r-to electrode. In a device having such a structure, the space between the second region and the semiconductor layer formed above the second region is used as a capacitive portion in which information is held, and first, the information is stored through the first transistor. Then, a charge corresponding to the information is supplied to the second region, and the first impurity region (read pit line) is turned on.

□ [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. In FIG. 4, a P-type semiconductor substrate 51 having a resistivity of, for example, 5 Ω, has a film thickness of, for example, 400 Ω in a cell region separated by an element isolation region 52′ provided under the inversion prevention layer sx*f′. 1 dirt insulating films 53m and 53b are formed,
and f-) Semiconductor layers 55, which will become sources and drains for writing, are formed using, for example, a polycrystalline silicon layer, in separate parts of the insulating films 53* and 53b. The 9-1st ff-) electrode 54 becomes a write word line WW.

Also, the above? -) The surface of the semiconductor substrate 51 under the insulating film ssb is lightly ion-implanted with an impurity of conductivity type opposite to that of the plate 51 such as phosphorus or arsenic, and the inversion layer 58 faces the upper conductor layer 55. It is formed to do so.

Next, using the first dirt electrode 54 and the semiconductor layer 55 as a mask, a cell alignment ('self-alignment) technique is used to diffuse, for example, arsenic into the semiconductor substrate 5 in an electrically conductive manner opposite to that of the substrate 51. □ drain 56 of the first transistor,
A source 51 is formed. The source 57 is connected to the inversion layer 5'8, and can be regarded as an integral region where carriers of the opposite type to the substrate 51, that is, electrons, participate in nuclear conduction. □ Next, in order to improve the electrical characteristics of the semiconductor layer 55, an annealing process using electron beam or radar beam irradiation is performed to convert the semiconductor layer 55 into a single crystal silicon. Semiconductor □ layer 58 consisting of
n10- type impurities such as arsenic are selectively introduced into both ends of the first impurity region 55a1.
A second impurity region 55b is formed.

The second impurity region 55b itself becomes a read word line RW.

Subsequently, after forming a glabellar insulating film 53e made of silicon oxide or phosphorus glass as appropriate, contact holes 59 are formed.
The drain 56 of the first transistor is connected to the write-in line WB via &, and the first
The impurity region 55m is also connected to the read pit line RB via the contact hole 59b. Note that, also in FIG. 4, detailed relationships between insulating films such as an interlayer insulating film formed on the semiconductor substrate 51 are omitted.

Here, the semiconductor layer 55 is a portion that becomes the element region of the read-only second transistor, and the first impurity region 55
The a and second impurity regions ssb serve as the source and drain, respectively, and the inversion layer 58 under the semiconductor layer 55 serves as the r- and to-electrodes.

Next, the operation of such a cell will be explained.

First, in order to write information into a cell, the write pit line WB is fixed to, for example, Ov or 5V depending on the information ro J and r I J. Next, the potential of the first r-) electrode 54, which is the e-) electrode of the first transistor and also serves as the write word line WW, is set to, for example, 7V to make the first transistor conductive.

Then, the potential of the write pit line wn is transmitted to the source 57 of the first transistor, and the inversion layer 58 connected to this source 57 also has the same potential. After this, if the transistor in the tube 1 is turned off, the semiconductor layer 55 and the inversion layer 58
In the inversion layer 58 of the capacitive part formed between the write pins 1iWB and 1iWB, a charge corresponding to the potential of the write pin 1iWB is stored, and information is stored.

On the other hand, when reading, the read pit line R
It is sufficient to check the electrical resistance between B and the read word line RW. For example, if the potential of the inversion layer 58 is 5V, the second transistor will not be in a conductive state; conversely, if the potential of the inversion layer 58 is Ov, the second transistor will be in a non-conducting state. . During this readout operation, the charges stored in the inversion layer 58 are not changed, so that so-called non-destructive readout is possible, and the readout operation is also stable.

Next, the area occupied by the cell shown in FIG. 4 will be described.

As is clear from comparison with the conventional cross-sectional view and cross-sectional view of FIG. 3, the device shown in FIG. 4 first requires an element isolation region to separate the first transistor and the second transistor. However, the size of the cell can be reduced accordingly. Further, in the conventional device, the stray capacitance between the f-) electrode 38 of the second transistor and the semiconductor body 5 substrate 31 was used as the main capacitance portion for storing information. How to ensure more stable and stable operation for this? -) Electrode 38. The area had to be made quite large. On the other hand, the cell shown in FIG. 4 includes the source and drain portions of the second transistor.
4 facing the inversion layer 58. Since one portion of the entire semiconductor layer 55 is used as a capacitance section, under the same design conditions, the cell 13 in FIG. 4 can have a larger capacitance section area.

In addition, in this example, the cell area required to obtain approximately the same cell capacity is reduced to approximately IA to 1/2.5 compared to the conventional cell area shown in FIG. It is possible to realize a significant increase in memory integration.

Next, FIG. 5 shows a modification of the cell shown in FIG. 4 above.

In the cell shown in FIG. 5, the inversion prevention layer 52m containing boron is
The inversion layer 58 is formed by, for example, ion implantation into a part of the cell region separated by the element isolation region 52 formed in the lower layer.
form.

Then, a dirt insulating film 53 is formed on the semiconductor backing plate 51, and the dirt insulating film 53 is formed on the insulating film 53 in the region adjacent to the inversion layer 58. -) Form a first goo electrode 54 to become a write word line WW on the insulating film 5.3. Then, an n-type impurity is diffused into a region on the opposite side of the inversion layer 58 with the first goo electrode 54 interposed therebetween, thereby forming a doin 56. Furthermore, what is on the inversion layer 58? -) Semiconductor layer 55 via insulating film 53
form. This semiconductor layer 55 is formed so that a portion of the region 14 overlaps the first dirt electrode 54 which becomes the dirt of the first transistor via a somewhat thick interlayer insulating film 53e, and both ends of this semiconductor layer 55 are In the region, there are first and second transistors that become the source and drain of the second transistor.
The impurity layers 55m and 55b are formed by introducing phosphorus or arsenic, for example. Then, the write pit line WB made of, for example, aluminum is connected to the drain 56 through a contact hole 59m formed in the glabella insulating film, and similarly, the first impurity region 55h of the semiconductor layer 55 and the read bit are connected through the contact hole 59b. Connect with line RB.

In such a cell, the source 57 of the first transistor and the dirt electrode of the second transistor in the cell shown in FIG. 4 are shared by the inversion layer 58. In order to further reduce the size of the second impurity region 55b which becomes the read word line RW of the semiconductor layer 55,
This is formed on the dirt electrode i54 of the first transistor.

As another modification, as shown in FIG.
The semiconductor layer 55 may be formed so that the entire semiconductor layer 55 is placed on top of the semiconductor layer 55 .

In addition, an inversion layer 58 (a portion that becomes a second region) that also serves as the source of the first transistor for writing and the second transistor for reading It can be replaced with a diffusion region into which conductive type impurities are introduced.

'Furthermore, the manufacturing steps in the description of the embodiments in FIGS. 4 and 5 are not limited to those described above, and the memory cells shown in FIGS. 4 and 5 can be formed even if the order is changed as appropriate. The method for introducing impurities may be a thermal diffusion method, an ion implantation method, or the like, selected and combined as appropriate.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, a carrier of a conductivity type opposite to that of the substrate exists as a region that serves as the source of the first transistor for writing and the r-to electrode of the second transistor for reading. By forming a possible region (second region) on a semiconductor substrate, and forming a semiconductor layer having first and second impurity regions on this second region with a dirt insulating film interposed therebetween. (2) There is no need for an element isolation region to separate the write transistor and read transistor, which were required in conventional non-destructive readout memory cells, (2) It is also possible to increase the ff-) capacity. Therefore, the stability of dynamic memory operation can be guaranteed and high integration can be achieved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional semiconductor device, Fig. 2 is a diagram II of a semiconductor device capable of non-destructive readout, Fig. 3 is a cross-sectional configuration diagram of a conventional semiconductor device, and Fig. 4 is a diagram of a semiconductor device of the present invention. FIG. 5 and FIG. 6 are cross-sectional diagrams showing other embodiments of the present invention, respectively. 51... Semiconductor substrate, 52... Element isolation region, 52
a... Inversion prevention layer, 5 J + 5 Jl * 5 J
Goose...r-17- Insulating film, 54... First dirt electrode (write word line), SS-... Semiconductor layer, 55a... First impurity region, 55b... Second impurity region, 56I... drain (first region), 57... source (second region), 58... inversion layer (second region), 59m, 59b
...Contact hole, WB...Write bit line, 'RB--Read bit line. Applicant's agent Patent attorney Takehiko Suzue 18-

Claims (3)

[Claims] (1) A semiconductor substrate, a first region and a second region formed separately in the semiconductor substrate, and f-) an insulating film on the semiconductor substrate region sandwiched between the first region and the second region. a first e-) electrode formed on at least a part of the second region; a semiconductor layer having an impurity region, and a change in a channel region induced between the first and second impurity regions of the semiconductor layer in response to a change in the potential of the second region is controlled by the first impurity region. A semiconductor device characterized in that detection is performed through a region and a second impurity region. (2) The semiconductor device according to claim 1, wherein the semiconductor layer is made of single crystal silicon. (3) The semiconductor device according to claim 1 or 2, wherein the dirt insulating film is a silicon oxide film.