JPS59151244A - Detection for trouble of computer instruction code - Google Patents

Abstract

PURPOSE:To detect trouble without adding trouble detecting hardware by setting distances to all instruction codes. CONSTITUTION:When an instruction code is transferred from a main storage device 1, it is latched in an instruction register 15 of a CPU5 from a program area 2 through an input bus 9. The control is jumped to an instruction processing are in accordance with a jump instruction in an instruction code allocation area of a program area 16. At this time, if the instruction code is normal, the control is jumped to an instruction execution area to perform a coresponding processing. If an error occurs in the instruction code, the control is jumped to a wrong instruction processing area to perform an instruction code reloading processing. If several instruction code errors are detected continuously, the error is detected as permanent trouble of the instruction code, namely, the trouble of a main storage device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer that is applied to condition 1 in the field of computer application, where requirements for small size, light weight, low running costs, and high reliability are strictly required. In recent years, with the advancement of computer utilization technology, there has been a demand for more complex functions and improved reliability.Failure countermeasures from both the linftware and hardware perspectives have been taken up as an important issue. Especially when the period of use becomes longer.

In addition, the more important the role of computers is, the more they are required to improve their performance. It has been revealed that computer failures occur in the main memory, which is composed of many LSI components. Among the main storage devices, RA~1 is sensitive to the logical reversal phenomenon of take caused by after-sound and radiation (Banok-zink and radiation from space). In this sense, it can be seen as the most important item in terms of measures against failures in storage devices and improvements in computer reliability. Among the malfunctions of the 100-100 system, the most common one is the occurrence of a change in the program 70- due to an error in the instruction code.

In many cases, program runaway occurs, making it impossible to perform normal control and calculations. It is difficult to prevent failures in the main storage device, and the most important issue is how to efficiently deal with failures when they occur.As a countermeasure, hardware such as an error detection circuit is generally added. However, under conditions where physical quantity constraints are severe, it is important to minimize the addition of hardware and take more effective measures.

In order to address the above-mentioned problems with PCs, the present invention is characterized in that errors in the instruction codes of 11 machines can be detected by a microprogram without adding any hardware.

As a conventional instruction code failure detection method, there is a parity Cheno Kubla method shown in FIG.

In FIG. 1, (1) is a main memory, (2) is a program area, and (3) is a parity bit area. The main storage device (11) is basically configured by adding a parity focus area (3) to a program area (2).

(4) is the central processing unit, (5) KE0PU, (6)
is a data output bus that transfers the instruction code to the program area (2), and (7) is the instruction code of the data output bus (6).
(8) is a baritigi inertator that generates a baritibinoto from a barity,
), (9) is a data input bus that transfers the instruction code from the program area (2) to the central processing unit (4), and 01 is the parity input bus that transfers the parity bit area (3) to the parity bit area (3). Bus, 01)
are data input bus (9) and parity input bus, 10)
Detects instruction code errors from both data.
J Detector, (1 second is an error identification string that reports the detection result of the parity detector circle to Op +, + +5+.

In this way, the parity check method is based on the fundamentals of computers. Parity Tector ++Dt
It has an elaborate structure.

Next, the operation will be explained.

The instruction code is transferred to the main memory device Fil+ using OP U 1.
51 via the data output lotus (6). The instruction code is input to a parity generator (7), and even (or odd) parity bits are generated. The number of parity hits varies depending on the system, but is generally generated at a rate of 1 bit per 1 byte (8 bits). For example, when the data output bus (6) is 16 bits, the number of parity bits is 2 bits, and the data is transferred to area (3) via the parity output bus (8) (7 to parity bit).

When transferring an instruction code from the main memory i11, the instruction code 1 and parity bit are transferred from the program area (2) and parity bit area (3) to the data input bus (
The data output bus (9) and the parity input bus (ll+i) are transferred to the central processing unit (4) via the parity input bus (1α).
1) A harness check is performed for even numbers (1 (or odd)). If the set parity results are different, it is assumed that an instruction code error has occurred and the error identification column 02 is checked. Notify the failure to CP Ll +51 through 7.

This error identification signal f6C of around 0 is generated as an interrupt process to 1, for example, OPU +5+, depending on the system design, and recovery process is performed by the failure countermeasure routine.

In this way, the conventional method of detecting faults in instruction codes using the parity check method includes the parity bit control area (3), the validity delay controller (7), and the parity checker OD.
It is necessary to add a hardware circuit to make up the system, which increases the number of parts, which is one of the disadvantages of application to systems where compactness, lightness, and low power consumption and output are important issues.

1 is an example of the parity bit area (3), parity checker (7), and parity checker (If), which are circuits for parity checking. There was also a drawback that it could be misjudged.

This invention was made to solve the shortcomings of Konera, and provides a method that can detect failures simply by setting distances to the 7-section code without adding hardware for mydriasis detection. be.

Hereinafter, FIG. 2 for explaining one embodiment of the present invention is as follows.
This is the basic configuration of a computer according to the present invention, and shows a hardware configuration in which the parity check circuit of FIG. 1 is completely removed. FIG. 3 shows the main circuit configuration of 0))[1(5). (1 moat is the arithmetic unit that controls logic and numerical operations, 0
4) is a control unit that controls the operation sequence of OP U (51), (one is an instruction register for manually inputting the instruction code via the data human power bus (9), q6) υ-1 instruction register This is a microprogram area that decodes the instruction code stored in 051 and executes processing.The microprogram area is generally constituted by a ROM-based memory circuit.

FIG. 4 shows the structure of the main areas of the microprogram 1 music area + lfa. The surface has instruction code assignment 'i@m'.

(1 & is the instruction execution area, 01 is the illegal 1 order processing area. The instruction code allocation area OD is an instruction register (an area that is directly accessed by one instruction code, and is made up of individual jump instructions. If the instruction code is correct, the jump destination of the jump instruction is the packing execution area (field); if an error occurs and the incorrect addition code is reached, the destination is the invalid instruction processing area (1! In the 1st page, a microprogram corresponding to each instruction code is written, and the control unit 04) and the calculation unit 0y are controlled according to the appropriate processing sequence. A fault countermeasure processing program is written when this is detected.

FIG. 5 shows the structure of the instruction code allocation area 07). (21J is the microprogram address.

c! I) shows a jump command list. The instruction code is
It is encoded in a form that corresponds to the address code of the microprogram address @ and the advance payment. For example, in Figure 5, the microprogram address ■ is 2 in hexadecimal.
It is displayed in digits, that is, in binary 8 bits. At this time, the instruction code is represented by an 8-bit code. For this reason.

The instruction code itself stored in the program area (2) of the main memory (11) can directly specify microprogram address 00. Therefore, this instruction code can be used to directly specify the microprogram address (4 ) By using a Hamming code, for example, and giving the code a certain distance (for example, Figure 5 shows distance 2), it becomes possible to detect errors in the instruction code.Table (21) is a list of jump instructions. , shows the state of this instruction code assignment 71?.The shaded area is microprogram address 1.
This is an area that is prohibited from being allocated to instruction codes.

Instruction code 1 (When an error occurs, the instruction code changes to L.
+Changes to the code of the microprogram address (A) corresponding to the shaded part of the instruction code allocation area 0η. This makes it possible to detect the occurrence of an error in the instruction code. Fifth
The figure shows an example in which the distance is set to 2, and a 1-bit error of 1 in the instruction code can be detected. If the distance W#L is n, then (n
-1) It is possible to detect even bit failures.

Next, the operation will be explained.

When transferring the Onsha code to the main memory (1).

The set 611 code is directly transferred to the program area (
2) Store. Main memory (when transferring from I+ 6
．． The instruction code is latched from the program area (2) to the instruction register +15) of the control unit 04) via the data bus (9). The instruction code launched into the instruction register (1) directly specifies the microprogram address ■ which is the instruction code allocation area 01 in the microprogram value area OF5, and jumps to the instruction processing area according to the corresponding jump instruction list 00. When the instruction code is normal, that is, when the instruction code matches the microprogram address (a) other than the shaded area on the jump instruction list CD, the instruction execution jump is executed (1 & jump, and the process corresponding to each instruction is executed. .

When an instruction code error occurs.

That is, when the instruction code matches the microprogram address in the diagonally shaded part of the jump instruction list Qυ, it is judged as an illegal instruction code and the instruction is jumped to the illegal instruction processing area O1. In the illegal instruction processing area O1, instruction code reload processing is performed. If an instruction code failure is detected several times in succession, the error can be detected as a permanent failure of the instruction code, that is, a failure of the main storage device (1).

In this way, this invention adds a humming code to the instruction code itself.
By providing a distance such as a code and directly assigning the distance to the execution address of the microprogram, it is possible to completely detect whether or not a failure has occurred in the instruction code. Due to this.

It is possible to suppress the addition of hardware for detecting faults in instruction codes, which is a drawback of the conventional method.

Although the above description has been made regarding the case of a computer, the present invention is not limited to this, and the present invention is not limited to this. and a microphone [which defines the basic operation of the control section]
The present invention may also be used for programmable control devices and arithmetic devices having l programs and the like.

As described above, according to the present invention, by setting a distance for the instruction code and also making this instruction code match the address of the microphone [coprodarum area], even if an instruction code error occurs, the distance is set and the distance is set for the instruction code. It has the advantage of being able to jump to the illegal instruction processing area in the microprogram area and detecting all errors in all codes without the addition of special hardware.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a parity check circuit, Fig. 2 is a basic block diagram of a computer as an embodiment of the present invention, Fig. 3 is a block diagram of the CPU portion of Fig. FIG. 5 is a diagram showing the configuration of the microprogram area shown in FIG. 4, and FIG. In the figure, il+ is the main memory, and (2) is the program area. (3) is a parity bit area, and (4) is a central processing unit. f5) fd OP U, +711 is validigi x4
rater, 'J'; 3 is parity techter, 041rj
Control unit, fl! i) is an instruction register,
(() is the microprogram area, (1ε is the instruction execution area, Ql is the illegal instruction processing area, ((a) is the microprogram address, and Cυ is the jump instruction list. The parts are indicated by the same reference numerals. Fig. 2 Fig. 3 Fig. 5 Fig. 4

Claims (1)

[Claims] In an instruction code failure detection method for detecting an error in a main storage device or an instruction code error occurring during transfer to a central processing unit during instruction execution and suppressing a program execution error caused by an invalid instruction, 17. A method for detecting faults in computing machine timing codes, characterized in that by setting distances for all instruction codes, detection of incorrect instruction codes is carried out by a microprogram using fault detection hardware. .