JPS59149065U

JPS59149065U - level display device

Info

Publication number: JPS59149065U
Application number: JP4330283U
Authority: JP
Inventors: 岩谷　利男; 俊三井上
Original assignee: キヤノン株式会社
Priority date: 1983-03-28
Filing date: 1983-03-28
Publication date: 1984-10-05

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のプロセサーカメラの構成を示す概略図、
第２図は本考案の一実施例を示す回路図、第３図は本考
案の増減検出器についての一例を示す回路図である。２１・・・レベル検出器、２２・・・発振器、２３゜２
４．２５・・・比較器、２６・・・増減検出器、２７゜
２８．２９．３９．４０．４１・・・インバータ回路、
３０．３１．３２，３３．３４゜３５．５４゜５６・・
・アンド回路、３６．３７．３８・・・オア回路、４２
．４３．４４・・・表示灯、５１・・・パルス発生回路
、５２・・・カウンタ、５３・・・サンプリング回路、
５５゜５７・・・ＲＡＭ、５８・・・減算回路、５９・
・・正負判別回路。Figure 1 is a schematic diagram showing the configuration of a conventional processor camera.
FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing an example of the increase/decrease detector of the present invention. 21... Level detector, 22... Oscillator, 23゜2
4.25...Comparator, 26...Increase/decrease detector, 27°28.29.39.40.41...Inverter circuit,
30.31.32, 33.34゜35.54゜56...
・AND circuit, 36.37.38...OR circuit, 42
．． 43.44... Indicator light, 51... Pulse generation circuit, 52... Counter, 53... Sampling circuit,
55° 57...RAM, 58...Subtraction circuit, 59.
...Positive/negative discrimination circuit.

Claims

[Scope of utility model registration request]

In a level display device including a plurality of indicators, each of which displays a measured quantity of an object to be displayed according to each level, means for detecting an increase or decrease direction of the measured quantity;
A level display device comprising means for switching a display mode of the display device which is displaying the level from a blinking display mode to a continuous display mode according to the increasing/decreasing direction.