JPS59148917A - Data transfer circuit system - Google Patents

Abstract

PURPOSE:To form a titled system economically without using a specific gate by using a data line for data bits excluding a check bit as a writing data line and a reading data line in common. CONSTITUTION:A data control part 1 is connected to a data storage part 3 through a writing data line 5 for a check bit from a check bit generating circuit 13, a reading data line 6 and a common two-way data bus 7 for data bits excluding the check bit to form a data transfer circuit. In this case, the two-way data bus 7 is used as one end terminal and a terminal resistor 8 is provided to the control part 3 on the data transfer circuit 2 side. Data sent from a control device in a storage device are temporally latched in a register 15 and then written in a memory element through the two-way data bus 7 and normal gate drivers 9, 10. The data read out from the memory element are corrected by an error detecting circuit 14 and a correction circuit 17 through a transfer circuit 4 and the bus 7, latched by a register 16 and then transferred to said control device.

Description

[Detailed description of the invention] [Field of application of the invention]・ The present invention relates to a data control section in a storage device.

ECL (Emj ter Co.
This invention relates to a data transfer circuit system using the Apple 20 Loyic.

It is something.

[Prior art]

FIG. 1 shows a conventional unidirectional data bus.

1 shows a data transfer circuit in a storage device in which a write data line 5 and a read data line 6 are provided separately. .

Generally, a storage device is a data controller 1 and a data controller.

It is divided into an evening storage section 6 and an evening storage section 6. The data control unit 1 receives addresses, data, and control from the control device of the storage device.

Upon receiving both signals, it controls the writing and reading of data into the data storage section 3, and when performing a read operation, sends the viewing data back to the control device of the storage device.

2.4. are a data control section and a data recorder, respectively.

It is a data transfer circuit in the storage section, and is usually a gate driver.

Iba91 normal gate receiver 10. And near the end.

It consists of anti-8. Here is the normal gate.

is a gate that has the ability to drive a 50Ω line.

This is a dry 25Ω line, which will be described later.

Distinguish it from special gates that have the ability to

The data storage unit 6 includes a memory element and data 0. It is composed of peripheral circuits such as a transfer circuit 4.

Data is stored here.

Check bit and data pin during write operation.

The data control unit 10 is normally dry at the gate 9.

The signal is transferred from pin 11 to write data line 5 to pin 11 to normal gate 5 to receiver 10 and written to the memory element.

It will be done. At this time, the terminating resistor 8 serves as the receiving end terminal, while
During read operation, read from the memory element.

Check bits and data bits are data.

The data is transferred from the normal gate driver 9 of the storage unit to the bin 11 to the readout 10, and then from the data line 6 to the pin 11 to the normal gate receiver 10 of the control unit. At this time, the terminating resistor 8 becomes the receiving end terminal.

The disadvantage of FIG. 1 is that each check bit and data bit requires 4 input/output pins 11, 2 data lines, and 2 terminating resistors.

This is the point. Especially the recent one (L8i).

As the number of bins becomes higher and higher, the number of bins becomes increasingly insufficient.

In this case, the unidirectional data bus method becomes even more disadvantageous.

Become. 2゜Figure 2 shows a method that has been used since the beginning of America to reduce the number of bins in Figure 1, in which the write data line and the read data line are shared, that is, a bidirectional data bus 7 is used. be. here.

In FIG. 2, the same numerical symbol as in FIG. 1 has the same meaning as 5.

Since both the check bit and data bit were bidirectionally interrupted, the number of pins and data lines were both halved.

I was able to do something. However, the bidirectional data bus 7°
This is a 0Ω transmission line, and in order to achieve impedance matching, a terminating resistor 8 is provided at both ends, terminating at the data control section and the data storage section, respectively.

Ru. Therefore, it can be used as a bus driver for 25Ω transmission.

A special gate driver 12 with line capability is installed.

- It has the disadvantage that it is required for each data transmission circuit for the control section and data storage, and it does not reduce the number of terminating resistors.

[Purpose of the invention]

The object of the present invention is to drive a bidirectional data bus by means of a normal gate, and in this system, data 2°, 3.

This will increase the time it takes to confirm and reduce throughput.

We decided to make Nickbit a unidirectional data bus.

This eliminates the need for special gates and reduces the amount of material needed.

And a data transmission circuit that prevents a drop in performance.

Our goal is to provide the following. 5 [Summary of the Invention] Normally, a bidirectional data bar is used to drive the gate.

One end of the bus can be terminated at either the data control section or the data storage section. in this case,.

Noting that the read operation has a critier 10 cal path than the write operation, it was decided to terminate at the data control section. On the other hand, during a write operation, the data confirmation time of the check bit data is delayed from the data bit only by the number of stages of the generation circuit, and the number of check bits is small. Pay attention to and check it.

The data bus is bidirectional.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

explain. 2゜・4
- In the present invention, the bidirectional data bus is terminated at one end.

By making it possible to drive with a normal gate.

be.

In FIG. 3, the data bits are bidirectional bars.

The difference from FIG. 2 is that the terminating resistor is terminated at one end only for data bit 1.

Is Rukoto.

Here, the data flow in FIG. 3 will be explained.

The data sent from the storage device control device is -.

The register 151C is latched. This data is 10
Register 15 → Normal gate driver 9 → Pin 11 → Bidirectional data bus 7 → Pin 11 → Normal gate receiver 1
0 is written to the memory element via .

- 10,000, data pins read from the memory element.

A normal part of the data transfer circuit 4 in the middle stage is shown in FIG.

- drive driver 9 → pin 11 → bidirectional bus 7 → pin.

11 → Normal gate receiver 10. And error detection.

Check with circuit 14 and if there is an error, use correction circuit 17.

Modify register 16 TLC-bearing latch and storage.

Transferred to the control device. What should be noted about data flow of 2° or more is:

- During the card operation, the termination resistor 8 of the control data transfer circuit 2 in the middle stage serves as the receiving end termination. .

- During a write operation, the terminal of the normal gate driver 9 of the control data transfer circuit 2 in the middle stage is the termination resistor 8 in the same circuit 5, and serves as the sending terminal.

be. In other words, when writing, this normal gate driver.

Tap-off occurs between the controller 9 → pin 11 → bidirectional bus 7 → pin 11 → memory unit normal gate receiver 10. 10. Next, why is the sending end terminated during write operation?

Explain. Figure 4 shows the lights marked ■ and ■ in Figure 3.

Shows the shape of a time drum. ■ is the output waveform of register 15.

Yes, ■ indicates data bit storage data transfer.

This is the input waveform of the normal gate receiver of circuit 4. Yamata, @ is write enable (to)) and mouth.

− level, it becomes active and de-energizes the memory element.

-Write evening. When writing, ■ is a tag-off.

As a result, ringing occurs in the waveform, and the minimum time required for this ringing to become active is defined.

ing. Therefore, during this period, the ringing converges.

If you do that, there will be no problem. On the other hand, when reading, K.

If it is the sending end termination, then this is the convergence time of this ringing.

The latch timing of the register 16 must be delayed by 5. In other words, the crit is during the read operation.

Calbus, so that ringing does not occur.

One-end termination was performed in the data control section. As a result,.

During a write operation, the sending end was terminated. ·next,
The data flow of the check bit will be explained below. During a write operation, the data in the register 15 is sent to the check bit generation circuit 13, which generates a check bit, and then the normal gate 9 of the upper control section data circuit 2.
Bin 11 → Write.

Data line 5→pin 11 storage data circuit 40 is normally transferred to a 5-gate receiver 10 and written to a memory element.

be included.

10,000, during read operation, reads from the memory element.

The checked bits are stored in the storage data in the lower row.

Transferred to the normal gate driver 9 of the transfer circuit 4, 2° pin 11 → read data line 6 → bin 11 → data section 1 error detected in the transfer circuit 20.

The data is transferred to the circuit 1-4, and if there is an error, it is corrected by the correction circuit 17°.

What should be noted here is that the check bit is constructed from two unidirectional data buses. .

The reason why it was not made into a bidirectional bus like the data bit is that
Due to the following reasons.

Figure 4 OK, check bit write operation.

The time waveform (point ■ in Figure 3) is shown. The reason that ■ rises 11' later than ■ is from the check bit.

This is the number of dirt stages in the raw circuit. ■The dashed line is.

Cod indicates the case of transmission on a bidirectional data bus.

Ringing is occurring due to pull-off. Therefore, the time required to activate ■ is the sum of the delay due to the number of gate stages and the convergence of ringing (15).

bawl. (Figure 4, broken line part of @) Therefore, lie.

When operating, the check bit is critical.

The bus is one-way de to improve this.

-Tavas. , 1° As a result, the solid line waveform shown in Figure 4 @ is obtained.

Also, it acts faster because the ringing is gone.

Eve can now do it.

However, as a result of converting to a unidirectional data bus, the number of pins, data lines, and terminating resistors are doubled, but the number of bits per chip is twice as large as that of a large computer.

In this case, it is about 1/8 of the data bit, so the effect is small.

do not have.

〔Effect of the invention〕

According to the present invention, 10. The check bit is a unidirectional write, read/read only data line, and is the receiving end terminal.

■ Data line for writing and reading data bits.

The bus is shared, making it a bidirectional bus, and one end is terminated only in the data control 5 control section.

Since the data transfer circuit can be configured by ■ and ■,
Both are single-ended data buses and are called buses.

It is possible to use a regular guest as the driver instead of a special gate, making it cheaper. 2゜■ Compared to the case where all bits are unidirectional, the number of data lines and the number of terminal resistors can be reduced to about -1. .

■ Since the critical bus is at the receiving end, the data is smaller than if all bits were unidirectional.

The transmission section will be almost the same.

[Brief explanation of drawings]

Figure 1 shows a conventional all-bit unidirectional data bus. The data transfer circuit diagram shown in FIG. 2 is a conventional all-bit unidirectional data bus with one terminal at both ends. The data transfer circuit diagram of FIG. 3 is the same as that of the 101st embodiment of the present invention, and FIG. 4 is the same. Figure 3 ■■■ and WE) 17) Waveform diagram during write operation. DESCRIPTION OF SYMBOLS 1...Data control part 2...Control part data transfer circuit 3...Data storage part 4...Storage part data transfer circuit l:5...Write data line 6...Read data line. 7...Bidirectional data bus 8...Terminal resistor 9...Normal gate driver (source side) 10...A normal receiver (sink side) 11...I/O bin 12...
・Special gate driver. ). 13...Check bit generation circuit 14...Error detection circuit 15. Is...Register
. 17...Error correction circuit] 0 Early 1 Figure Sheep 3 Figure [ Early 4 Figure

Claims (1)

[Scope of Claims] 1. In an ECL level data transfer circuit that connects a data control unit and a data storage unit of a storage device, in order to detect and correct an error in the output of stored information. , the check bit added at the time of programming is for writing to the data storage unit. A read-only data line and a read-only 10 data line are provided, and the data bits except check bits are
One for writing and one for reading. -Sharing the evening line and data control unit. In addition, a terminating resistor is provided to connect these two types of data. 15 data transmission circuit system characterized by being configured with a parallel wire.