JPS59148431A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To increase gain and operating margin by using an amplifier where a logical threshold voltage is variable in an amplifier such as CMOS inverter, and controlling automatically a logical threshold value to bring it to the vicinity of a reference voltage. CONSTITUTION:When the logical threshold value of a simulating amplifier A1 and a main amplifier A0 is at a potential higher than a reference voltage VR1 in the initial state, an output signal O1 of the simulating amplifier A1 goes to a level higher than a reference voltage VR2 and an output signal O2 goes to a negative potential. Thus, the potential of a control signal Vc1 is shifted negatively by a control signal generating circuit G1. The logical threshold value of the simulating amplifier A1 and the main amplifier A0 is shifted to a low potential by this control signal Vc1. When the reference voltage VR1 and the logical threshold value are made equal after a series of operations continue, the potential of the output signal O1 and the reference voltage VR2 is made equal and when the potential of the outut signal O2 is reduced to zero V, the control signal Vc1 is held.

Description

[Detailed Description of the Invention] (Industrial Application Field) This article relates to an amplifier circuit used in semiconductor integrated circuits that is advantageous in terms of interest and low cost and has a large operating margin. Out.

(Prior Art) Conventional amplifier circuits include a large number of wires, and CMOS inverters are also used as a part of the amplifier. C.M.O.
The S inverter is shown in FIG.
The gates of the P-channel transistors (J and N-channel transistors Q) are connected together, and the input signal Ir'
manually, supply the lth voltage m-VDD to the source of the p-channel transistor, supply the second source of a to the source of the n-channel transistor, and connect the p-channel and n-channel The trains of the transistors are connected to each other and the output signal α is extracted.
Perform low voltage binding 1 to VBB'. The transfer characteristics of the CMOS inverter are as shown in Figure 2.
There is a %r sign that the output signal suddenly changes when approaching the THL. This logical threshold voltage is determined by the threshold voltage+'blood flow gain ratio of the p-channel transistor and the n-channel transistor. Here, the intermediate potential between the high level and low level of 8-Q is set as the total reference voltage, and the commercial threshold voltage is around the reference voltage (rc setting square) and the human gain is 1.
do. However, since the operating range in which this large gain occurs is small, as the threshold voltage increases due to fluctuations in the OM force and the Froese constant, the gain becomes smaller in the operating range. The excitation point shifts to , and the amplifier no longer functions as an amplifier.

For this reason, this circuit is used only when the amplitude of the input signal is large, such as the TTL input interface circuit, and when the input signal amplitude is small, such as the h:cL input interface circuit. I couldn't use it.

(Object of the Invention) The present invention was proposed in order to improve the above-mentioned drawbacks, and an object of the present invention is to provide an amplifier circuit with a large gain and a large operating margin.

(@Ming's configuration) In order to achieve all of the above objectives, the present invention identifies the relationship between the input signal and the logic threshold voltage, and expresses it as a high level and a low level corresponding to the result of the identification. There is an amplifier circuit VLh which outputs a binary signal 1r, the main amplifier to which the front voltage information is input δt, the simulated amplifier 7 to which the reference voltage is inputted, and the simulated amplifier 7 to which the reference voltage is inputted. 11if+L, which generates a control signal by observing the output pressure, and the control signal e.
(The purpose of the invention is to create an amplifier circuit in which the logic threshold voltages of the present amplifier and the Matata pseudo-amplifier are made similar to t%.

The general rule is that the present invention has two logic thresholds in the amplifier circuit.
The present invention is characterized by the use of an amplifier in which the 1Ik voltage is variable, and the addition of a control function to automatically set the voltage close to the 116% reference voltage.

Next, implementation of the present invention? ll Explain the situation with the diagram 0
It should be noted that the embodiments are merely illustrative, and it goes without saying that changes or improvements may be made without departing from the spirit of the present invention.

FIG. 3 shows the first embodiment of the amplifier circuit of the present invention, which is composed of 11 simulated amplifiers A, 7-Ao, a comparison (b) circuit, and a control signal generation circuit G, and the simulated amplifier AI is # Thermal voltage vR1 control (G No. VC1 is input, output signal 01 is generated, comparison circuit B1 is 01 and reference voltage ■.

Full human power output signal 1 output signal 0+t'' is generated, and the control signal generation circuit G1 is operated manually to generate control signal ■c. Occurs.Mock amplifier A.

This amplifier AO outputs the inverted signal 0+ r Os'l of the human input signal VR,,I, and outputs the signal "R4*I".
I 7>E 77 puA.

Output 1g when the potential is lower than the logical threshold fuim pressure of Ao
No. 0. ．． 0. becomes high, and conversely, when the signal VR,,I, is still at potential, 0. ．． 0. becomes rocky. Anne 1A, ,
The logic threshold voltage of Ao is controlled by the control signal VC8, and when the signal VC reaches the red potential, the logic threshold voltage goes to the low potential, and the signal VC1 goes to the low potential. In this case, the logic threshold voltage is controlled to be a low potential. Further, the signal vR1 is set between the high level and the low level of the input No. 18 (2), and the rLs signal VR2 is set at IW4 between the high level and the low level of the output (Qi) O1.

The comparator circuit B detects the potential difference sound between the signals O3 and VR2, generates an output signal Oak, and outputs a signal 0. When the potential is higher than the signal VR1, the signal O! is a negative potential, and signal O1 is a signal.

When the potential is extremely low, the signal 02 becomes a positive potential. The control signal generation circuit G1 receives an input signal 0. The control signal VcI is controlled by the input signal 0! When is positive, the control signal VC't^ is in the direction of the potential, and when the human chi H No. 02 is negative, the control signal vc,i
Shift to lower potential.

Also, simulated amplifier A, and real amplifier A. The logic thresholds of 3 fL are controlled to be equal to each other.

Next, the operation of the first embodiment of the present invention will be explained below.

Now, in the initial state, the simulated amplifier A1 and the main amplifier A
. Suppose that the logical result rarely occurs at a higher potential than the reference voltage R1, and at this time, the output signal O5 of the simulating amplifier A1 becomes high level and is outside the reference voltage.

Therefore, the output signal O3 becomes a negative potential. Therefore, the control signal generation circuit G,
The potential of No. d and ■c shifts in the negative direction. This control signal VC, model amplifier A, real amplifier Ao (7)
-The physical threshold shifts to a lower potential. This series of operations continues, and when the reference voltage becomes equal to the logic value, the potentials of the output signal 01 and the voltage outside the reference voltage become equal, and the potential of the output signal O1 becomes V, and at that point The potential of the open side 1 signal VC5 at is held. Amplifier A+ + Ao'
J 8R threshold voltage is lower than reference voltage ■R1 Potential V (
If so, the control signal vc1 changes until the reference voltage vR and the logic threshold become equal to each other by an operation opposite to the above.

Through this series of operations, the logic of the p1 amplifiers A and AO is controlled so that 1fi is always equal to the reference voltage vR3.

As shown diagonally above, the reference voltage VR, , VR, i amplifier A (
By setting the operation head with a large gain of 1, it is possible to realize an amplifier circuit with a large operating margin and a large gain.

FIG. 4 shows a second embodiment of the present invention, in which a simulated amplifier, A4. It is composed of a main amplifier input, a comparison circuit B + Bj + a control signal generation circuit G, and the pseudo amplifier Aj has a reference voltage VR3 and a control # signal VC, and outputs a signal O6 manually.
A meeting occurred 1. The simulation amplifier A4 is outside the reference voltage, and the control HM
No. ■. , the output signal Oat'' is generated by inputting the comparator circuit Bt#'i output signal 04 and the reference voltage vR, Th, and the output signal 06 is generated by inputting the output signal O8 and the reference voltage vR4t - human power. The control signal generation circuit G generates the output signal 06.
! The output signal Os is generated by inputting the input signal 1tk. Here, to this amplifier 〇 logic threshold 1 @ voltage t VT
HL, and the logic threshold voltage of the simulated amplifier is VT)L.
L+△V, the logic threshold voltage of simulated amplifier A is VTH
Set it so that it becomes L-C■. Simulated amplifier AS t
Aa r main amplifier A0. The functions of the comparison circuits Bt and Bs are the same as those in the first embodiment of the present invention, and the control signal generation circuit G
, when the output signal 06 is high, the OII signal VC is shifted to the full high potential side, and when the output signal 07 is high, the control signal vo, k is shifted to the low potential side δ, and the output signal Us, O
When both v and V are low, the function is to hold the potential of the control N signal Vc at that time.

Next, a complete explanation of the operation of the second embodiment of the present invention will be given.

First, consider the case where the voltage VTHL is set between ■R1-ΔV and VR11ΔV, and is smaller than the signal amplitude of the human signal generator 2, which is 2×2・ΔV. When the logic threshold voltage VTHL of the amplifier A is at a higher potential than the reference voltage vRs, the output signal 0° becomes a high potential, and the lump threshold voltage VTHL of the simulated amplifier becomes
Since the voltage V is at a lower potential than the reference voltage vR3, the output No. 18 O5 becomes a low potential. Since the output signal 04 has a lower potential than the reference voltage VR, each output 06 has a low potential, and since the reference voltage VR4 has a higher potential than the output signal 03, the output signal 0) has a low potential. Therefore, the input signal 06,0? of the control signal generation circuit G2? Since both have a low potential, the potential of each control number Vc at that time is held. At this time, the high level of input signal 2 is at a higher potential than VTHL, and the low level of input signal I2 is at a lower potential than VTHL.
, the inverted signal is output. Next, the logic threshold voltage V
Considering the case where THL fluctuates and becomes a higher potential than vR1+V, the logical threshold voltage of the simulated amplifier As'vT
Since HL+mu is at a higher potential than the reference voltage VRs, the output No. 3 04 is up to the SJ turtle potential 1, and the logic threshold voltage VTHL-mu of the simulated amplifier A4 is at a higher potential than the reference voltage vR1. Therefore, the output signal 08 changes from low potential to low potential. However, the output signal O of comparison circuit B? However,
potential, and is controlled by the control signal generation circuit G2 (g V
. 2 is shifted to the lower potential side. The result is simulated apricot A
j.

The logic threshold of this amplifier A0 shifts to the lower potential side, and this operation causes the copper salt threshold voltage VTHL to be VR80△
■Continues at 1, which becomes a low potential. When this operation is completed, the output signal O1l of the simulation amplifier A4 becomes low potential again.
The output signal 6 of the comparator circuit B becomes a low potential, and the potential of the control signal c at this time is held. Finally, if we consider that the logical threshold voltage VTHI changes to a lower potential than VR, - V, then the logical threshold 1 of the simulated amplifier A3
The direct storm pressure VTHL+V becomes a lower potential than the reference voltage vR5, the output No. 4H 06 of the comparator circuit B2 becomes a low potential, and the control signal Vc shifts to the high potential side. This operation continues until the logic threshold voltage VTHL reaches a potential of VR3-ΔV.

As a result of the above series of operations, when the logic threshold voltage vT fluctuates and goes outside the voltage range of ±△V, the control signal Vc
, and shift the potential of VTHL force S■R.

The voltage is controlled to be within the voltage range of ±ΔV.

FIG. 5 shows a third embodiment of the present invention (/, 1″″C
: Ruri, simulated amplifier A4 r real amplifier AOI comparison circuit B
,.

Each circuit consists of a B111 control number generation circuit G, and the lock function is the same as that of the second embodiment of the present invention.
The difference is that it is set to HLVc. Also, the reference voltage VR input to the comparator circuit B4 is VR5-△
rL is set to vR, and the reference voltage V input to the comparison circuit B6
R, is set to vRIs+muVR. The operation of the present invention will now be explained as follows: Amplifier A6 r A? The copper salt threshold voltage "THI+" is the reference voltage VR, and the potential of the output 0 of the simulated antenna 7°A6 is the reference voltage VR.
6, the outputs of the comparator circuits Ba and Bs each have a value of 0.6. . , 011 are both turned off at a low potential, and the potential of control No. 100, VC, at this time is held. VTHL fluctuates to the high potential side and the output signal 0° potential or skeleton voltage V
When the potential becomes higher than R7, the output signal O1I of the comparator circuit B becomes the next potential, and the output control signal O1I shifts to the lower potential side.

17. When VTHL changes to the low potential side and the potential of the 1st output color number O, becomes a V lower potential than the reference pressure VR6, the output signal 01o of the ratio d19 circuit B4 still becomes the potential, The Tsumugi ft+lJ bait number VO1 shifts to the potential side.

From the above operation, the main amplifier AO and the simulated amplifier A6
The logic threshold voltage VTHL of 1 simulated A6 changes.
The output signal of 0. When the voltage is outside the voltage range of VR5±△VR, the potential of the control signal Vc is shifted and VTHIJ is controlled, and the output signal 0. is controlled so that it always falls within the voltage range of vR, ±ΔVR.

FIG. 6 shows a fourth embodiment of the present invention, which includes simulated amplifiers As, A@ and comparison circuit B6. B? and control signal generation (9) path G4, HG5, G6, and the main amplifier AO, @pseudo amplifier A8. A. Comparison circuit B61 B
q + control 1l 141 alarm signal generation circuit G41 Gll,
The present amplifier AO has the same functions as the first embodiment of the present invention, and the control signal generating circuit G6 includes resistors g, , Rt and a cap C+.
, Ct, whose control signal vC,h is applied to the first terminal of the resistor R1 and the capacitor C8, and the control signal v is applied to the first terminal of the resistor R8 and the capacitor C1. , k manpower, resistance R,,R,
and capacitance: C+, second terminal of Ct? They are connected to each other and output as control signals VC,'. Clarifying the connection relationship between each block, the simulation amplifier Ag has a reference voltage vRs and a control signal Vc.

The comparison circuit B6 receives the output signal 0□ and the reference voltage vR1° and outputs the output signal 0+t.
sk output and control signal generation circuit G+k output signal O1,
? The control signal VC4 is generated manually, and the simulated amplifier A has a reference voltage vR and a control signal V. , and output signal 0
1. The comparator circuit B outputs an output signal 016 by manually inputting the output No. 18 014 and the reference voltage VR, OK, and the control signal generating circuit G generates a control signal ■ C, by manually inputting the output signal 0+s. However, the control signal generation circuit G6 generates the control signal, V
(34 and VC, k are manually generated and the control signal Vc, ?!- is generated, and this amplifier A. is the human input signal I4 and the control signal v (,, i
It inputs and outputs one output color gO+t'c. here,
Set the reference voltage vR9 to the high level potential of the power value -1+I4.

Next, a seventh explanation of the operation of this embodiment will be given.The amplifier ^, the soft circuit B6. Control 18'@ A circuit section consisting of the generating circuit G4 and A@, B? , G6''''C tL performs all the same operations as described in the first embodiment of the present invention, and therefore the control signal V. , the potential of the amplifier is the logic threshold voltage of the amplifier VB.

The control signal 11L of the control signal ① becomes the potential set to the logical threshold voltage iVB of the amplifier A9. Then, the control (1=i generation circuit G6) generates a voltage Vc6 intermediate between the control signals c4 and ccl+.
．． Ru. Therefore, the logical value of this amplifier A0'! The pressure is
It is set between the high level and low level of the input (g+5It).

7 with the above VC explanation, from the first embodiment to the fourth embodiment
R, y VRs r vRclr (■R8+■Ro
)/2K t@t” is controlled so that it is equal to 1.

Reference voltage ■, , VR,, face, , (%8+VR9
) 72 Udemoto Anzu's large gain 'f1m Ff ti
By setting it in the lt region, it is possible to realize an amplifier with a large operating margin and a large gain. In addition, since it can be made more easily, it is possible to reduce the number of stages required for the U.S. nuclear system, which is required to be 7, and increase the speed and reduce the power of the enemy.

The amplifier used in the first and fourth embodiments above is as follows:
Is it just one frying stand? Although shown, several main amplifiers can of course be provided in parallel.

FIG. 7 shows a first example of a logical 1lkt-controllable amplifier used in the present amplifier and pseudo-amplifier of the present invention, and includes a source follower circuit F and a capacitor C1.
The source follower circuit F is composed of a p-channel transistor Qs and an n-channel transistor Q4, and the source follower circuit F is an n-channel transistor Q.

and an n-channel transistor Q used as a variable resistance element.
It is composed of 2.

If we clarify the connection relationship in detail, the transistor Q,
Power supply VDD is connected to the drain of transistor Q3 and the source of transistor Q3.
We have a meeting and the gate of transistor Q1 and '6 Jt C
3, the input signal I is applied to the first terminal of the transistor Q.
! The control signal V (1-manual power) is applied to the gate of the transistor Q.
, the source of transistor q and the source vL current utr,
V8El h, connect all the transistor Q1 resource, the drain of transistor Q, the transistor Qa and Q4 gate, and the second terminal of the container Cs, and the voltage at the contact point [signal vN, transistor Qa and Q4 Connect the drain of and take out the output signal OK from contact 17.

Next, we will explain the operation of this circuit. Source follower circuit F
A: Considering the amplifier where the result is 1, the voltage value that is greater than the threshold voltage of transistor Q1 is kj, and the voltage shifted to a low potential is present at the signal station. I'll do it. This shift tL is determined by the resistance value of the transistor Q2 used as a resistance element.In other words, the control signal vcL:/) can be controlled by pressure.The control signal gi is applied to the cylinder potential. Then, the resistance value of the transistor Q becomes smaller, so the shift amount increases, and when the control signal c becomes a low potential, the resistance value of the transistor becomes larger and the shift amount decreases.Capacitor Cj
The voltage change of the human input signal l is measured by the short cutoff r of the signal VN vc, and the transistor Q
The propagation delay due to the valve 1- is 6 times 1. Guidance
Transistors Qs and Qa with different wL properties are so-called CM
It is composed of the US Inverter Association. Since the signal VN, which is shifted to the low potential side of the human input signal Ik, is fully input, the logic threshold voltage is shifted to the high potential side when applied from the input information engineer.

This shift amount can be controlled by the control signal Vo as described above, and when this control signal Vc is set to a lower voltage, the shift amount of the primary threshold voltage toward the island potential side increases.

Figure 8 shows the logical threshold 11! The second fully controllable amplifier
An example of the configuration is shown below. In the first S configuration example, the signal vN and Ijk were applied to the gates of the transistors Qj and Q+, which have different conductivities, but in the second configuration example, the signal VNhp was applied manually to the gate of the cell transistor Q7, and the signal (m No. I'?f: Inputs to the gate of n-channel transistor Q6. In this example, 16J1"7 full input is shifted to the lower position side. Upper transistor Q.

This means that the lower value voltage has been shifted to the lower potential side.

Threshold voltage control of this transistor Q7 - information VQ
By controlling VC power, transistors Q+, Qs
The threshold voltage of this amplifier is changed.

Fig. 9 shows a third configuration example of an amplifier capable of controlling buried threshold sound. The input signal is input to the gate of the transistor Qo*Q+o, and the signal generated by the source follower circuit composed of the transistors Qo*Q+o and the gate of the p-channel transistor Q++ is inputted to the gate of the p-channel transistor Q++. The shift of the threshold voltage m is the total seven fL control signals v, , vc'
As a result, the controller 6C can be made individually.

Figure 10 shows an example of the configuration of an amplifier wJ4 that can control logical values, and one of the two source follower circuits used in the third configuration example is a p-channel transistor QI6 r Q.
It is composed of +a and comes out. Similarly to the fourth configuration example, the n Nayanel transistor Q is
+a and pcha not transition, star Ql? The threshold 1@ can be individually controlled th41:f.

In addition, the above-mentioned first to fourth configurations? ll is p channel and n
Nayanel transistors can be used together to reduce the VSSt control voltage VDD to a low voltage.

Also, capacity Cs* C:41 C111Ce+ Cr
Even if it is removed to r Cs', the first to fourth configuration waves can be operated.

FIG. 11 shows an example of the configuration of a control signal generation circuit used in an embodiment of the present invention, in which p-naya transistor Q1. tmvDDi is supplied to the source and the lth terminal of the container C8, and n
The source of the transistor Qto and the second terminal of the capacitor C1 (+) are supplied with the X source VSS, and the drain of the transistor Q1 and the capacitor C1 are connected to the drain of the transistor Qto.

Connect the second terminal of Rain and C, and the first terminal of C1jl, take out output No. 16 from the contact point, and output the human power signal S.
+? The configuration is such that a human input signal 82 is input to the gate of the transistor Qzo by inputting an input signal to the r inverter and inputting the output ' to the gate of the transistor Q+o. The operation of this circuit will be explained below.When both the human power signal 1g S1 and the human power signal S2 are at low potential, the transistor Q. y
Output signal 0 when Qto is both cutoff
1. The 0'-position is held; 1. The human input signal S is still at potential; 7.
('), the transistor Q+o turns on, the output signal Hirohito shifts to the surface potential u(11), and the human input signal S
If the potential is still lower than 2, the transistor Qxo is turned on and the potential of the output signal O is shifted to the lower potential side. In the embodiment of the present invention, both the input signal '@S and the human input signal S2 do not have a high potential YC, so there is no need to worry about such a case. This circuit is G2. of the embodiment of the present invention. G
It can be applied to the control section 3.

FIG. 12 shows an example of a circuit for controlling the copper lump threshold value. Power supply control circuit Nb CM
Consists of OS inverter 20M, ``power supply control circuit M,
is the 1JL source VDD k Vn by the control signal d.

The power supply control circuit M2 converts it into CMOS inverter j1cMK and supplies it to control No. 16 d2 = Jikan = VSStv
It is converted to S and supplied to CIVl OS Inver 20M. To briefly explain the operation of this configuration example, the controller gd+, 4\i'' is shifted to the high potential side, and the VDI
) and VS'S k to the Hirohito side, the CMUS invert jICM's @ buried threshold voltage shifts to the lower potential side with 7n, and conversely, the control (i No. d+, dtk
When the potential is shifted to a lower potential, the logic threshold voltage of the CMOS inverter CM is shifted to the higher potential side. Through this series of operations, it is possible to control the current threshold voltage.

2. The power supply control circuit Ml2M of the above configuration example! You can also omit one of them (purple).

(Effects of the Invention) As explained above, the advantage of the present invention is that the logic threshold voltage of the amplifier is always near the reference voltage VC set between the input signal's noise level and lower level. Can be controlled automatically. In the past, it was possible to always operate the amplifier at a large gain operating point, and
It is possible to realize an amplifier with a large gain and a good margin made by DIJJ. When the circuit of the present invention is applied to, for example, an ECL interface, amplification circuits of at least two stages are required to amplify up to the MO8 level, which can rarely be reduced to 11-1 stages. A fast 7il (CL interface circuit) can be realized with low power consumption.

The circuit of the present invention can be applied not only to h:cL and TTL inter 7/8 circuits, but also to sense amplifiers that amplify read signals of memory cells such as static memories.

[Brief explanation of the drawing]

Fig. 1 is an example of a conventional amplifier circuit, Fig. 2 is a transfer characteristic of a conventional amplifier circuit, Fig. 3 is a first embodiment of the present invention, and Figs. Example, FIG. 7 shows an example of the 1+7 configuration of an amplifier that can fully control the logic threshold, FIGS. 8 to 10 show other configuration examples, FIG. 11 shows an example of the configuration of a control signal generation circuit, The figure shows an example of a configuration in which all control is performed at logical threshold 1. VDD, vss・・・・・・・・・・・・・・・
...Power supply Q1 ~ Ant, ......
・・・・・・・・・MOS transistor I, I
,~I4・・・・・・・・・・・・・・・・・・
Input signal 0.01~06.・・・・・・・・・・・・・・・
......Output signal vR,,VR,.・・・・・・
・・・・・・・・・・・・・・・Reference voltage A0
・・・・・・・・・・・・・・・・・・・・・・・・
This amplifier AH, A3, A4 HA6 HA8HAg
・・・Simulated amplifier B, ~B7 ・・・・・・・・・・・・
・・・・・・・・・・・Comparison circuit 61~G6
・・・・・・・・・・・・・・・・・・・・・Control signal generation circuit R+, & ・・・・・・・・・・・・・・・
・・・・・・・・・・・・Resistance C3~CIG・・・・
・・・・・・・・・・・・・・・・・・・・・Capacity VC+
VC+ VC+ ~ Va, ...... Control signal F ......
・・・Source follower circuit vN・・・・・・・・・・・・
・・・・・・・・・・・・16 b++82 ・・・
・・・・・・・・・・・・・・・・Input signal M+, Mt ・・・・・・・・・・・・・・・
......Power control circuit d,,d,...
・・・・・・・・・・・・・・・・・・・・・Control signal CM ・・・・・・・・・・・・・・・・・・・・・
...CMOS inverter No. 7E! ! J Figure 9 Figure 10 -] 20! ss Fig. 12 DD r 1 dl-+-IQ211 ■ L J `` 1 One-pressure layer 022r Hephui irises! I 231 1 Vss' 1 :C9 :C10 Mt CM A sajfib!, -M2

Claims (1)

[Claims] (1.1 Amplification that identifies the magnitude relationship between the human input signal and the logical threshold voltage, and outputs a binary signal expressed as a high level and a low level in accordance with the result of the discrimination. In the circuit, there is a main amplifier to which the human input signal is input by human input, a simulated amplifier to which the reference voltage is input, and a control value generator for generating the output voltage of the simulated amplifier. The amplifier circuit is configured to control the logical threshold voltage sound of the main amplifier and the simulated amplifier according to the control signal. IL power supply (b) path and CMOS inverter
Item 1. A self-mounted amplifier circuit characterized by using a circuit configured to supply the output sound of the power supply circuit to the %L@terminal of a CMOS inverter. (3) Having different conductive layers connected in series
Equipping these two field effect transistors, applying 100 degrees of human power to the gate of the field effect transistors, and applying two to an amplifier circuit that extracts an output signal from the midpoint of the series connection,
At least a circuit consisting of a source follower circuit formed using a resistor whose resistance value can be changed depending on the design number, and a capacitor connected between the input terminal and output terminal of the source follower circuit. 1 or more + J plus Mu
A human input signal to the amplifier circuit is applied to the input terminal of the source follower circuit, and the signal obtained from the output terminal of the source follower circuit is transmitted to the gate of the at least one field effect transistor connected in series. The JVI width circuit according to item 1, which is characterized by having the following features: