JPS59146380A - Digital signal processor - Google Patents

Abstract

PURPOSE:To transfer data to a memory without using any FIFO and to simplify the constitution of a discrete Fourier transforming (DFT) device by providing a data buffer area to the memory in the device and addressing the memory by a control means which uses a counter and an adder. CONSTITUTION:A signal from a data collector 1 is converted by an A/D converter 2 into a digital signal, which is applied to the DFT device 5 through an interface buffer 3. The data buffer area is provided to the memory 7 of this DFT5 and a latch 6, arithmetic processing circuit, address generator 10, and address adder 15 are connected to the memory 7. An arithmetic bus counter 13 is connected to this adder 15 through a data selector 14. This adder 15 adds a one-bit address to the bit position of an address bus 16, and when the generator 10 addresses the memory, ZM<-1> pieces of data in the buffer area are updated in every arithmetic processing cycle to process N pieces of data by the circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal processing device that receives a data string from a low-speed data acquisition device as input and performs Fourier transform processing.

Conventional configuration and its problems Conventionally, when performing real-time Fourier spectrum analysis of time-series signals converted to digital quantities, an FFT digital signal processing device with a dedicated hardware configuration using FFT (Fast Fourier Transform) as an algorithm has been used. It was often used. - As an example, it is known that the output of an ultrasonic pulse Doppler blood flow meter can be analyzed by a Fourier spectrum using an FFT digital signal processing device, and the specifications of the processing device are as shown below.

Number of input data points: 128 points Complex number irregularity Sample period: 5KHz Processing time: 2t+tSe In the example, the sample period is 5KHz, so 2 m
10 new data are sampled within the processing time of Sec, and in the next calculation, 128 data including this 1o data are used as an input data string.

FIG. 1 is an example of a block diagram of a system for processing an input data string as described above.

In the figure, 1 is an ultrasonic pulse Doppler blood flow meter and has a data sample period of 5 KHz. 2 is an A/D converter, and a time series signal converted into a digital quantity is transferred to an interface buffer 3.

2711 for interface buffer 3. 128 points of data are transferred to FIFO (first-in, first-out register) 4 in synchronization with the SeC processing time.

When data input/output of the interface buffer 3 is controlled by a microprocessor, a large processing capacity is required.

The area surrounded by broken lines is the FFT digital signal processing device. The 128 points of data temporarily stored in the FIFO 4 are transferred to the high speed memory 7 via the latch 6. 8 is an arithmetic processing circuit composed of a multiplier and an adder. 9 is a coefficient ft0M, which outputs the values of the SIN and CO3 coefficients necessary for FFT calculation.

It is a 10U address generator and generates the address of the memory 7, the address of the coefficient FtOM9, etc. Reference numeral 11 denotes a controller which controls the timing of the entire FFT digital signal processing device.O12 is a FIFO for practical use in arithmetic operations, and outputs the Fourier spectrum calculation results output at high speed in accordance with the speed of an external device.

One process of the FFT digital signal processing device 5 is 1) FI
It consists of three routines: transferring the input data string from FO4 to memory 7, 2) executing FFT in arithmetic processing circuit 8 based on the data in memory 7, and 3) transferring the calculation result to FIFO 12. The total time required for processing is one processing time. Therefore, transferring input/output data via the FIFOs 4 and 12 is useful for shortening the overall processing time.

Access time for memory 7 is 100 nSec
On the other hand, in order to process a complex input data string of N points, a memory of 2N words, that is, 12
It is known that for a complex input data sequence of 8 points, a memory of only 266 words is sufficient.

Access Time 100, which has been produced as standard in recent years.
Static RAM on the nSeC scale and tJX scale are generally MO8 ICRAMs with a capacity of about 1024 words x 4 bits (7), and if the memory 7 is configured with such an ICRAM, an extra memory area will be created.

In addition, WFTA (
In Winograd) ~ Riko Conversion Algorithm), the number of input data points is not a power of 2, and for example, 128 points F.
It is known that the value corresponding to FT is 120 points or 144 points.

For such a number of input data points, if a normal ICRAM whose number of words is a power of 2 is used, a large amount of extra memory area will be required.

Purpose of the Invention The present invention has been made in order to solve the problems of the conventional art as described above. An object of the present invention is to provide a digital signal processing device having memory address control means that enables data transfer without using memory address control.

Structure of the Invention In order to achieve this object, the present invention provides: j) Allocating a buffer area for input data in the memory in the FT processing device, and controlling memory address control means using an arithmetic pulse counter and an address adder. It consists of

Description of examples Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a data acquisition device such as an ultrasonic pulse Doppler blood flow meter, and the sampling period is 5 KHz. 2 is an A/D converter, 3 is an interface buffer, and the area surrounded by a broken line 5 is a DFT digital signal processing device. D
The arithmetic algorithm of the FT digital signal processing device 5 is the above-mentioned WFTA, which processes N-120 points of complex data into 1
, 6 m5ec. Therefore, 8 (-2M-1M-4) pieces of complex data are updated in each arithmetic processing cycle.

In the memory 7, an area for input data and an area for executing DFT calculations are allocated separately, so it is possible to transfer data to and from the interface buffer 3 without waiting for the completion of the calculation, which reduces the transfer speed. is approximately equal to the sampling period of the data acquisition device 1 and can be made slow. The memory 7 has addresses from ○ to 1023 and is composed of standard IC static RAM. Addresses 0 to 255 are assigned to the 120-point complex manual data string and used as the input data buffer area. 6 is lunch,
8 is an arithmetic processing unit, and 9 is a coefficient ROM which outputs the value of a multiplication coefficient necessary for WFTA calculation. 10 is an address generator which generates the address of the memory γ and the address of the coefficient RΦM9. A controller 11 controls the timing of the entire DFT processing device and requests data to the interface buffer 3. The interface buffer 3 activates its output in response to a data request, transfers the data to the latch 6, and starts preparing to send data corresponding to the next data request. The address generator 10 and controller 11 are collectively called a fixed instruction generation section. 12 is an arithmetic path counter of 013td-L=4 bits which is a FIFO for arithmetic operation, and counts in synchronization with the arithmetic processing cycle. Reference numeral 14 denotes a data selector, and when the address generator 10 generates an address corresponding to the input data banoff 7 area of the memory 7 in response to an instruction from the controller 11, it outputs the 4-bit data a of the counter 13 and accesses other areas. In this case, zero data b is selected. 15 is a 4-bit address adder, which combines the 4-bit output C of the data selector 14 and the hit position M−M+L− of the address bus 16 of the address generator 10.
1, i.e. address bus portion 1 of bit positions "4-7"
Add 7 0 However, make the most significant bit of the counter 13 correspond to the bit position °゛7''' of the address bus ○The address bus 16 is composed of 10 pinpoints corresponding to the 1024 word addresses of the memory γ, its bit position '0'
The portion 22 of the address bus consisting of .about.3'' and 8.about.9'' is directly connected to the address input of the memory 7. The address adder 15 inputs the 4-bit output d, ignoring the carry output, to the address input bit position pars 4 to 4 of the address input of the memory 7.
Connect to γ′′.

Next, when the address generator 10 generates addresses O to 255 in the input data buffer area of the memory 7, the address input of the memory 7 is changed and/or updated every calculation cycle by the address adder 15. It is shown in Table 1.

However, arithmetic processing cycle number; NCYOLE arithmetic bus counter value; NPASS Address of memory 7 corresponding to read address bus 0 to 239 of address generator 10 Write address output 240 to 25 of address generator 10
The address of memory 7 corresponding to number 6 is NW.

According to Table 1, address 240 at operation cycle NCYOLE=O
The 8 complex data written in ~266 are the following NCYC
It is read with LE=1 and new eight complex data are written to addresses Q to 15.

Calculated pulse counter value NPASS with NCYCLE-16
=o, and the address value returns to the state of NCYOLE-〇. In this way, memory address control can be performed corresponding to each calculation cycle.

That is, according to this embodiment, when updating 8 (=2, M=4) pieces of data for N, -120 complex data every cycle of arithmetic processing, the address bus Insert the L bit and door address adder 15 into the hint position M-M+L-1 of 16, and at the predetermined timing, L pinot! - It can be seen that the addition deviation of the calculation pulse counter output is good.

However, the Lt7) value is N (= 120) = 2M
-1×=8×K, from the relationship K(=15)≦2L, L
= 4 can be obtained. 4-bit counter, data selector 1
Standard ICs for each of the 4° adders 16 are commercially available, and the above-mentioned memory address control is possible with a simple configuration.

Note that for N = 120 actual data, 8
(=2M, M=3) also when updating data of N
(=120)=2MxK=8xK, L=4 is obtained from −15×2L, and address bus bit position M −M
It is good to insert the 4-bit address adder 15 at +L-1, that is, "3 to 6".

As described above, in this embodiment, the input data Banonoa area is allocated to the high-speed memory 7 in the DET processing device 5, and the transfer from the data collection device 5 is performed at approximately equal intervals within the J:DFT processing time to reduce the speed. 1, and this speed is on the order of the Zangle period of the data acquisition device 1. Therefore, the role of the interface buffer 3 is to input low-speed data from the data collection device 1 and to respond to low-speed data transfer requests from the DFT processing device 6, and to provide input data to the FI for input data.
FO also became disrespectful.

Therefore, in the memory 7 of the DFT processing device 5, a problem arises in that the write address of the transferred data and the address of the entire input data string must be shifted every calculation cycle.
This problem can be solved by a simple memory address control means using 3 and an address adder 15.

As described in detail, the present invention makes it possible to directly transfer data from a low-speed data acquisition device to the input data bath area of a high-speed memory for calculation using a memory address control means with a simple configuration. This eliminates the need for data transfer rate conversion means such as FIFO in the data input section. Particularly when the extra area of the calculation memory is used as the input data/kunofa area, the effect of saving parts is significant.

Moreover, the number of input data transfers is small and the transfer speed is low, which reduces the workload of the interface buffer between the data acquisition device and the digital signal processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional DFE digital signal processing device, and FIG. 2 is a block diagram showing an embodiment of the digital signal processing device of the present invention. 1...Data collection device, 3...Interface buffer, 4.12...FIFO, 6...
・DFT processing device, 6...Latch, 7...
Memo') -18... Arithmetic processing circuit, 9...
... Coefficient ROM, 10... Address generator, 11.
...Controller, 13...Calculation path counter, 14
...Data selector, 16...Address adder, 16. River address bus. Name of agent: Patent attorney Toshio Nakao (1st person)
figure! ? 3 /// L-, -J Figure 2 / z3 /// L-11-----J 535

Claims (1)

[Claims] A fixed instruction generation section, a part of memory, an operation path counter having a clock input synchronized with one operation processing cycle, and bit positions M to M+L-1 of an address bus connected from the fixed instruction generation section to the part of memory. an address adder that adds the L-pinto address calculation data to the L-pinto; and updating 2 (I=O: real data, I=1: complex data) pieces of data in the human data buffer 7 area every one arithmetic processing cycle, and updating N( -2M-iXK,
A digital signal processing device that processes K<2L) input data strings.