JPS59145165A - Driving device for heat-sensitive type recording head - Google Patents

Abstract

PURPOSE:To markedly reduce recording time, by a method wherein switching element driving signals for simultaneously opening or closing current-passing circuits for all heating elements in each block are sequentially made to rise with a time interval of DELTAT, and are made to fall when a power source current exceeds a predetermined value. CONSTITUTION:With a transfer completion pulse 12 supplied, image information stored in a shift register 11 is latched by a latch circuit 14, only those of a plurality of elements 19 in a switching circuit 16 which correspond to picture elements are turned ON, and transistors 241-246 are turned ON, upon which corresponding heating elements 18 are operated to generate heat. The transistors 241-246 are provided for each block of the group of the heating elements 18, a scanning signal of a timing-generating circuit 33 causes a counter 29 to count basic clocks 34, driving signals D1-D6 of close time T are sequentially raised form decoders 31, 32 with a time interval of DELTAT<T, and when a power source current 20 provided by the turned-ON heating elements 18 exceeds a predetermined value, the driving signals are made to fall, and are subsequently raised after a predetermined period of time. Accordingly, recording time can be markedly reduced without increasing the capacity of the power source.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thermal recording head drive device that performs recording by selectively energizing a large number of heating elements.

Conventional Structure and Problems Therein FIG. 1 is a block diagram showing an embodiment of a thermal recording head 1 driving device employed in a conventional thermal recording facsimile machine.

Reference numeral 1 denotes a thermal recording head, which has mXn heating elements 2. 3 is a shift register, and 4 is a latch ROM, each of which has a capacity capable of storing image information for one line. 5 is a switching circuit, and each heating element 2
Open/close the energized path between the and the power supply. The heat generating elements 2 are divided into n blocks each having m elements, and n transistors 2 to 7n are provided in association with each block. The heating elements 2 in each block are collectively connected to ground via the corresponding transistors 71 to 7n. 8 is a transistor 71
This is a drive circuit that generates drive signals 81 to Sn of ~7n.

In operation, when one line of image information is accumulated in the shift register 3, the image information from the shift register 3 is latched into the latch circuit 4 all at once. The switching circuit 5 closes the energization path between the heating element 2 to be energized and the power source 6 according to the image information in the latch circuit 4 . Therefore, if the transistors 71 to 7n are turned on, the heating element 2 to be energized
The energizing paths are closed and energized, and these heating elements 2 generate heat.

Now, conventionally, the drive circuit 8 generally includes transistors 71 to 71.
Drive signals S1 to s are set so that the on periods of 7n do not overlap.
n is generated in the sequence shown in the waveform diagram of FIG. Therefore, each of the drive signals 81 to Sn has an on time 'It. Then, the time required to record one line of image information is nto.

Problems with such conventional devices will be explained next.

To shorten the recording time, either the number of blocks (n) is eliminated, or the energization time (t) per block is reduced. However, due to the thermal response delay of the thermal recording head 1, the contact thermal resistance between it and the recording paper, and the supply voltage of the power source 6, etc. is fixed to a certain length, so there is no other way than to reduce the number of blocks n (C. Therefore, the number of blocks n f should be determined using the minimum transmission time of 1 line image information as a guide. However, this minimum transmission time When it is decided by, the number of blocks n
becomes relatively small, the number of heating elements per block increases, and the current flowing from the power supply 7 increases (for example, when n = i, it may reach several tens of amperes), so the power supply 70 becomes larger. , leading to an increase in equipment costs. Therefore, in conventional facsimile machines, in order to satisfy conditions such as cost and size of the device, the number of flocks n is set much higher than the value determined by the minimum transmission time.
This has had to be dealt with at the expense of lowering the recording speed, which is undesirable from the standpoint of facsimile machine functionality.

As described above, the thermal recording head drive device described above has a drawback in that it is difficult to increase the recording speed sufficiently in terms of power supply capacity.

In addition to the examples described above, a technique has also been proposed in which the number of heat generating elements to be driven at one time is dynamically changed according to the number of black pixels included in the image information to be recorded. In other words, among the heating elements, current actually flows only through those corresponding to black pixels, so if there are few black pixels included in the image information to be recorded, it is necessary to drive many heating elements at once. It is something. Although this technique can certainly improve the recording speed, it has another drawback in that it complicates the counting of black pixels and the means for controlling the drive of the heat generating elements based on the counting results.

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks.
It is an object of the present invention to provide a thermal recording head driving device that shortens recording time without using a complicated configuration.

Structure of the Invention The present invention sequentially raises a drive signal for driving the switching means for opening and closing the current-carrying paths of all the heating elements for each block at intervals of time ΔT, and continuously drives the switching means. If the power supply current exceeds a predetermined value due to the rise of the signal, the drive signal is immediately turned down and the switching means restarts the rise of the drive signal after a certain period of time, and the setting of ΔT is controlled by the switching means. The relationship is ΔT(T) with respect to the normal closing time T.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing a thermal recording head driving device according to an embodiment of the present invention.

In the figure, numeral 11 is a shift register for accumulating one line of image information, and it sequentially receives image information transferred to input terminal 13 at the timing of pixel transfer lock input to input terminal 12. Shock and shift to the right. 14
is a latch circuit for latching image information for one line. When the transfer of image information for one line is completed, a transfer end pulse is input to the input terminal 15, but this pulse causes the latch circuit 14 to latch all the image information in the shift register 11, and transfer it to the switching circuit 16. Output.

A thermal recording head 17 has a large number of heating elements 18. The switching circuit 16 is composed of a large number of switching elements corresponding to each heating element 18. In this example, a transistor 19 is provided, and one end (the upper end in the figure) of each heating element 18 is connected to the power supply line 2o through each transistor 19.
connected to.

Each of the transistors 19 is turned on and off by the output of the corresponding bit of the latch circuit 14. The power supply line 20 is connected to the positive terminal of a DC power supply 22 via a resistor 21 for overcurrent detection. The negative electrode of this DC power supply 22 is grounded. The resistance value of the resistor 21 is sufficiently small;
For example, 0.020 is selected. An overcurrent detection circuit 23 detects the current value of the power supply line 2o from the voltage drop caused by the resistor 21, and turns on the overcurrent signal ae while the current value exceeds a predetermined value Imax f.

The heating elements 18 are divided into a plurality of blocks each having a predetermined number, for example six blocks. 241 to 246 are switching elements associated with each block of the heating elements 18, which are transistors in this example.

One end (lower end in the figure) of the heating elements 18 in each block is collectively grounded via the corresponding transistors 241 to 246.

Reference numeral 24 denotes a drive circuit 1 that turns on and drives the transistors 241 to 246, and includes ORKETs 261 to 266 associated with the transistors 241 to 246 and a pulse generation circuit 2.
7. 276 and the control circuit 28.

Drive signals D1-D6 for turning on transistors 241-246 are sent from OR gates 261-266.

The control circuit 28 has a counter 29 . 30, decoders 31 and 32, and a timing generation circuit 33. The input terminal 15 of the transfer end pulse is connected to the counter 2.
Clear human power CLR of 9: Connected. The basic clock input terminal 34 is connected to the count-up side clock input UP of the counter 29 through the AND gate 30, which is controlled by the scanning signal line f sent from the timing generation circuit 33.
is combined with A down-count clock input DN of the counter 29 is connected to a down-clock line q output from the timing generation circuit 33 . Output QA of counter 29
, QB, and Qc are connected to decoders 31 and 32 and a timing generation circuit 33. The enable line q from the timing generation circuit 33 is connected to the enable input ENB of the decoders 31 and 32.

h are connected respectively. The decoder 31 has six outputs, each of which has an OR circuit 26. ~266 corresponding one input. The decoder 32 also has six outputs, each of which is connected to the pulse generation circuits 271 to 2.
76 corresponding one input. Decoder 31
．． 32, pulse generation circuits 271 to 276 decode the value (QA-QC) of the counter 29 only while the enable manual ENB is on, and selectively turn on only the output corresponding to the four counter values. is triggered by turning on, and sends out a pulse of constant width. The outputs of these pulse generation circuits 271 to 276 are output from OR gates 261 to 276.
266 corresponding one input. The overcurrent signal line e is connected to a timing generation circuit 33.

Next, the operation of this device will be explained.

When the transfer of image information for one line is completed and a transfer end pulse is sent to the input terminal 12, the image information accumulated in the shift register 11 is latched in the latch circuit 14, and at the same time, the counter 29 is cleared.

Of the many transistors 19 of the switching circuit 16, only those corresponding to the black pixels in the image information latched by the latch circuit 14 are turned on. The heating element 18 connected to this turned-on transistor 19 is energized and generates heat when the transistors 241 to 246 to which it is connected are turned on.

On the other hand, when the timing generation circuit 33 detects the reset of the counter 29, it turns on the scanning signal line f.

As a result, the basic clock input to the input terminal 34 passes through the AND gate 30 and is supplied to the clock input UP of the counter 29, and the counter 29 starts counting up.

1st output of decoder 31.3', 2 (heating element 18
When the counter 29 counts up to a value that turns off the first block (corresponding to the first block of send it to The same pulse is applied to the transistor 241 as the drive signal D1.
In addition, in order to turn on the transistor, only those corresponding to the black pixels among the heating elements 18 in the first block are energized, and a current proportional to the number of energized heating elements flows through the power supply line 2Q. This current value is the specified value m
If ax is not exceeded, the timing generation/generation circuit 33 sends out a minute width pulse to the other enable line at the same time as the enable line q is turned on, and causes the first output of the decoder 32 to send out the pulse. The pulse generating circuit 27 according to the same pulse
1 is triggered and outputs a constant width pulse. This pulse is applied as a drive signal D1 to transistor 261, and transistor 26. Turn on. Therefore, the transistor 1241 is turned on for the total time T of the output pulse width of the decoder 31 and the output pulse width of the pulse generation circuit 271.

When the counter 29 counts up to a value that turns on the second output of the decoder 31, the timing generation circuit 33 sends out the enable line qK minute width pulse.

The sending time of this minute width pulse is delayed by a time ΔT (however, ΔT(T)) from the sending time of the same pulse immediately before, and the same time Δt is determined by the cycle of the basic clock input to the input terminal 34. Decoder 31 sends a pulse with the same width as the pulse on the enable line q to the second output.The pulse becomes the drive signal D2 and turns on the transistor 242.At this time, if the current signal line e is not turned on, the timing The generation circuit 33 sends a minute width pulse to the enable line and causes the second output of the decoder 320 to send a pulse of the same width.
A positive signal is generated and applied to the transistor 242,
The transistor remains on.

If the overcurrent signal line e is turned on immediately after a pulse is output from the second output of the decoder 31, the timing generation circuit 33 stops sending pulses to the enable line, turns off the scanning signal line fi, and then One pulse is issued to the down clock line q to cause the counter 29 to count down by one. Then, the pulse generating circuit 27. Around the time when the output of is turned off, the timing generation circuit 33 turns on the scanning signal line f again, causing the counter 29 to restart counting up.

This operation is repeated, and finally the pulse generation circuit 27
When the trigger No. 6 is completed, the timing generation circuit 33 turns off the scanning signal line f, stops the counter 29, and completes the timing generation operation for one line.

The time required for driving one line by this apparatus varies depending on whether there are many or few black pixels included in the image information to be recorded. This will be explained with reference to FIGS. 4 and 5.

FIG. 4 is a waveform diagram of the drive signals D1 to D6, the power supply current, and the signals on the overcurrent signal line e when recording image information with a relatively large number of black pixels.

1st. Drive signal DD1 corresponding to the second block! 2 are started up in sequence, and then when the drive signal corresponding to the third block is started up, the power supply voltage reaches the predetermined value Ima.
Since the overcurrent signal line e is turned on beyond x, the drive signal D3 is immediately lowered.

(When the number of blocks is set to a large number, it is of course possible to maintain D3 at a high level with a margin for the overcurrent value.) Immediately after the fall of the drive signal D2, the drive signal D3 is raised again, Next, the drive signal D4 corresponding to the fourth block
When the overcurrent signal line e is turned on,
The drive signal D4 is immediately lowered. Drive signal D3
Immediately after the fall of the drive signal D4, the drive signal D4 rises again, followed by the fifth drive signal D4. Drive signal D5 corresponding to the 6th block
．． D6 is started up one after another.

In this case, the time required to drive all blocks (recording time for one line) is about 3T, which is about half of the time required to drive each block alternately for a time T.

FIG. 6 is a similar waveform diagram when recording image information with few black pixels. In this case, since the overcurrent signal line e is not turned on when driving any block, the drive signals D1 to D6 are sequentially raised at intervals of time ΔT, so the drive time (recording time) is the shortest, about 2T. This is about one-third of the time when each block is driven alternately.

In this way, the fewer black pixels included in the image information, the shorter the driving time (recording time) becomes. However, in facsimile communication, character images are overwhelmingly handled, and The ratio of black pixels is generally less than ten percent. Therefore, according to the present device, the driving time (recording time) can be significantly shortened compared to the conventional device which uses a power source with the same or lower current capacity and drives each block alternately.

In addition, this device is configured to perform drive control according to the number of black pixels in the image information by slightly shifting the drive start time of each block and monitoring whether the power supply current exceeds a predetermined value. The device configuration can be simplified compared to the conventional device which performs similar drive control by directly counting the number of black pixels in the image information.

Note that the configuration of the switching circuit 16 may be changed as appropriate. The number of blocks of the heating element 18 may also be changed as necessary. The transistors 241 to 246 may also be replaced with other switching elements. The overcurrent detection resistor 21 may be omitted and a Hall element or the like may be used to detect the overcurrent. Each output of the decoder 31 and the pulse generation circuit 27
If the outputs of 1 to 27b can be wired-ORed, the OR gates 261 to 266 may be omitted. The configuration of the control circuit 28 may also be changed as appropriate. For example, the decoder 32 may be omitted, the output of the decoder 31 may be coupled to the inputs of the pulse generation circuits 271 to 276 via gates, and the gates may be controlled by the timing generation circuit 33. 4. The switching means is not limited to the transistors used in the embodiment, but is also a latch circuit.The reason is that the output of the switching circuit is input to the input terminal of ANDKATE for each bit, and this is divided into a plurality of blocks, and OR gates 271 to 276 are used. Of course, the same effect can be obtained even if the output of each block is made to correspond to each block and inputted to one other input terminal of a plurality of AND gates.

Effects of the Invention As is clear from the above description, the present invention sequentially generates five drive signals at intervals of time ΔT to drive the switching means for opening and closing the energizing paths of all heat generating elements at once for each lock. If the power supply current exceeds a predetermined value due to the successive rises of one drive signal of the switching means, the drive signal is immediately stopped and the drive signal is restarted from the switching means after a certain period of time. Let, Δ
T is ΔT with respect to the normal closing time T of the switching element.
It is set so that the relationship ``<T'' is established, and it has the excellent effect that the recording time can be significantly shortened at low cost with a simple circuit configuration without increasing the power supply capacity.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of a conventional thermal recording head driving device, and Fig. 2 shows the block diagram of the conventional device.

Claims (2)

[Claims] (1) Thermal recording--A switching circuit is provided to open and close the energizing path of each heating element made of rad clay, and a switching circuit is provided corresponding to each block that is a collection of a plurality of heating elements. A plurality of switching means open and close the energized paths of all heat generating elements included in one block to be closed at once, and each of these switching means is kept in a closed state for a time T. an overcurrent detection circuit that sends out an overcurrent signal when the sum of currents flowing through all the current-carrying paths of the heating element exceeds a predetermined value;
The drive circuit transmits a drive signal for causing each of the switching means to close MVC in a certain order over a period of time Δ.
T' (7C, ΔT (T)), and when the overcurrent signal is sent out at the time of the rise of the drive signal to a certain switching means, the drive signal is immediately stopped, or The thermal recording head drive device is configured such that the switching means restarts the rise of the drive signal after a certain period of time has elapsed without stopping the drive signal. (2) The drive circuit is provided with a control circuit having a plurality of first and second outputs associated with each switching means, and a signal outputted from the corresponding second output. and a plurality of pulse generation circuits that send out pulses of a constant width when triggered by the control circuit. If an overcurrent signal is not sent at the time of sending, a sequence is executed to immediately send a signal to the second output corresponding to the first output that sent the same pulse, and a pulse is sent to the certain first output. If an overcurrent signal is sent at the time, the signal to the second output corresponding to the first output is not sent, and after a certain period of time has elapsed, the first output and the corresponding second output are sent. The sequence is then restarted, and an OR signal of the pulses respectively sent from the corresponding first output and the pulse generation circuit is supplied to each of the switching means as a drive signal. The thermal recording head drive device according to item 1.