JPS59143477A - Fly-back transformer - Google Patents

Fly-back transformer

Info

Publication number
JPS59143477A
JPS59143477A JP58017251A JP1725183A JPS59143477A JP S59143477 A JPS59143477 A JP S59143477A JP 58017251 A JP58017251 A JP 58017251A JP 1725183 A JP1725183 A JP 1725183A JP S59143477 A JPS59143477 A JP S59143477A
Authority
JP
Japan
Prior art keywords
voltage
winding
terminal
windings
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58017251A
Other languages
Japanese (ja)
Other versions
JPH0221716B2 (en
Inventor
Hideo Hishijo
菱城 秀夫
Yukio Kamiyama
幸夫 神山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Nippon Victor KK
Original Assignee
Victor Company of Japan Ltd
Nippon Victor KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd, Nippon Victor KK filed Critical Victor Company of Japan Ltd
Priority to JP58017251A priority Critical patent/JPS59143477A/en
Publication of JPS59143477A publication Critical patent/JPS59143477A/en
Publication of JPH0221716B2 publication Critical patent/JPH0221716B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/18Generation of supply voltages, in combination with electron beam deflecting
    • H04N3/19Arrangements or assemblies in supply circuits for the purpose of withstanding high voltages

Abstract

PURPOSE:To reduce the number of winding times of a winding and to reduce the insulation of the winding and the reverse voltage resistance of rectifier elements by providing inductance elements connected with the rectifier elements in series between the terminals of the primary and/or tertiary windings in a fly-back transformer which take out a positive polarity pulses. CONSTITUTION:A power source is supplied to the terminal 2 of the primary windings N11, N12 in the fly-back transformer 1 and voltage rectified by a diode D2 is smoothed by a capacitor C1 and supplied from a terminal 7 to a video output circuit. The voltage of the secondary windings N21-N24 is rectified and supplied to a CRT and the voltage of the tertiary windings N31-N33 is rectified by diodes D1, D6, smoothed by capacitors C2, C3 and supplied from terminals 5, 6, 13 to circuits such as the CRT and a tuner. The indactance elements L1, L2 connected with the diodes D2, D1 in series are provided between the terminals of the primary windings N11, N12 and/or the tertiary winding N33 in the transformer 1 which takes out positive polarity pulses and the smoothing capacitors C1, C3 and the values of the indactances L1, L2 are set up so that the high voltage of the windings N21-N24 is increased.

Description

【発明の詳細な説明】 本発明はフライバックトランスに係り、正極性のパルス
電圧を取り出1m子と平滑素子との間に整流素子とめ列
にインダクタンス素子を設けることにJ:り高圧負荷変
動率が改善され効率の改善されるフライバックトランス
を提供することを目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flyback transformer, in which an inductance element is provided in a rectifying element stopper row between a 1 m element and a smoothing element to extract a pulse voltage of positive polarity. It is an object of the present invention to provide a flyback transformer with improved rate and efficiency.

最近のプレビジョン受像機においては、そのフライバッ
クトランスを受像管に陽極電圧を供給する機能の伯に、
上記陽極電圧を発生される高圧巻線以外の巻線より取り
出したパルス電圧を整流してヂューナ等の小信号回路、
映像出力回路9垂直偏向出力回路等の主要回路に電力を
供給する機能をイ」加して使用し、コスト低減を図った
しのが多い。第1図、第2図は夫々従来のフライバック
トランスの各個を示す。
In recent pre-vision receivers, the flyback transformer is used to supply the anode voltage to the picture tube.
A small signal circuit such as a tuner rectifies the pulse voltage extracted from a winding other than the high voltage winding that generates the above anode voltage.
Video output circuit 9 In many cases, a function for supplying power to main circuits such as a vertical deflection output circuit is added to reduce costs. FIGS. 1 and 2 each show a conventional flyback transformer.

第1図において、1はフライバックトランスであり、そ
の1次巻線には端子2J:り電源が供給されている。こ
のフライバック1ヘランスの2次巻線に接続された端子
3からは受像管の陽極電圧となる高圧出力電圧が取り出
され、端子4からは受像管のフォーカス電圧が取り出さ
れる。また、3次巻線の端子5からは正極性の帰線パル
ス電圧を整流した垂直偏向出力回路の電源が取り出され
、端子6からは負極性の帰線パルス電圧を整流したヂュ
ーナ、映像中間周波増幅回路等の小信号回路の電源が取
り出される。更に、1次巻線の端子7からは正極性の帰
線パルス電圧を整流した映像出力回路の電源が取り出さ
れる。また、第2図において、8はフライバックトラン
スであり、端子2へ・4、’6.7は第1図示のものと
同一ひあり、端子6.7夫々より小信号回路の電源、映
像出力回路の電源が取り出される。このフライバックト
ランス8からは垂直偏向出力回路の電源は取り出されて
おらず、これは例えば7レビジ一]ン受像機の電源トラ
・ンスより取り出される。
In FIG. 1, reference numeral 1 denotes a flyback transformer, the primary winding of which is supplied with power through terminal 2J. A high voltage output voltage serving as the anode voltage of the picture tube is taken out from a terminal 3 connected to the secondary winding of the flyback 1 Herance, and a focus voltage of the picture tube is taken out from a terminal 4. In addition, from terminal 5 of the tertiary winding, a power source for a vertical deflection output circuit that rectifies the positive retrace pulse voltage is taken out, and from terminal 6, a dyuna that rectifies the negative retrace pulse voltage, and a video intermediate frequency Power for small signal circuits such as amplifier circuits is taken out. Further, from the terminal 7 of the primary winding, a power source for a video output circuit obtained by rectifying the positive retrace pulse voltage is taken out. In addition, in Figure 2, 8 is a flyback transformer, terminals 2, 4, and 6.7 are the same as those shown in Figure 1, and terminals 6 and 7 are used for power supply and video output of the small signal circuit, respectively. The circuit is powered. The power for the vertical deflection output circuit is not taken out from this flyback transformer 8, but is taken out from the power transformer of, for example, a 7-channel television receiver.

ここで、比較的低い電圧で使用される小信号回路の電源
は第3図に示す如き負極性のパルス電圧を発生させ、導
通期間の長い走査期間部の正極性部分Vsを整流して取
り出す。また、比較的高い電力の必要な映像出力回路、
垂直偏向出力回路等の電源は第4図に示す如き正極性の
パルス電圧を発生させ、その帰線部分の正極性部分Vp
を整流して取り出している。しかし、正極性のパルス電
圧を整流する場合には、例えば抵抗R1が無いとき第1
図示の端子5に接続されるダイオードDIのアノードに
は第5図の実線AOに示す如き電圧が印加されると共に
、実線Boに示す如き電流が流れる。このようにピーク
電流は相当に大きいため帰線期間内の負荷が大となり、
同様に帰線期間の正極性パルスを利用している端子3よ
りの高圧出力電圧の高圧負荷変動率が大幅に悪化する。
Here, the power supply of the small signal circuit used at a relatively low voltage generates a negative pulse voltage as shown in FIG. 3, and rectifies and extracts the positive polarity portion Vs of the scanning period portion having a long conduction period. In addition, video output circuits that require relatively high power,
The power supply for the vertical deflection output circuit etc. generates a positive pulse voltage as shown in FIG.
is rectified and extracted. However, when rectifying a positive pulse voltage, for example, when there is no resistor R1, the first
A voltage as shown by the solid line AO in FIG. 5 is applied to the anode of the diode DI connected to the illustrated terminal 5, and a current as shown by the solid line Bo flows. In this way, the peak current is quite large, so the load during the retrace period is large,
Similarly, the high-voltage load fluctuation rate of the high-voltage output voltage from the terminal 3, which utilizes the positive pulse during the retrace period, is significantly worsened.

このため従来はダイオードD1と直列に抵抗R1を挿入
して一ヒ記ピーク電流を抑制している。
For this reason, conventionally, a resistor R1 is inserted in series with the diode D1 to suppress the peak current.

この端子3にり出ノ〕される高圧出力電圧が0111A
のときの高圧出力電圧をE HT oとし、高圧負荷電
流が1  mAのときの高圧出力電圧を[E l−I 
T + とじ、高圧負荷電流をOn+Aから1mAまで
変化させたときの高圧負荷変動率ηをとし0表わり°。
The high voltage output voltage from this terminal 3 is 0111A.
The high voltage output voltage when the high voltage load current is 1 mA is set as E HTo, and the high voltage output voltage when the high voltage load current is 1 mA is [E l-I
When the high voltage load current is changed from On+A to 1 mA, the high voltage load fluctuation rate η is expressed as 0°.

ここで、抵抗R1の抵抗値を増加させるど、高圧出力電
圧E t−l T +は第6図(Δ)の破線■aに示す
如く低下し、高圧負荷変動率ηは第6図(B)の破線■
aに示ず如く僅かに改善される。また、垂直偏向出ツノ
回路へ供給する電源電圧(端−子5の電圧)は第6図(
C)の破線11aに承り如く低下し、高圧負荷電流1n
1Δのとき端子2よりフライバックトランス1に流入す
る電流は第6図(D)の破線IVaに示す如く低下し、
史に高圧負荷電流を−OmAから11Il八に変化さμ
IC際の端子5の電j丁変動は第6図([三)の破線V
aに示す如く上昇した後低下づる。なお第6図(Δ)〜
(D)における横軸は第6図(0)、(E)の下部に承
りものと同一である。このように抵抗R1を人とすると
高圧出力電圧及び端子5の電圧の低下をまねさ、その割
には高圧負荷変動率の改善が少ないという欠点があった
Here, as the resistance value of resistor R1 is increased, the high-voltage output voltage E t-l T + decreases as shown by the broken line ■a in FIG. 6 (Δ), and the high-voltage load fluctuation rate η decreases as shown in FIG. ) dashed line ■
As shown in a, there is a slight improvement. In addition, the power supply voltage (voltage at terminal 5) supplied to the vertical deflection output horn circuit is shown in Figure 6 (
The high voltage load current 1n decreases as expected on the broken line 11a of C).
When 1Δ, the current flowing into the flyback transformer 1 from the terminal 2 decreases as shown by the broken line IVa in FIG. 6(D),
Historically, the high voltage load current was changed from -OmA to 11Il8 μ
The power fluctuation of terminal 5 at the time of IC is shown by the broken line V in Figure 6 ([3)]
As shown in a, it rises and then falls. In addition, Fig. 6 (Δ) ~
The horizontal axis in (D) is the same as that shown at the bottom of FIGS. 6(0) and (E). In this way, if the resistor R1 is replaced by a resistor R1, the high voltage output voltage and the voltage at the terminal 5 will decrease, and the improvement in the high voltage load fluctuation rate will be relatively small.

同様に正極性パルスを利用している映像出力回路の電源
を取り出す回路につい−Cも抵抗R2が挿入される。第
2図において、抵抗R2の値を増加さUると、高圧出力
電圧FHT+、高圧負荷変動をη、高圧負荷電流をOm
Aから1mAに変化さけた際の端子7の電圧変動、端子
7の電圧夫々は第7図(△)〜(D)の破線Vla−I
Xaに示す如く変化する。なお、第7図(A)〜<D)
における横軸は第7図(D>の下部に示づものと同一で
ある。これらに示される如く抵抗R2を人とすると高圧
出力電圧及び端子7の電圧が低下し、高圧負荷電流変動
による端子7の電圧変動が人となり、イの割には高圧負
荷変動率が改善されないという欠点があ゛つだ。
Similarly, a resistor R2 is inserted in the circuit for taking out the power of the video output circuit which uses positive polarity pulses. In Figure 2, when the value of resistor R2 is increased, the high voltage output voltage FHT+, the high voltage load fluctuation is η, and the high voltage load current is Om.
The voltage fluctuation at terminal 7 when changing from A to 1 mA, and the voltage at terminal 7, respectively, are shown by the broken lines Vla-I in Fig. 7 (△) to (D).
It changes as shown in Xa. In addition, Fig. 7 (A) to <D)
The horizontal axis in is the same as that shown at the bottom of Fig. 7 (D>).As shown in these figures, if the resistor R2 is set to a value, the high voltage output voltage and the voltage at the terminal 7 decrease, and the terminal voltage due to high voltage load current fluctuations decreases. It has many drawbacks, such as the voltage fluctuations of 7 and the high voltage load fluctuation rate not being improved compared to A.

このため、高級機のように高圧負荷変動率を小さくする
必要がある場合、例えばフライバックトランス1より負
極性のパルス電圧を発生されてこれを整流し゛(垂直偏
向出力回路に供給するが、この場合は巻線の巻回数が正
極性のパルスを用いた場合の8倍程度となり、帰線期間
内のパルス電圧も818程度高くなるので巻線の絶縁及
び整流用ダィA−ドの逆耐圧を高くけねばならず二]マ
ドが高くなるという欠点があった。
Therefore, when it is necessary to reduce the high-voltage load fluctuation rate such as in a high-end machine, for example, a negative pulse voltage is generated from the flyback transformer 1 and rectified (supplied to the vertical deflection output circuit). In this case, the number of turns of the winding will be about 8 times that of when using positive polarity pulses, and the pulse voltage during the retrace period will also be about 818 times higher, so the insulation of the winding and the reverse withstand voltage of the rectifier diode A will be There was a drawback that the 2] must be raised high.

本発明は上記の欠点を除去したちのであり、第8図以下
と共にその各実施例に゛つぎ説明−りる。
The present invention eliminates the above-mentioned drawbacks and will now be described in conjunction with FIGS.

第8図は本発明になるフライバック1〜ランスの第1実
施例の回路図を示り一0同図中、第1図と同一部分には
同一符号を(qす。第8図中、10は水平ドライブ1〜
ランスであり、11は水平出力トランジスタである。こ
の水平出力トランジスタ11のコレクタはフライバック
トランス1の1次巻線N +2の一端に接続されている
。フライバック1〜レンス1は1次巻線N+1.NI2
.2次巻線N21へ・N271.3次巻線N 31〜N
 33を有し−(いる。1次巻線N uの一端は9i;
子2に接続されて電源を供給されており、1次巻線Nl
+、N+2を水平偏向パ1ルスが流れるとき生ずる正極
性のパルス電圧は適当な比率で分割された1次巻線N−
,u 、’ N +2の中間タップより取り出され抵抗
R2を通った後ダイA−ドD2で整流されコンデンサC
1で平滑されて端子7より受像管の陰t4を駆動する映
像出力回路の電源として出力される。2次巻線N2+の
一端は端子12を介して自動ビーム電流制限回路へ接続
されてあり、2次巻線N2+とN22の間、N23とN
24の間には整流用ダイオードD3.D1+を介して接
続され、2次巻線N 24は整流用ダイオードD5及び
受像管の管内放電による衝撃保護用の抵抗R3を介して
端子3に接続され、これらの2次巻線に発条トシた正極
性のパルス電圧が整流されこの端子3より受像管の陽極
電圧として出力される。これと共に適当な化率で分割さ
れた2次巻線N22.N23の中間タップより取り出さ
れた電圧は可変抵抗V[く1を介して端子4より受像管
の一ノオーカス電圧としC出力される。
FIG. 8 shows a circuit diagram of a first embodiment of the flyback 1 to lance according to the present invention. In the same figure, the same parts as in FIG. 10 is horizontal drive 1~
11 is a horizontal output transistor. The collector of this horizontal output transistor 11 is connected to one end of the primary winding N+2 of the flyback transformer 1. Flyback 1 to Lens 1 are primary windings N+1. NI2
.. To secondary winding N21/N271.Tertiary winding N31~N
33. One end of the primary winding N u is 9i;
It is connected to child 2 and is supplied with power, and the primary winding Nl
The positive pulse voltage generated when a horizontal deflection pulse flows through + and N+2 is applied to the primary winding N-, which is divided at an appropriate ratio.
, u, ' N +2 is taken out from the intermediate tap, passes through resistor R2, is rectified by die A-D2, and is connected to capacitor C.
1 and output from terminal 7 as a power source for the video output circuit that drives the picture tube's shadow t4. One end of the secondary winding N2+ is connected to the automatic beam current limiting circuit via terminal 12, and between the secondary windings N2+ and N22, N23 and N
A rectifier diode D3. The secondary winding N24 is connected to the terminal 3 through a rectifier diode D5 and a resistor R3 for shock protection due to discharge inside the picture tube. The positive pulse voltage is rectified and output from this terminal 3 as the anode voltage of the picture tube. Along with this, the secondary winding N22. is divided at an appropriate ratio. The voltage taken out from the center tap of N23 is outputted from terminal 4 via variable resistor V1 as a single orifice voltage of the picture tube.

このフライバックトランス1の3次巻線N 3+に発生
した電圧は電圧調整用の抵抗RIを介して端子13より
受像管のヒータ電圧として出力される。
The voltage generated in the tertiary winding N 3+ of the flyback transformer 1 is output as the heater voltage of the picture tube from the terminal 13 via the voltage adjusting resistor RI.

また、適当な比率で分割された3次巻線N32゜N33
の中間タップは接地されており、3次巻線N32に発生
した負極性のパルス電圧はダイオードD6で整流された
後保護用の抵抗R5を通り、コンデン゛すC2で平滑さ
れ−(端子6よりヂューナ。
In addition, the tertiary winding N32°N33 divided at an appropriate ratio
The intermediate tap of is grounded, and the negative pulse voltage generated in the tertiary winding N32 is rectified by the diode D6, passes through the protective resistor R5, and is smoothed by the capacitor C2. Juna.

映像中間周波増幅回路等の小信号回路に供給される。ま
た、3次巻線N 33の一端はダイオード[)1のアノ
ードに接続され、このダイオードD1のノコソードはピ
ーク電流を抑圧Jるためのインダクタンス素子11の一
端に接続されている。インダクタンス素子1−1の他端
は一端を接地された」ンデンザC3の他端及び端子5に
接続されている。この3次巻線N 33に発生した正極
↑に1のパルス電F1はダイオードD1で整流された後
インダクタンス素子L1を通りコンデンサC2で平滑さ
れて☆:i4 T 5J:り垂直偏向出力回路に供給さ
れる。
It is supplied to small signal circuits such as video intermediate frequency amplification circuits. Further, one end of the tertiary winding N33 is connected to the anode of the diode [)1, and the anode of this diode D1 is connected to one end of the inductance element 11 for suppressing the peak current. The other end of the inductance element 1-1 is connected to the terminal 5 and the other end of the inductor C3 whose one end is grounded. The positive polarity ↑ 1 pulsed current F1 generated in the tertiary winding N33 is rectified by the diode D1, passes through the inductance element L1, is smoothed by the capacitor C2, and is supplied to the vertical deflection output circuit. be done.

ここで、インダクタンス素子L1のインダクタンス値を
増加させると高圧出力電JJ: l: II T + 
は第6図(A)の実線■bに示づ如く上昇した後低不し
、高圧負荷変動率ηは第6図(B)の実線■bに示す如
く急激に低下して改善される。また、垂直偏向出力回路
へ供給する電圧つまり端子5の電圧、フライバックトラ
ンス1に端子2より流入す゛る電流は夫々第6図(C)
、(D)の実線■b。
Here, when the inductance value of the inductance element L1 is increased, the high voltage output voltage JJ: l: II T +
increases as shown by the solid line (2) b in FIG. 6(A) and then remains low, while the high voltage load fluctuation rate η rapidly decreases and improves as shown in the solid line (2) b in FIG. 6(B). In addition, the voltage supplied to the vertical deflection output circuit, that is, the voltage at terminal 5, and the current flowing into the flyback transformer 1 from terminal 2 are shown in Fig. 6 (C).
, solid line ■b in (D).

IV bに示す如〈従来と同様に低下する。更に高圧負
荷電流をOmAから1mAに変化させIC際の端子5の
電圧変動は第6図(E)の実線vbに示づ−如く低下】
る。
As shown in IV b, it decreases as before. Furthermore, by changing the high-voltage load current from OmA to 1mA, the voltage fluctuation at terminal 5 at the IC decreases as shown by the solid line vb in Figure 6(E)]
Ru.

また、インダクタンス素子[1のインダクタンス値を1
0μH,2oμHと選んだとき夫々のダイオードD1の
アノードにおりる電圧、電流波形を第9図<A)、([
3>に示す。ここで実線A1゜△2は電圧波形を示し、
実線B+ 、B2は電流波形を示している。この第9図
(△)、(B)に示づ如く、インダクタンス値を増加さ
けるに従って電流の導通期間は長くなり、電圧のピーク
点に対する電流のピーク点の遮れが大となる。また、第
55図の実1iQ A Oに示されるパルス電圧波形の
尖頭部のつぶれ及び右肩部の電圧急変部分がなくなり、
電圧波形は垂直偏向出力回路へ電源を供給しない場合の
波形と略同−となる。また、第6図(C)より20μH
のインダクタンス素子L1と略等しい端子5の電圧を得
るには第1図示の回路では抵抗 R1を4.7Ωとすれ
ば良いが、このときのダイA−ドD1のアノードにd5
りる電圧波形、電流波膨大々は第9図(C)の実線Δ3
.B3に示J如きものである。この第9図(B)、(C
)を比較りるど電流のピーク値は略同じ値であるが、イ
ンダクタンス素子し1を用いたものの方が電流の導通期
間が長く、電圧波形についても尖頭部の奇数次高調波の
波形がくずれず電圧急変部分がなくなつ゛C理想的な波
形となつ−Cいる。また第9図(C)では電圧、電流の
ピーク点が略同−であるのに対し、第9図(B)では電
流のビーク5気が電圧のピーク点より遅れている。従っ
て、ダイオードD+の導通時間と電圧のピーク点の時間
が−ずれ、第6図()3 )に、示す−如く高圧負荷変
動率ηが急激に低下改善される。
In addition, the inductance value of the inductance element [1] is
When 0μH and 2oμH are selected, the voltage and current waveforms at the anode of each diode D1 are shown in Fig. 9<A), ([
3>. Here, the solid line A1゜△2 shows the voltage waveform,
Solid lines B+ and B2 indicate current waveforms. As shown in FIGS. 9(Δ) and (B), as the inductance value is increased, the current conduction period becomes longer and the interruption of the current peak point with respect to the voltage peak point becomes larger. In addition, the collapse of the peak of the pulse voltage waveform shown in Figure 55 and the sudden voltage change part at the right shoulder are eliminated,
The voltage waveform is approximately the same as the waveform when no power is supplied to the vertical deflection output circuit. Also, from Figure 6(C), 20μH
In order to obtain a voltage at the terminal 5 that is approximately equal to the inductance element L1, the resistor R1 may be set to 4.7Ω in the circuit shown in the first diagram.
The voltage waveform and current waveform shown in Fig. 9(C) are the solid line Δ3.
.. It is as shown in B3. This figure 9 (B), (C
), the peak value of the current is almost the same value, but the current conduction period is longer with the inductance element 1, and the voltage waveform of the odd-numbered harmonics at the peak is also different. There is no distortion and there are no sudden voltage changes, resulting in an ideal waveform. Further, in FIG. 9(C), the peak points of voltage and current are approximately the same, whereas in FIG. 9(B), the peak point of current is delayed from the peak point of voltage. Therefore, the conduction time of the diode D+ and the time of the voltage peak point are shifted by -, and the high-voltage load fluctuation rate η is rapidly reduced and improved as shown in FIG. 6() 3).

更に、インダクタンス素子L1によつCフライバック1
−ランス1の高調波の同調点を変化させることができ、
第6図(A>の実FA I bに示づ高圧出力電圧F 
HT +が最大となるインダクタンス値を選択してフラ
イバックトランス1の効率を」−げろことが可能となる
。一方、このインダクタンス索子1−1を挿入した場合
フライバックトランス1に端子2より流入する電流は第
6図(D>に示す如く抵抗R1を用いた場合と略同−の
値であり、また第6図(「)に示す如くインダクタンス
素子1−1を用いたんが端子5より出力される平向偏向
出力回路の電源の安定度が改善される。すなわち、入力
が増加することなく出力が増加しておりフライバックト
ランス1の効率が良くなっている。
Furthermore, the C flyback 1 is caused by the inductance element L1.
-The harmonic tuning point of lance 1 can be changed,
High voltage output voltage F shown in Figure 6 (actual FA I b of A)
It is possible to increase the efficiency of the flyback transformer 1 by selecting the inductance value that maximizes HT+. On the other hand, when this inductance cable 1-1 is inserted, the current flowing into the flyback transformer 1 from the terminal 2 is approximately the same value as when using the resistor R1 as shown in FIG. As shown in Fig. 6 (), the stability of the power supply of the flat deflection output circuit output from terminal 5 is improved by using the inductance element 1-1.In other words, the output increases without increasing the input. This improves the efficiency of the flyback transformer 1.

第10図は本発明のフライバックトランスの第2実施例
の回路図を示す。同図中、第2図、第8図と同一部分に
は同一符号を付し、その説明を省略する。第10図中、
フライバックトランス8の1次巻線NI+、N+2の中
間タップはインダクタンス素子L2の一端に接続されて
おり、ピーク電流を抑圧するためインダクタンス素子L
2の他端は整流用のダイオードD2のアノードに接続さ
れこのダイオードD2のカソードは一端を接地されたコ
ンデンサC1の他端及び端子7に接続されている。この
1次巻線N nに゛発生した正極性のパルス電圧はイン
ダクタンス素子L2を通りダイオードD2で整流され、
さらにコンデン+tC+で平滑されて端子71:り映像
出力回路に供給される、。
FIG. 10 shows a circuit diagram of a second embodiment of the flyback transformer of the present invention. In this figure, the same parts as in FIGS. 2 and 8 are designated by the same reference numerals, and their explanations will be omitted. In Figure 10,
The intermediate taps of the primary windings NI+ and N+2 of the flyback transformer 8 are connected to one end of the inductance element L2, and the inductance element L is connected to one end of the inductance element L2 to suppress the peak current.
The other end of the rectifying diode D2 is connected to the anode of the rectifying diode D2, and the cathode of the diode D2 is connected to the terminal 7 and the other end of the capacitor C1 whose one end is grounded. The positive pulse voltage generated in the primary winding Nn passes through an inductance element L2 and is rectified by a diode D2.
The signal is further smoothed by a capacitor +tC+ and supplied to a terminal 71: a video output circuit.

ここで、インダクタンス素子[2のインダクタンス値を
増加させると高圧出力電圧E l−I T + 、 i
?’:i圧負荷変動率°η、高圧負荷電流をQ m八か
ら1111Aに変化させた際の端子7の電L1−変動、
端子7の電1.1夫々ハ第7図<A)−(D)の実線v
Ib〜IXbに示り゛如く変化Jる。また、第11図(
A)。
Here, when the inductance value of the inductance element [2 is increased, the high voltage output voltage E l-I T + , i
? ': i voltage load fluctuation rate °η, voltage L1- fluctuation at terminal 7 when changing high voltage load current from Qm8 to 1111A,
Terminal 7 voltage 1.1, respectively, Fig. 7 < Solid line v of A)-(D)
There are changes as shown in Ib to IXb. Also, Figure 11 (
A).

(B)夫々は端子7より略等しい電圧が得られるインダ
クタンス素子L 2のインダクタンス(「1を/1. 
Ou Hとした場合と、第2図の抵抗R2の抵抗(IY
lを100とした場合とのダイオード1)2のアノ−1
〜におりる電圧及び電流波形を承り。ここで実線AI、
△5は電圧波形、B、1.85は電流波形を示している
。この第11図(A>、(B)に示づ如くインダクタン
ス索子1−2を用いた方が電流の導通期間が長く、電流
のピーク値が小ざく、電流のピーク点が電圧のピーク点
より遅れており、電圧波形もきれいである。この電流の
遅れにより高圧負荷変動率ηが第7図(B)に示゛り如
く改善され、インダクタンスL2の値を変化させて高圧
出力電圧EHT+が第7図(A)の最大値をとるよう変
化させフライバックトランス8の効率を上げることがで
きる。このとぎ、端子2に流入する電流及び端子7より
取り出°り電圧の安定度は抵抗R2を用いたときと略同
−である。
(B) The inductance of the inductance element L2 from which substantially equal voltages can be obtained from the terminal 7 ("1 to /1.
Ou H and the resistance of resistor R2 (IY
Diode 1) Anor-1 of 2 when l is 100
We accept voltage and current waveforms ranging from ~. Here, the solid line AI,
Δ5 indicates a voltage waveform, and B, 1.85 indicates a current waveform. As shown in FIG. 11 (A>, (B)), when the inductance cable 1-2 is used, the current conduction period is longer, the peak value of the current is smaller, and the peak point of the current is the peak point of the voltage. This current delay improves the high-voltage load fluctuation rate η as shown in Figure 7 (B), and by changing the value of inductance L2, the high-voltage output voltage EHT+ increases. The efficiency of the flyback transformer 8 can be increased by changing the value to take the maximum value shown in FIG. This is almost the same as when using .

このように、抵抗R1又はR2の代りにインダクタンス
素子L1又はL2を使用゛りることにより、整流用のダ
イオードD1又1はD2を流れる電流のピーク値を抑圧
すると共に、電流のピーク点を電圧のピーク点より遅ら
せて高圧負荷変動率ηを改落できる。このため、例えば
フライバック1〜ランメ1にり負極性パルスを発生さけ
て垂直偏向出力回路に供給づる必要がなくなり巻線の巻
回数が少なくて演み、巻線の絶縁及びタイオードの逆耐
圧し低くて良く、コストが安価となる。また、受像管の
管内放電時に発生する異常パルス電圧も巻回数が少ない
ために小さくその際の電流もインダクタンス素子L1.
L−2で抑圧されダイオード[〕1D2等が充分に保護
される。また、抵抗RI。
In this way, by using the inductance element L1 or L2 instead of the resistor R1 or R2, the peak value of the current flowing through the rectifying diode D1 or D2 is suppressed, and the peak point of the current is changed to the voltage The high voltage load fluctuation rate η can be reduced later than the peak point of . For this reason, for example, it is not necessary to generate negative polarity pulses from flyback 1 to ramme 1 and supply them to the vertical deflection output circuit, and the number of turns of the windings is reduced, which improves the insulation of the windings and the reverse withstand voltage of the diode. It is low cost and the cost is low. Furthermore, the abnormal pulse voltage generated during discharge within the picture tube is small because the number of turns is small, and the current generated at that time is also small due to the small number of turns of the inductance element L1.
It is suppressed by L-2 and the diode [ ] 1D2 etc. are sufficiently protected. Also, the resistance RI.

R2よりインダクタンス索子L+、L2の方が電力損失
が小さく発熱も少ないので素子の小型化が可能となる。
Since the inductance wires L+ and L2 have smaller power loss and generate less heat than R2, it is possible to miniaturize the element.

更に、インダクタンス素子L+。Furthermore, an inductance element L+.

1−2のインダクタンス値を適当に選定りることにより
フライバックトランス1.8の高調波に対する同調点を
変化させて最大の高圧出力ミルを得ることができフライ
バックトランスの効率を上げることができる。
By appropriately selecting the inductance value of 1-2, the tuning point for the harmonics of the flyback transformer 1.8 can be changed to obtain the maximum high voltage output mill, and the efficiency of the flyback transformer can be increased. .

なお、第8図にJ3ける抵抗R2を第10図と同様にイ
ンダクタンス素子12に代えても良く、インダクタンス
素子L1は3次巻線N 33の一端どタイオードD+の
アノードとの間に接続しても良く、インダクタンス素子
L2はダイオードD2のノコソードとコンデンサC+の
一端との間に接続しても良く、上記実施例に限定されな
い。
Note that the resistor R2 at J3 in FIG. 8 may be replaced with the inductance element 12 as in FIG. 10, and the inductance element L1 is connected between one end of the tertiary winding N33 and the anode of the diode D+. Alternatively, the inductance element L2 may be connected between the anode of the diode D2 and one end of the capacitor C+, and is not limited to the above embodiment.

上述の如く、本発明になるフライバック]・ランスは、
低圧側の1次巻線、高圧側の2次巻線、パルス発生用の
3次巻線のうち少なくとも1次巻線ど2次巻線とを有し
、1次巻線及び/又は3次巻線から正極性のパルス電圧
を取り出しパルス電圧を整流素子及び平滑素子により整
流平滑して比較的高電力を要する回路に供給するフライ
バック[・ランスにおいて、1次巻線及び/又は3次巻
線の正極性パルスを取り出す端子と平滑素子との間に整
流素子と直列にインダクタンス素子を設けてなるため、
高圧負荷変動率が改善され、これによって巻線の巻回数
が少なく巻線の絶縁及び整流素子の逆耐圧が低くて済み
コストが安価となり、また従来より電力損失が少ないの
で小型のインダクタンス素子を使用することが可能どな
り、更にインダクタンス素子は2次巻線より取り出され
る高庄出力電圧をインダクタンス素子がないときに比し
て高くするようなインダクタンス値に設定してなるため
、このフライバックトランスの効率が改善される等の特
長を有するものである。
As mentioned above, the flyback lance according to the present invention is
It has at least a primary winding and a secondary winding among a primary winding on the low voltage side, a secondary winding on the high voltage side, and a tertiary winding for pulse generation, and the primary winding and/or the tertiary winding A flyback lance that extracts a positive pulse voltage from the winding, rectifies and smoothes the pulse voltage using a rectifying element and a smoothing element, and supplies it to a circuit that requires relatively high power. Since an inductance element is provided in series with the rectifying element between the terminal for taking out the positive pulse of the line and the smoothing element,
The high-voltage load regulation rate has been improved, which reduces the number of turns of the winding, requires less winding insulation, and lower reverse withstand voltage of the rectifying element, resulting in lower costs.Also, smaller inductance elements are used because power loss is lower than before. In addition, the inductance element is set to an inductance value that makes the high output voltage extracted from the secondary winding higher than when there is no inductance element, which improves the efficiency of the flyback transformer. It has features such as improved performance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は従来のフライバックトランスの各個の
回路図、第3図、第4図、第5図は第1図示のフライバ
ックトランス各部の電圧波形及び電流波形図、第6図(
A)〜(E)は第1図、第8図に示づ抵抗R+、インダ
クタンス系子11の定数を変化させたとぎの各特性図、
第7図<A)〜(D>は第2図、第10図に示す抵抗R
2,インダクタンス素子L2の定数を変化させたときの
各特性図、第8図、第10図は本発明になるフライバン
ク1−ランスの各実施例の回路図、第9図(A)〜(C
)、第11図(A)、(B)は第1図、第2図、第8図
、第10図の各部の電J+波形及び電流波形図である。 1.8・・・フライバック1〜ランス、3・〜7,12
゜13・・・端子、C1へ・C3・・・二1ンデンリ、
Dlへ・D6・・・ダイオード、Ll、l−2・・・イ
ンダクタンス索子、R+・〜・1(5・・・抵抗、Nu
、N+?・・・1次巻線、N21・〜N 24・・・2
次巻線、N31へ・N31・・・3次巻線。 第6図 −R+In] −127asecm −晴間〔μ5ec〕 第1図 一昨間[psecl
Figures 1 and 2 are individual circuit diagrams of a conventional flyback transformer, Figures 3, 4, and 5 are voltage and current waveform diagrams of various parts of the flyback transformer shown in Figure 1, and Figure 6. (
A) to (E) are characteristic diagrams when the constants of the resistance R+ and the inductance system 11 shown in FIGS. 1 and 8 are changed,
Figure 7 <A) to (D> are the resistances R shown in Figures 2 and 10.
2. Characteristic diagrams when changing the constant of the inductance element L2, FIGS. 8 and 10 are circuit diagrams of each embodiment of the flybank 1-lance according to the present invention, and FIGS. 9 (A) to ( C
), FIGS. 11(A) and 11(B) are electric J+ waveforms and current waveform diagrams of each part of FIGS. 1, 2, 8, and 10. 1.8...Flyback 1~Lance, 3・~7,12
゜13...Terminal, to C1, C3...21,
To Dl・D6...Diode, Ll, l-2...Inductance wire, R+...1 (5...Resistance, Nu
, N+? ...Primary winding, N21...N24...2
Next winding, to N31/N31...Third winding. Figure 6-R+In] -127asecm - Clear space [μ5ec] Figure 1 Two days ago [psecl

Claims (2)

【特許請求の範囲】[Claims] (1)低圧側の1次巻線、高圧側の2次巻線、パルス発
生用の3次巻線のうち少なくとも1次巻線ど2次巻線と
を有し、該1次巻線及び/又は3次巻線から正極性のパ
ルス電圧を取り出し該パルス電圧を整流素子及び平滑素
子により整流平滑して比較的高電力を要覆る回路に供給
覆るフライバックトランスに(;3いで、該1次巻線及
び/又は3次巻線の正極性パルスを取り出り端子と該平
滑素子との間に該整流素子と直列にインダクタンス素子
を段4)’Uなることを特徴どづるフライバックトラン
ス。
(1) It has at least a primary winding and a secondary winding among a primary winding on the low voltage side, a secondary winding on the high voltage side, and a tertiary winding for pulse generation, and the primary winding and /or Take out a positive pulse voltage from the tertiary winding, rectify and smooth the pulse voltage using a rectifying element and a smoothing element, and supply relatively high power to the covering circuit. A flyback transformer characterized in that an inductance element is provided in series with the rectifying element between the terminal for taking out the positive pulse of the secondary winding and/or the tertiary winding and the smoothing element. .
(2)  該インダクタンス素子は該2次巻線j、り取
り出される高B−出力電圧を該インダクタンス素子が4
1いとさに比しく高くりるようなインダクタンス値に設
定してなることを特徴とする特許請求の範囲第1項記載
のフライバック1〜ランス。
(2) The inductance element is connected to the secondary winding j, and the high B-output voltage taken out by the inductance element is
1. The flyback lance according to claim 1, wherein the flyback lance is set to have an inductance value that is higher than that of the flyback lance.
JP58017251A 1983-02-04 1983-02-04 Fly-back transformer Granted JPS59143477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58017251A JPS59143477A (en) 1983-02-04 1983-02-04 Fly-back transformer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58017251A JPS59143477A (en) 1983-02-04 1983-02-04 Fly-back transformer

Publications (2)

Publication Number Publication Date
JPS59143477A true JPS59143477A (en) 1984-08-17
JPH0221716B2 JPH0221716B2 (en) 1990-05-15

Family

ID=11938727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58017251A Granted JPS59143477A (en) 1983-02-04 1983-02-04 Fly-back transformer

Country Status (1)

Country Link
JP (1) JPS59143477A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2593961A1 (en) * 1986-02-04 1987-08-07 Orega Electro Mecanique HIGH VOLTAGE TRANSFORMER IN FRACTIONED TECHNOLOGY, ESPECIALLY FOR CATHODE TRICHROME TUBE
JPH02185006A (en) * 1989-01-12 1990-07-19 Murata Mfg Co Ltd Flyback transformer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55131274A (en) * 1979-03-29 1980-10-11 Sharp Corp Power supplying circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55131274A (en) * 1979-03-29 1980-10-11 Sharp Corp Power supplying circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2593961A1 (en) * 1986-02-04 1987-08-07 Orega Electro Mecanique HIGH VOLTAGE TRANSFORMER IN FRACTIONED TECHNOLOGY, ESPECIALLY FOR CATHODE TRICHROME TUBE
US4858098A (en) * 1986-02-04 1989-08-15 Societe Orega Electronique Et Mecanique Split-diode high-voltage transformer
JPH02185006A (en) * 1989-01-12 1990-07-19 Murata Mfg Co Ltd Flyback transformer

Also Published As

Publication number Publication date
JPH0221716B2 (en) 1990-05-15

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