JPS59142678A - Frame recognizing system - Google Patents

Abstract

PURPOSE:To recognize surely even an unshaped frame by extracting a long segment as a frame line candidate from a picture OR reduce in each scanning direction after the majority processing to make the picture hardly affected by noise. CONSTITUTION:A binary picture signal is inputted to an input terminal 100 in a picture unit. This binary picture signal is inputted directly to a latch circuit 101 and is inputted to latch circuits 104 and 105 after being delayed by the on- line length. The output signals of circuits 101, 104, and 105 are subjected to the majority processing, and the output is outputted from an OR circuit 109. Or between the output signal of this circuit 109 and a signal attained by delaying this signal by the one-line length is ORed in an OR circuit 112 through latch circuits 127-129 and is inputted to a counter circuit 113. A control circuit 114 enables 3 the circuit 113 for one scanning time and is ORed for the scanning lines in the subscanning direction to reduce them to one scanning line. An integrating circuit 118 integrates a black run, which can be regarded as one long segment, out of the extracted black runs in the main scanning direction. The similar operation is performed in the subscanning direction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for recognizing a frame on a binary image such as an I-square or a document.

[Prior art]

The method of gating a frame on a binary image is as follows: 1) Detect patterns equivalent to the corners of the frame by pattern matching using a mask, and select those that satisfy a predetermined positional relationship from among the detected patterns. (1) A method of recognizing frames by tracing line segments and determining the shape of the trajectory of the line segments that forms a closed loop; (2) A method of recognizing frames by tracing line segments and determining the shape of the line segment locus that forms a closed loop; (2) Extracting long line segments in each of the main and sub-scanning directions; Main as border, m %
A typical method is the 08 method, which recognizes frames by determining two pairs of long line segments in the scanning direction.

However, although the above method (2) can be applied to the recognition of a well-shaped frame such as a printed frame, when applied to the gait of a frame with large deformation such as a handwritten frame, the recognition rate is seriously reduced. In other words, there is a drawback that the degree of freedom of the recognition target is small. Method (2) is easily affected by noise such as cutting of rocks and skew (and also has the drawback that it requires a relatively large capacity image buffer, but the processing time tends to be long.

As for the above method (■), the inventor performed high-speed processing by ORing the z-value image in the main and sub-scanning directions, reducing it in the main and Noritani scanning directions, and extracting long line segments from the reduced image. An improved method has already been proposed that makes it easier and less susceptible to the effects of skew (Japanese Patent Laid-Open No. 104868/1983). However, when processing facsimile paintings, etc., erroneous recognition may occur. In other words, in transmitted images such as facsimile images, a single black line in the main scanning direction is likely to occur as noise. There was a case.

〔the purpose〕

The purpose of the present invention is to enable high-speed processing without requiring a large image buffer, to be less susceptible to noise and skew such as "black lines," and to be able to handle deformed frames such as handwritten frames. The purpose of this invention is to provide an applicable frame recognition method.

More specifically, the present invention aims to provide a frame recognition method that is an improvement on the above method (2).

〔Example〕

FIG. 1 is a schematic block diagram showing one embodiment of the present invention.

The binary image signal for frame recognition processing is input to input terminal 10.
0 is serially input pixel by pixel. This binary image signal is input directly to the latch circuit 101, and is input to the latch circuits 104 and 105 after being delayed by one line length shift registers 102 and 108, respectively. Therefore, the image cumulative deviation at the same position in eight consecutive scan lines of a binary image (in this example, black is '1' and white is '0')
) are latched by the latch circuits 101, 104 and 105.

The output signals of latch circuits 101 , 104 , 105 are output from AND circuits 106 , 107 , 108 and OR circuit 109
The input signal is input to a majority circuit consisting of , and subjected to majority voting processing. That is, only when the output signals of two or more of the latch circuits 101, 104, and 105 are 1'', the OR circuit 109
The output signal becomes 1". In this embodiment, the majority decision process is performed for 8 scanning lines, but the invention is not limited to this. For example, majority decision processing may be performed for 5 scanning lines.Basic The number of scanning lines that takes a majority vote can be determined depending on the accuracy of frame recognition.The "black streaks" that occur in facsimile images are generally one pixel thick, and can be removed by majority voting processing. Colander.

The output signal of the OR circuit 109 of the majority processing circuit and the signal delayed by the one-line shift registers 110, 111 are input to the OR circuit 112 via the latch circuits 1217, 128, 129. It will be done.

The output signal of this OR circuit 112 is input to a counter circuit 118. This force I counter circuit 118 is connected to the control circuit 11
4, the input signal is
After the transition from 0'' to 1'', the pixel clock starts counting, and when the human input signal transitions from 1'' to 0', the count value is output and then reset. That is, the control circuit 11
The output signal of the OR circuit 112 is valid only during the period when the counter circuit 118 is enabled in step 4. This timing control will be explained with reference to FIG.

In Fig. 2, Si, j are pixels on the input binary image, and i
is the bud (scanning line number) in the sub-scanning direction, and j is the address in the main scanning direction. The positions of the pixels before and after the majority decision process have a one-to-one correspondence (that is, no reduction is performed). The control circuit 114 is! -0 and i=1 scanning line majority processing signals are accumulated in shift registers 110 and 111, and i=2 scanning line majority processing signals are stored in the majority processing OR circuit 1.
The counter circuit 118 is enabled for one scanning line period from the time of output from 09, and the output signal of the OR circuit 112 is made valid. Similarly, the output signal of the OR circuit 112 is enabled in the last scan line (i=5) of the next eight scan lines. Thereafter, by similar control, the majority-processed image is essentially divided into blocks every 8 scanning lines, and the 8 scanning lines of each block are divided into blocks.
The scanning lines are ORed in the sub-scanning direction and reduced to one scanning line. The pixels on the image reduced to % in the sub-scanning direction in this manner are .times. and j in FIG. 2, where .lambda. is an address in the sub-scanning direction and j is an address in the main scanning direction. V engineering, j of j has a one-to-one correspondence with 5lpj, and ■ corresponds to l-θ~2.
=0 corresponds to I=1 and ■=8 to 4.

Note that the reduction magnification is not limited to %.

Now, returning to FIG. 1, as is clear from the above, the counter circuit 118 counts and outputs the length of the black run on each constant distortion line of the image reduced in the sub-scanning direction. Comparison circuit 115 compares the run length output from counter circuit 118 with a predetermined value of 1M,
After J-□ or more, a cutting signal is sent to the length memory 116 and the position memory 117.

When the length memo IJ 116 receives the cutting signal, it internally stores the run length data output from the counter circuit 118. Further, the position memory 117 has the address LJ of the reduced image/sickle manually entered from the control circuit 114, and the address I when the write signal is given.

The data of j is stored in 1b (;. That is, the human-powered binary image is subjected to majority voting processing, and among the focused runs on the image that has been reduced in the sub-scanning direction by the embedding process, the run length of JlB or more is stored. The length data of the black run held and the address data of the end (right end) of the black run are stored in the length memory 11.
0 is obtained in the position memory 117.

118 is an integrated circuit that refers to the data stored in the length memory 116 and the position memory 117, and can be regarded as one long line segment among the black runs in the main scanning direction extracted as described above. Performs processing to integrate black runs. That is,
When the distance in the main scanning direction between the black run at I= and the other black run at I=k or ■=1 (±1) is less than or equal to a certain value m, Combine them into one black run. /jThe starting address of the black run is determined from the Nagashio address and the run length.For example, the 8th agon (A)
The pair of black runs shown in , (b), and (c) are integrated.

Then, the integrating circuit 118 determines the leading and ending addresses of the integrated black run, that is, the long line in the main scanning direction, and outputs it.

In this way, since the black runs extracted from the depressed image are integrated and the long line segments in the main scanning direction are used, the long line segments that are skewed overall due to the skew may also be locally affected due to noise. It is possible to reliably extract long line segments that are broken, line widths change, or are slightly curved, such as in the framework of a handwritten frame. Moreover, as mentioned above, due to the majority voting process, 0 black stripe becomes 1 black stripe.
Therefore, there is no possibility of erroneously extracting a "black streak" as a long line segment.

Extraction of long line segments in the sub-scanning direction is similar, and will be explained below.

The output signal of the OR circuit 109 of the majority circuit is sequentially input to an 8-bit shift register 119, and each time eight pixels are accumulated, an output timing is sent from the control circuit 114, and the shift register 119 outputs the contents in parallel. Then reset. The output signal of this shift register 119 is ORed by an OR circuit 120, and an image signal reduced by % in the main scanning direction is input to a counter memory circuit 121.

HLJ in FIG. 2 is a pixel on the image reduced in the main scanning direction, l corresponds one-to-one with I of Si, j,
J is s, j=0-2 is J=0, j=8-5 is J=
It corresponds to 1.

Note that the reduction magnification is not limited to %.

Returning to FIG. 1, the counter memory circuit 121 has a color function and a memory function having a memory address corresponding to the maximum value of address J. That is, when the value of the address J given from the control circuit 114 is switched (at this time, the counter memory circuit 121 inputs the shift register 119
), and the output signal of the OR circuit 120 is '
1", 1 is added to the memory contents of memory address (J). Also, when the output signal of the OR circuit 120 is '0", after outputting the memory contents of memory address (J), the same value is added. Clears the contents of a memory address. In other words, the counter memory circuit 121 extracts black runs in the sub-scanning direction on the image reduced in the main-scanning direction, calculates the run length,
When the end (lower end) of a black run is detected, this circuit outputs the run length.

The comparison circuit 122 compares the run length output from the counter memory circuit 121 with a certain value 1v, and if the value is 17 or more, sends out a write signal. When this commitment signal is issued, the length memory 128 internally stores the run length data output from the counter memory circuit 121. Further, when a write signal is output, the position memory 124 is connected to the control circuit 1.
The data at address i%J given from 14 is stored. The integration circuit 125 is a circuit that refers to the data stored in the length memory 12B and the position memory 124, and performs the same integration process as the above-mentioned integration circuit 118 on the extracted black zine in the sub-scanning direction. That is, black runs at J= and J=k or J=
When the distance in the sub-scanning direction between the end of the black run and the start end or the start end and the end of the other black run with ±1 is less than a certain value, those black runs are integrated into one black run, and the integrated black run is Outputs the start and end addresses of a run (long line segment in the sub-scanning direction).

In this way, since the black runs extracted from the OR-reduced image are integrated and the long line segments in the sub-scanning direction are extracted, even long line segments that are tilted overall due to skew may be locally interrupted due to noise or the line width It is possible to reliably extract long line segments that change or are curved, such as the frame line of a handwritten frame.

The long line segments in the main and rigid scanning directions extracted as described above are frame line candidates, and each data is stored in the frame recognition unit 12.
6 is input. This frame g heel section 126 examines the relative positional relationship of long line segments as input frame line candidates, and calculates a pair of long line segments in the main scanning direction and a pair of long line segments in the sub scanning direction constituting one frame.
Distinguish the pair of long line segments and recognize the frame area. This frame recognition process may be performed using the same procedure as detailed in the above-mentioned Japanese Patent Application Laid-Open No. 57-104868, and is not the main point of the present invention, so a detailed explanation will be omitted.

〔effect〕

As described in detail above, the present invention extracts long line segments as frame line candidates from an image that has been subjected to minor logical processing in the main and sub-scanning directions after performing majority processing.
etc., and can reliably recognize not only printed frames but also irregularly shaped frames such as handwritten frames. Moreover, as is clear from the above example, the large violet image buffer This has the effect of easily achieving high-speed processing without using .

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention, and FIG.
The figure is a diagram for explaining image reduction, and FIG. 8 is a diagram showing an example of line segments to be integrated. 102, 108, 110, 111, 119...
・Shift register, 101, 104, 105, 1
27, 128, 129... latch circuit, 11B.
...Counter circuit, 114...Control circuit, 115°1
22... Comparison circuit, 116, 128... Length memory, 117° 124... Position memory, 118, 1
25... Integrated circuit, 121... Counter memory circuit, 126... Frame recognition unit. -453- (c) Reward χ2

Claims (1)

[Claims] (1) Frame recognition that recognizes frames by extracting long line segments in the main scanning direction and sub-scanning direction on a binary image and distinguishing between two pairs of long line segments in the main and secondary scanning directions as frame lines In this method, for each set line of a binary image, a majority determination process is performed on the state of each pixel between adjacent mantissa scanning lines, and after this majority decision process, sub-scanning is performed for each of multiple constant strain lines in the binary picture mound. A z-value image reduced in the sub-scanning direction is obtained by processing the z-value image in the sub-scanning direction, and a z-value image reduced in the main-scanning direction is obtained by performing logical sum processing in the main-scanning direction for each of multiple images Obtain a binary image reduced to , extract long line segments in the main scanning direction from the binary image reduced in the sub-scanning direction,
A frame recognition method characterized in that a long line segment in the sub-scanning direction is extracted from the binary image reduced in the main-scanning direction.