JPS59141897A - Processing system of signal bit - Google Patents

Processing system of signal bit

Info

Publication number
JPS59141897A
JPS59141897A JP1582083A JP1582083A JPS59141897A JP S59141897 A JPS59141897 A JP S59141897A JP 1582083 A JP1582083 A JP 1582083A JP 1582083 A JP1582083 A JP 1582083A JP S59141897 A JPS59141897 A JP S59141897A
Authority
JP
Japan
Prior art keywords
data
exchange
bit
bits
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1582083A
Other languages
Japanese (ja)
Other versions
JPH0544240B2 (en
Inventor
Kozo Nakamura
中村 昂三
Sadao Aso
阿相 貞雄
Toshio Itabashi
板橋 敏雄
Takeshi Takahashi
剛 高橋
Daisaku Minato
湊 大作
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Tokyo Electric Power Co Holdings Inc
Original Assignee
Tokyo Electric Power Co Inc
Fujitsu Ltd
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electric Power Co Inc, Fujitsu Ltd, NEC Corp, Nippon Electric Co Ltd filed Critical Tokyo Electric Power Co Inc
Priority to JP1582083A priority Critical patent/JPS59141897A/en
Publication of JPS59141897A publication Critical patent/JPS59141897A/en
Publication of JPH0544240B2 publication Critical patent/JPH0544240B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Interface Circuits In Exchanges (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To multiplex a sound call and a data call to a PCM transmission line for an exchange system having a multiplexed PCM transmission line by changing a signal bit position for a terminal to another position which is different from an exchange control bit position. CONSTITUTION:When the data on a subscriber line interface of (F+D1-D6+S) bits is sent from a terminal side, a line circuit holds the data blocks of every 8 bits at a shift register RA by a clock (a). Then (D1-D6+S) bits are shifted by one bit excepting the F bit and stored in a shift register RB to be delivered to the side of an exchange EX1 by a clock (b). The EX1 puts the data of 7 bits into a prescribed channel and then transmits the data to a transmission line after adding a signal bit of exchange control to the final bit position.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明はディジタルデータの伝送方式に係り、特にディ
ジタル交換機、PCM伝送路を介してのデータ端末間の
データ伝送における信号ビット処理に関するものである
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a digital data transmission system, and particularly relates to signal bit processing in data transmission between data terminals via a digital exchange and a PCM transmission line. .

(2)技術の背景 通信データの多様化にともない、交換ネットワークにお
いても、ディジタル交換機の導入と、伝送路の多重化に
ともないPCM回線を使用した交換システムの開発がな
されている。ディジタル交換機と伝送路は、多重化され
たチャネル毎に例えば8ビツトのPCM符号化でインタ
フェースされ、音声呼は第1図に示すように、伝送路上
では12マルチフレームi成をと、b、iフレームが2
4チヤンネル(CH)と同期用ビットSとから成り、回
線毎に8ビツト(4)を音声のディジタル情報として使
用し、例えば6マルチフレーム毎に8ビツトの内の1ピ
ツ) (B)を信号ビ’/ )として用い、交換側、吻 衡止の回線の起動9選択信号、応答信号等に使用するP
CM24B伝送路等が使用される。
(2) Background of the technology With the diversification of communication data, digital exchanges have been introduced in switching networks, and with the multiplexing of transmission paths, switching systems using PCM lines have been developed. The digital exchange and the transmission line are interfaced with, for example, 8-bit PCM encoding for each multiplexed channel, and as shown in Figure 1, a voice call consists of 12 multiframes i, b, i, and frame is 2
It consists of 4 channels (CH) and a synchronization bit S, and 8 bits (4) are used for each line as audio digital information. For example, 1 bit (B) of the 8 bits is used as a signal every 6 multiframes. P is used as a switching side, a starting 9 selection signal, a response signal, etc. for a proboscised line.
A CM24B transmission line or the like is used.

(3)従来技術と問題点 一方、一般のデータ端末間のデータの送受信においては
、第2図に示す様に、同期用ビットF。
(3) Prior Art and Problems On the other hand, in the transmission and reception of data between general data terminals, as shown in FIG. 2, a synchronization bit F is used.

データ9ピツ)(D、〜D0)、端末装置の制御用信号
ビットSの8ビツトからなる1ブロツクを単位としてデ
ータのやりとシが行なわれている。
Data is exchanged in units of one block consisting of 8 bits of data (9 bits) (D, to D0) and control signal bits S of the terminal device.

このデータ端末が交換機を介さず端末相互間を接続する
専用回線を用いてデータの送受を行なう分では、音声呼
の伝送とは独立して制御され、第2図の伝送フォーマッ
トで専用回線上も伝送可能であるが、伝送路の有効利用
、音声呼、ファクシミリ呼、データ呼を同一交換機でP
CM回線へ多重通信するサービスの高度化を図る上では
、PCM伝送路として第2図に示したη+データ6ビツ
ト+(団のうちSビットが、交換制御上の信号ビットの
)に置換えられてしまい、データ呼のトランスベアレン
ジ−転送ができないという問題が生じる。
Since this data terminal sends and receives data using a dedicated line that connects the terminals without going through an exchange, it is controlled independently of voice call transmission, and the transmission format shown in Figure 2 is used to transmit and receive data over the dedicated line. transmission is possible, but it is important to make effective use of the transmission path and to transmit voice calls, facsimile calls, and data calls on the same exchange
In order to improve the service of multiplex communication to the CM line, the PCM transmission line should be replaced with η + 6 bits of data + (S bit of the group is the signal bit for exchange control) shown in Figure 2. Therefore, a problem arises in that data calls cannot be transferred across the transmission range.

従って、1つのチャンネルに任意時点で、音声あるいは
FAX、別の時点ではデータ呼を接続することができず
、交換機で音声呼、データ呼を同一に扱うことはできな
かった。
Therefore, it is not possible to connect a voice or FAX call to one channel at any given time, and a data call at another time, and it is not possible for the exchange to handle voice calls and data calls in the same way.

(4)発明の目的 本発明の目的は、上記問題点を解決するもので、PCM
伝送路に音声呼とデータ呼を多重化可能とし、さらに交
換機側では伝送路のインタフェース上で音声呼、データ
呼の識別することなく、伝送可能とする信号ビット処理
方式を提供することにある。
(4) Purpose of the invention The purpose of the present invention is to solve the above problems, and to
The object of the present invention is to provide a signal bit processing method that allows voice calls and data calls to be multiplexed on a transmission path, and further enables transmission on the exchange side without distinguishing between voice calls and data calls on the interface of the transmission path.

(5)発明の構成 上記目的を達成するために、本発明は、データ端末とデ
ィジタル交換機間のデータ送受信は端末用の信号ビット
を含むデータフォーマットで行なわれ、前記ディジタル
交換機と他局とのデータ送受信は交換制御ビットを含む
多重化されたPCM伝送路をインタフェースとして行な
われる交換システムにおいて、前記信号ビット位置を前
記交換制御ビット位置と異なる位置に入換える手段を設
けたことを特徴とする。
(5) Structure of the Invention In order to achieve the above object, the present invention provides that data transmission and reception between a data terminal and a digital exchange is performed in a data format that includes signal bits for the terminal, and that data between the digital exchange and other stations is transmitted and received. In an exchange system in which transmission and reception are performed using a multiplexed PCM transmission line containing exchange control bits as an interface, the present invention is characterized in that means is provided for changing the position of the signal bit to a position different from the position of the exchange control bit.

(6)発明の実施例 以下、本発明を実施例によシ説明する。(6) Examples of the invention The present invention will be explained below using examples.

先に第2図で説明したようにデータ端末間で送受される
情報としてはデータ6ビツトと信号3’にットの7ビツ
トがあればよく、Fビットは端末間あるいは端末交換機
間インタフェースにおける同期用ビットとして使用され
るものでそれ以外では不要である。本発明はこのデータ
端末で必要となるデータ6ビツトとSビ、トの合計7ビ
ツトが、交換機、伝送路上で保証されればよいことに着
目したものである。
As explained earlier in Figure 2, the information sent and received between data terminals only needs to be 6 bits of data and 7 bits of signal 3', and the F bit is used for synchronization at the interface between terminals or between terminal exchanges. This is used as a service bit and is not needed for other purposes. The present invention focuses on the fact that a total of 7 bits, including 6 data bits and S bits, required by this data terminal need only be guaranteed on the exchange and on the transmission path.

第3図は本発明を適用した交換システム構成の一例を示
すものである。図において、DTEはデータ端末装置、
DCEは端末終端装置、 LCはライン回路、EXIは
ディジタル交換機、DTはトランク、EX2は対局ディ
ジタル交換機等を示す。
FIG. 3 shows an example of the configuration of an exchange system to which the present invention is applied. In the figure, DTE is data terminal equipment,
DCE is a terminal terminal equipment, LC is a line circuit, EXI is a digital exchange, DT is a trunk, EX2 is a counterpart digital exchange, etc.

端末DTEと交換機EXI間は第2図に示すデータフォ
ーマットで送受A (以下これを加入者インタフェース
と称す)。また交換機間EXI−EXZ間の伝送路イン
タフェースは第1図に示す伝送フォーマット(例えばP
CM24B)で多重化されている。
Data is transmitted and received A between the terminal DTE and the exchange EXI in the data format shown in FIG. 2 (hereinafter referred to as the subscriber interface). In addition, the transmission line interface between EXI and EXZ between exchanges uses the transmission format shown in Figure 1 (for example, P
CM24B).

かかる構成において、本発明は交換機経由で伝送路Cヘ
データを転送する場合端末から交換機に入力する際ある
いは伝送路へ入力する際にデータ変換を行ない、逆に伝
送路から交換機あるいは交換機から端末へデータを送る
とき、データの逆変換をすることによシ達成される。
In such a configuration, the present invention converts data when inputting it from a terminal to an exchange or inputting it to a transmission path when data is transferred to transmission path C via an exchange, and vice versa. This is accomplished by inverting the data when sending it.

以下第4図、第5図を用いライン回路LCに本発明のデ
ータ変換である信号ビット処理方式を適用した実施例に
ついて説明する。
An embodiment in which a signal bit processing method, which is data conversion of the present invention, is applied to a line circuit LC will be described below with reference to FIGS. 4 and 5.

第4図は端末から交換機へデータを送出するときのビッ
トシフト処理を説明するもので、CF+D、〜Da+S
)の加入者線インタフェースのデータが端末側よシ送ら
れてくると、ライン回路LCでは8ビット単位のデータ
ブロックをクロック■によりシフトレジスタRAに保持
し、次にFビットを除いて〔D1〜D6+S、1を1ビ
ツトシフトして、シフトレジスタRBに格納し、クロッ
ク■により交換機EXI側へ送出する。交換機EX1で
はこの7ビツトのデータを所定のチャネル(着信端末側
へ割当てられたチャネル)に挿入し、第1図に示すよう
に該チャネルの最終ビット位置に交換制御上の信号ビッ
トノ)を付けて伝送路へ送出する。
Figure 4 explains the bit shift processing when sending data from the terminal to the exchange, CF+D, ~Da+S
) is sent from the terminal side, the line circuit LC holds the data block in units of 8 bits in the shift register RA using the clock ■, and then removes the F bit and transfers it to [D1~ D6+S, 1 is shifted by 1 bit, stored in the shift register RB, and sent to the exchange EXI side by the clock ■. The exchange EX1 inserts this 7-bit data into a predetermined channel (the channel assigned to the receiving terminal side), and adds a signal bit number for exchange control to the last bit position of the channel as shown in Figure 1. Send to the transmission path.

第5図は交換機側から端末へデータを送るときのビット
シフト処理を説明するもので、伝送路より所定のチャネ
ル(発信端末用に捕捉されたチャネル)に乗ったデータ
を8ビット抽出し、ライン回路LCへ送る。ライン回路
Lc′では仁の8ビットをクロック■によシフトレジス
タRCへ保持し、次に同期ピットFを■によりシフトレ
ジスタRDに格納するとともに、レジスタRCの内容を
1ビツトシフトしてシフトレジスタRDに格納する。ク
ロック■によシ、シフトレジスタRDの内容を順次端末
側へ送出する。
Figure 5 explains the bit shift processing when sending data from the exchange side to the terminal, in which 8 bits of data on a predetermined channel (channel captured for the originating terminal) are extracted from the transmission path, and the line Send to circuit LC. In the line circuit Lc', the 8 bits of bits are held in the shift register RC by the clock ■, and then the synchronous pit F is stored in the shift register RD by the clock ■, and the contents of the register RC are shifted by 1 bit and transferred to the shift register RD. Store. Based on the clock (2), the contents of the shift register RD are sequentially sent to the terminal side.

斯して、交換機側で伝送路インタフェースをとる場合に
音声呼と同様に何んら識別することなく、7ビツトのデ
ータに制御用ピットノ)を付与することで、データ端末
からのデータブロックをSビ。
In this way, when establishing a transmission line interface on the exchange side, data blocks from data terminals can be transferred to S by adding control pitnos to the 7-bit data without any identification, similar to voice calls. B.

トを破壊することなく、伝送路へ送出可能となる。can be sent to the transmission path without destroying the port.

こζでクロック■、■は時分割ハイウェイへ挿入し、抽
出するタイミングをとるもので、例えば交換機内のハイ
ウェイが32多重(2,048mb/S)とすると、ゲ
ート回路G2. G、はとの32回線に同期して制御さ
れることになる。またクロック■■は端末終端装置DC
Eとライン回路LC間の伝送ブロック曝位でタイミング
をとるものでゲートGI、G4はそのタイミングによシ
開閑の制御がされる。
In this ζ, the clocks ■ and ■ are inserted into the time-division highway and set the timing for extraction.For example, if the highway in the exchange is 32 multiplexed (2,048 mb/S), the gate circuit G2. It will be controlled in synchronization with the 32 lines of G and Hato. Also, the clock ■■ is the terminal terminal equipment DC.
The timing is determined by the exposure of the transmission block between E and the line circuit LC, and gates GI and G4 are opened and closed according to this timing.

第6図は、このディジタル交換機のハイウェイHWの例
を示したもので、1フレーム(125μg)が32多重
(32回線)され各タイムスロッ)TSO〜TS、31
は8ビツトで構成される。
Figure 6 shows an example of the highway HW of this digital exchange, in which one frame (125 μg) is multiplexed 32 times (32 lines) and each time slot) TSO to TS, 31
is composed of 8 bits.

尚、ピット処理としては上記実施例では、ビットフット
処理を行ったが、これに限定されるものでなく、第7図
に示す如く、加入者線インタフェースのフォーマットの
Fビットの位置が、伝送路インタフェースのフォーマッ
トの制御ピット(B)に相当する位置へ移動する変換で
あってもよい。
In the above embodiment, bit foot processing is performed as pit processing, but it is not limited to this. As shown in FIG. 7, the position of the F bit of the subscriber line interface format is It may also be a conversion to move to a position corresponding to the control pit (B) of the interface format.

また、本実施例ではライン回路LCでビット処理を行う
例で説明したが、交換機−伝送路間のインタフェース回
路(例えばトランク)にビット処理を備えてもよい。
Further, in this embodiment, an example in which bit processing is performed in the line circuit LC has been described, but the bit processing may be provided in an interface circuit (for example, a trunk) between an exchange and a transmission line.

また、本実施例では伝送路インタフェースとしてPCM
24Bの構成で説明したが、1チヤネル内の1ビツトを
交換制御用として使用する伝送方式であれば本発明の適
用し得ることはいうまでも々い0 (7)発明の詳細 な説明したように、本発明によれば、ディジタル交換機
に接続された多重化PCM伝送路をもつ交換システムに
おいて、伝送路インタ7エーxと異なるインタフェース
を有するデータ端末を接続するとき釦も、交換制御上使
用する信号ピット(B)によシデータ端末側で必要とす
る信号ピッ) (S)が破壊されることがなく、また交
換機において音声呼とデータ呼を識別する制御を不要と
し、音声呼と同様の交換処理で、データ呼を扱うことを
可能とする。
In addition, in this embodiment, PCM is used as the transmission line interface.
Although the explanation has been made using a 24B configuration, it goes without saying that the present invention can be applied to any transmission system that uses one bit in one channel for switching control. According to the present invention, in a switching system having a multiplexed PCM transmission line connected to a digital exchange, the button is also used for switching control when connecting a data terminal having an interface different from the transmission line interface 7Ax. The signal pit (B) does not destroy the signal pit (S) required on the data terminal side, and eliminates the need for control to distinguish between voice calls and data calls at the exchange, allowing the same exchange as for voice calls. Processing allows data calls to be handled.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は伝送路インタフェースの信号フォーマットを示
す図、第2図は加入者線インタフェースの信号フォーマ
ットを示す図、第3図は本発明を適用した交換システム
構成図、第4図、第5図は本発明の信号ピット処理方式
を説明する実施例の図、第6図は交換機のハイウーエイ
HWの構成例を示す図、第7図は信号ピット処理の他の
例を示す図である。 DTE:データ端末 DCE:端末終端装置 LC;ライン回路 EXI ;ディジタル交換機 DT ;トランク EX2 ;対局ディジタル交換機
Figure 1 is a diagram showing the signal format of the transmission line interface, Figure 2 is a diagram showing the signal format of the subscriber line interface, Figure 3 is a diagram showing the configuration of a switching system to which the present invention is applied, Figures 4 and 5. 6 is a diagram showing an example of the configuration of a highway HW of an exchange, and FIG. 7 is a diagram showing another example of signal pit processing. DTE: Data terminal DCE: Terminal termination equipment LC; Line circuit EXI; Digital exchange DT; Trunk EX2; Opposite digital exchange

Claims (1)

【特許請求の範囲】[Claims] データ端末とディジタル交換機間のデータ送受信は端末
轟号ビットを含むデータフォーマットで行なわれ、前記
ディジタル交換機と他局とのデータ送受信は交換制御ビ
ットを含む多重化されたPCM伝送路をインタ7エー玉
として行なわれる交換システムにおいて、前記信号ビッ
ト位置を前記交換制御ビット位置と異なる位置に入換え
る手段を設けたと七を特徴とする信号ビット処理方式。
Data transmission and reception between a data terminal and a digital exchange is performed in a data format that includes a terminal signal bit, and data transmission and reception between the digital exchange and other stations is performed using an inter-7A transmission line that includes an exchange control bit. 7. A signal bit processing method according to claim 7, further comprising a means for changing the signal bit position to a position different from the exchange control bit position in an exchange system performed as an exchange control bit.
JP1582083A 1983-02-02 1983-02-02 Processing system of signal bit Granted JPS59141897A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1582083A JPS59141897A (en) 1983-02-02 1983-02-02 Processing system of signal bit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1582083A JPS59141897A (en) 1983-02-02 1983-02-02 Processing system of signal bit

Publications (2)

Publication Number Publication Date
JPS59141897A true JPS59141897A (en) 1984-08-14
JPH0544240B2 JPH0544240B2 (en) 1993-07-05

Family

ID=11899484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1582083A Granted JPS59141897A (en) 1983-02-02 1983-02-02 Processing system of signal bit

Country Status (1)

Country Link
JP (1) JPS59141897A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5289019A (en) * 1976-01-20 1977-07-26 Nec Corp Circuit supervising system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5289019A (en) * 1976-01-20 1977-07-26 Nec Corp Circuit supervising system

Also Published As

Publication number Publication date
JPH0544240B2 (en) 1993-07-05

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