JPS59140697A - Semiconductor detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor detecting circuit which has a high-speed operation and low power consumption with a simple constitution by using a diode structure connecting the gate and the drain of an MOS transistor(TR) as a constant voltage source connected with the source of the MOS transistor for initialization. CONSTITUTION:The reset pulse is impressed to a terminal 6 to reset the potential of a bit line 1. Here the potential is set at VDD-VTP for the line 1 to be reset if the mutual conductance of TRp7 is set at sufficiently large value. While the gate-source voltage difference is kept off by the threshold voltage of the TRp7 in a reset mode as long as the threshold voltage of a TRp2 is set equal to the TRp7. If the mutual conductance ratio of a CMOS reverse amplifying circuit is set large with p channel and small with n channel respectively, the identification potential VR of the reverse amplifying circuit approximates to VDD-VTP. Here if VR=(VDD-VTP)-DELTAV(DELTAV: microvoltage) is satisfied, the read-out time is set as tauRD=C1 or V/Inl. Thus the read-out time tauRD is reduced compared with the conventional value. Here VTP is the threshold voltage of the TRp7 and Inl is the ON current of n1.

Description

[Detailed description of the invention] Industrial applications The present invention is a semiconductor structured circuit (hereinafter referred to as LSI).

It particularly relates to high density memory sense amplifiers.

Conventional Structures and Problems Various efforts have been made to shorten the so-called access time (the time from when an input address signal is applied until the contents of the memory are read) in LSI memories. In particular, it is important to shorten the so-called read time τRDt'', which is the time required for the detection circuit to identify a change in the potential of the bit line, which changes depending on the contents stored in the accessed memory cell.

FIG. 1 shows an example of a detection circuit using the simplest CMOS inversion circuit. n in the figure, + n2
+ n51n4 is N channel m08) transistor pl
- p2UP channel MO8) transistors are shown. Each n + * n 2 I n s represents a transistor within a memory cell. n4. An inverting amplifier is formed at the terminals p, .

p is a circuit element for setting the initial potential of the bit line 1.

In general, since the bit line 1 is long and has many elements connected to it, it is considered that an isometrically large stray capacitance C1 is connected to the ground. The operation of this circuit will be explained next. First, immediately before the access operation starts, the potential of bit line 1 (i71J is set). In this example, in order to raise the power supply voltage to the level (potential of terminal 7), a pulse as shown in Fig. 2 is applied to terminal 6, and transistor p , ion.Direct current flows momentarily from the power supply, and the equivalent capacitance c1 is charged.

Next, after charging is completed, transistor p+k is turned off again.
Access is started by setting one of word lines 2 to 4 to a high potential. In this example, word line 2 is accessed as shown in FIG. As a result, nl is turned on, C1 starts discharging, and the potential of bit line 1 decreases. Note that even if the word lines 2 to 4 are accessed, the potential of the bit line 1 does not drop if there is no transistor. In order to improve the total integration, the size of t Rungis jtn is generally extremely small, so nl
The ON resistance of bit line 1 is also large, and the potential of bit line 1 decreases only slowly. On the other hand, the detection circuit has a discrimination potential vR determined by the ratio of the mutual conductances of P2 and n4, and when the input potential is less than VR, the output potential is a high potential (i.e. "
1”), the output potential is a low potential (i.e. “0
”). In this case, by making the mutual conductance of n4 relatively small and increasing the mutual conductance of p2, vR becomes high. However, in principle, vR has an upper limit that can be expressed by the following formula.

vR<vDD 'TQ2) "HHH'-++++
++ (1) However, vDD is the potential of the power supply, vT P (
2) is the threshold voltage of transistor p2.

FIG. 2 shows changes in the potential of the bit line 1 and changes in the potential of the output terminal 6. In the figure, B is the potential of bit line 1, and B2 is the gate voltage of transistor n1.

B5 is the potential of the output terminal 5, and 86 is the gate voltage of the transistor p. In this case, the read time τ is expressed by a quintic equation because the bit line potential change is approximated by a straight line.

”RD = C+ (vDD-vR) / I,,
--(2) However, ■. , Fi) ON of contactor n,
It is an electric current.

This detection circuit has a very simple configuration and has low power consumption because there is no direct current path when the identification operation is completed (when the potential of the pick wire 1 becomes near the ground potential).
This is effective for creating J i, but the time τRD, which occupies a large portion of the above-mentioned access time, does not become small as shown in the following equation (3).

It is rarely used in high-speed LSI memories.

τRD>C1(vDD-vRmax)/In1-C7v
, P/In1 (width)) The detection circuit of a high-speed LSI memory employs a circuit as shown in Fig. 3, taking into consideration the simplicity and power consumption of the circuit.

To briefly explain the operation of this circuit, transistor n5.
6*p5*P4+ p5 constitutes a differential amplification gain, and from the relationship between the potentials v and N of the bit line 1 and reference input terminal 9, which are input terminals, and vREF, Vl,>VRE, and Vout low potential. When v1N<vREF, v.ut becomes high potential.

However, Vout is the potential of the output terminal 8.

Next, the transistor "6" 6 is a signal DC potential shift circuit 1 normal voutFi, V3vDD-vD
Since it is in the range of D, this is shifted to the lower potential side as a whole and matched so that it changes in an appropriate potential range with respect to the identification potential vR of the inverting amplifier circuit composed of the next stage transistor "4" 2. let For example, %VDDl vOut
l Vl)p VR; In the case of 17% VDD, the potential v(,.) of the terminal 10 is taken as '/'a VDD Z V6o) Z % VDn.

In this circuit configuration, the final detection output v5 of the output terminal 6 responds quickly when the potential is set slightly lower than vREFfI:vDD, so that the above-mentioned readout time τRD can be significantly shortened. However, one circuit configuration is complicated with about four times the number of transistors, and since there is a DC current path even after the identification operation is completed, current flows, increasing power consumption.

OBJECTS OF THE INVENTION The present invention solves the conventional problems as described above, and provides a semiconductor detection circuit with a simple circuit configuration, high speed, and low power consumption.

Structure of the Invention In the present invention, the source of the MOS transistor for initial setting is not directly connected to the power supply, but is connected to a constant voltage source that generates a potential close to the discrimination potential of the inverting amplification circuit. By using a diode structure in which the gate and drain of a MOS transistor (MOS transistor) having the same threshold voltage as the amplifier components is used, a high-speed semiconductor detection circuit is realized with a simple configuration. The basic components of the present invention are shown below. Compared to the conventional detection circuit shown in FIG. 1, only a MOS transistor p7 is added. The gate and drain of p7 are connected in common to the source of a reset MOS transistor p.

To explain the operation of this circuit, a reset pulse is applied to the terminal 6 as in the conventional example shown in FIG.
Although the potential of +1 is reset, the bit line 1 is not reset to vDD in the circuit of this embodiment.

Generally, the current and voltage characteristics of a MOS transistor with a common drain and gate are as shown in FIG. If the mutual conductance of transistor p7 is made sufficiently large, this circuit is equivalent to a constant voltage source of the output voltage (vDD-vTP). However, -vTP is the threshold voltage of p3. Therefore, the potential of bit line 1 to be reset is (vDD-TTP
). -Construct a million-inverting amplifier circuit. Assuming that it is the same as the threshold value kp of p2 of the P channel in the 0M08 circuit,
In the reset state, the potential difference between the gate and the source is a threshold voltage of p7, so it is in the OFF state. Similar to the conventional example shown in Figure 1, the mutual conductance ratio of the CMOS inverting amplifier circuit is P
If the channel is made large and the N channel is made small, the discrimination potential vR of the inverting amplification circuit becomes close to (vDD'TP). Now, if vR"" (vDD V7p) IV CIV two minute 'fl pressure) - (4), then the readout time τRD is rRD ""' C1 (vRE8ET - vR)/
Engineering n+-01((vDD-vTP)-(vDD-vT
Pl+Δv]. .

-Q, ΔV/I. , ・・・・・・・・・・・・
([5) However, vRE8ET is the reset potential of bit line 1, and line-11' is (vDD-VTP)
It is. Therefore, TRn becomes shorter as shown in FIG. 6 compared to the case of FIG.

All the explanations in Section 1 assume that the MOS transistor of the memory cell is of N-channel type, but conversely, if it is of P-channel type, bit line 1 must be reset to the potential of (v88+vTN). Therefore, a detection circuit as shown in FIG. 7 in which the P channel and N channel are reversed can similarly realize a high speed detection circuit with low power consumption.

One sword, many detection circuits p20'"40" pH1
When ``41''p22'' 42 are connected in parallel, it is sufficient to supply the potential to one MOS transistor p3te (vDD-vTP) all together as shown in FIG.

Note that the transistor p. 'pN' Pi2 corresponds to the transistor p.

As is almost clear from the detailed description of the invention, the semiconductor detection circuit of the present invention is extremely important because it is capable of detecting signals at extremely high speed despite its simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a conventional detection circuit, FIG. 2 is a voltage waveform diagram of various parts showing the operation of the detection circuit of FIG. 1, and FIG. 3 is an equivalent 1ρ1 circuit diagram of another conventional detection circuit. Fig. 4 is an equivalent circuit diagram of the detection circuit of the present invention, Fig. 5 is a current-voltage characteristic diagram of a MOS transistor whose gate and drain are all common, and Fig. 6 is a voltage at each part showing the operation of the detection circuit of Fig. 4. FIG. 7 is an equivalent circuit diagram of another embodiment of the detection circuit of the present invention, and FIG. 8 is an equivalent circuit diagram of still another embodiment of the detection circuit of the present invention. 1...Bit line, 2, 3, 4--Code line, p, ~p7...P channel transistor, n, ~n4...H channel transistor . Figure 1 Figure 2 Figure 413? 34 HA55! ! + Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] P-channel and N-channel enhancement type 3 (
O5) Between the input terminal of the inverting amplifier circuit and the power supply, an inverting amplifier circuit of 0MO8 using transistors and a potential setting circuit in which the first and second MOS transistors of the same channel type and enhancement type are connected in series. and the drain of the first MOS transistor is connected to the input terminal of the inverting amplifier, the drain and gate of the second MOS transistor are connected to the power supply, and the source of the second MOS transistor is connected to the power supply. and the first MOS
A semiconductor detection device characterized in that the gate of the transistor is used as a tf pulse input terminal, and the threshold voltage of the second MOS transistor is set to approximately N- with the threshold voltage of the same channel type MOS transistor in the inverting amplifier circuit. circuit.