JPS59135555A - Program tracing device - Google Patents

Abstract

PURPOSE:To confirm whether the instruction that is contained in a module, a subroutine, an interruption processing or an optionally designated program range are executed by a CPU, by distinguishing and displaying the traced results for each designated address range. CONSTITUTION:An instruction memory address 302 delivered from a CPU300 is written to a region where a trace memory 340 is continuous. A reading control part 350 delivers a reading control signal 351 and then delivers in turn the contents of the memory 340 from the head. A comparator part 360 compares the contents of the memory 340 with address lower and upper limit values 361 and 362 delivered from an address range designating part 363. That is, it is decided that the output A of the memory 340 is within an address range designated by an address range designating 363 when the output A is defined as the address lower limit value <=A<=address upper limit value. Then the output A is sent to the column position corrsponding to the part 363 at a display part 390. Thus it is possible to display the program flow in the form of a timing chart and for each module, subroutine, interruption processing program and optional address respectively. This improves the debugging efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a 7° program trace device that displays the execution status of a program.

Configuration of conventional examples and their problems In recent years, with the advancement of computer hardware technology represented by microcomputers, the amount of program development has become enormous. Debugging is the most time-consuming task. In order to confirm that the created program correctly satisfies the original requirements, a program developer performs various checks, corrections, and corrections, and debugs the program. In order to perform this check efficiently, what is called a program development device or debugging device has traditionally been used, and the program developer can create a single file by inputting and outputting data from each building to and from the debugging device. Check the validity of the program inside.

Note that the program trace referred to here means a function of displaying which address of the program is executed by the central processing unit (hereinafter referred to as CPU). A conventional program tracing device will be explained below.

Figure 1 is a configuration diagram of a conventional program trace device.
(+00) is CPU, (101) is CPU (100)
The execution control signal J102) that controls the execution and stopping of C
The instruction memory address output by PU (IQQ), (
110) is an instruction memory that inputs an instruction memory address (102) and outputs an instruction (111), and (120) is a CP
The basic clock generator that outputs the basic clock (+213) of U (100), (+30) is the instruction memory address (
a write control unit that outputs a write control signal (131) for writing (102) into the trace memory (140);
[]) displays the contents of the trace memory (+40) on the display section (1
This is a continuous output control unit that outputs a readout control signal (151) to be sent to (60).

The conventional program tracing device configured as described above will now be described in detail.

First, the CPU (+00) to be traced enters the execution state when the execution control signal (+01) is activated.

Instruction memory address (102) to instruction memory (110)
Send to. Instruction memo! J (110) sends the memory contents corresponding to the input instruction memory address (+02) to the instruction (111) to the CPU (100). CPU
(100) Interpret and execute the id command (111). Thereafter, the CPU operations continue in this order, and the execution control signal (1
01) - inactive, L CPU (100)Ia
Stop f le. When the CPU (100) is in the execution state, that is, the execution control signal (101) is active, the write 5 control unit (+30)
outputs a write control signal (151) synchronized with the basic clock (121) of the CPU. This write control signal (
+31), the instruction memory address (+02) is written to the trace memory (140) every basic clock (121). The write control signal (131) is sent to the trace memory (1
40), and is incremented by 1 each time this FL/SHA instruction memory address (102) is entered into the trace memory (140). Therefore, the instruction memory address (
102) are written to a continuous area of the trace memory (140).

On the other hand, when the execution control signal (101) is changed from active to inactive, the CPU (100) enters a stopped state. At the same time, the write control unit (+30') also stops outputting the write control signal (131) because the execution control signal (+01) becomes inactive, and trace memo! Writing to J (1!10) stops. After this, the successive control unit (150) outputs the successive control signal (+51
), the contents of the trace memory (140) are read out sequentially from the beginning and sent to the first display section (160).

The display unit (160) applies appropriate formatting to the content received from the trace memory (140) and displays it externally.

FIG. 2 shows an example of the display on the display section (160). In Figure 2, (201) is a 4-digit hexadecimal number indicating the address of the trace memory (140) + (202) is the display delimiter signal, and (203) is the address (201) of the trace memory (140). The content held, i.e. CPU (1
00') outputs the instruction memory address (10
2). (204) is a special symbol for CPU (100
) has stopped just before this, that is, immediately after executing the instruction whose instruction memory address (102) is ``0247'' in hexadecimal.In the example in Figure 2, the CPU (1C
The address of the instruction memory (1110'') that was continuously executed by IO) is ``0123''.

'0124', '0125',...,'0
1.85","0246".

"0247" (all hexadecimal numbers).

However, in the above configuration, the program.

In other words, although it is difficult to grasp the order of execution of instructions,
The problem is that it is difficult to see what kind of relationship the instruction memory address (203) displayed at 0) has with other instruction memory addresses. For example, if there is a discontinuity in the values of the displayed instruction memory address (203'), is the reason for this discontinuity due to a branch instruction?

It is difficult to determine from the display whether it is due to a sub-IV-chin call instruction or an interrupt. Therefore, in order to make this determination, the conventional method has the disadvantage of requiring the troublesome task of frequently comparing the program list and the display.

Purpose of the Invention The present invention eliminates the need to compare the display section and the program list.
What modules and subroutines does the CPU use?

It is an object of the present invention to provide a program tracing device that can confirm whether interrupt processing or instructions included in an arbitrarily specified program range have been executed.

Composition of the Invention The program tracing device of the present invention includes a trace memory for storing CPU address signals, a trace memory write control section, a trace memory read control section, an address range specification section, and a trace memory content and address range specifying section. A comparison section that compares the contents of the address range specification section and a display section that displays the comparison results are provided.

The program is configured to display trace results separately for each specified address range.

The present invention is characterized in that the program developer is immediately informed of the correspondence between the instruction execution process and the program structure simply by looking at the display on the display unit.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 6 shows a block diagram of a program tracing device in an embodiment of the present invention.

In Figure 6, + (300) is the CPU to be traced.
.

(301) is an execution control signal that controls execution/stop of the CPU (300), and (302) is an instruction memo output by the CPU (300)! J7FV7. % (310) is an instruction memory that inputs the instruction memory address (302) and outputs the instruction (6th), (320) is the basic clock generator that outputs the basic clock (321) of the CPU (300), (
330) is the instruction memory address (302) fc) Race memo! A write control section outputs a write control signal (331) for writing to J (340), (350) is a trace memo! This is a read control unit that outputs a continuous control signal (351) for reading the contents of J (340).

A comparator (V.-5C560) compares the address lower limit value (361) and address upper limit value (362) output by the address range designator (363) with the contents of the trace memory (340). (370) and (38,9) are comparison sections similar to comparison section (360), (575) is an address range specification section that outputs the address lower limit [(371) and address upper limit value (372), and (583) is Address lower limit value (
381) and an address range specification section that outputs the address upper limit value (382).

(390) is the comparison part (360) (370) (380)
This is a display unit that formats and displays the output of .

The TM operation of the program tracing device of this embodiment configured as described above will be explained below.

The CPU (300) maintains an execution state if the execution control signal (301) is active, and remains in a stopped state if it is inactive. First, when the execution control signal (301) is active, ie.

When CPU (,500) is in execution state, CPU (30
0) repeats the sequence from ■ to ■ below.

That is, ■ Address of the next instruction to be executed by the CPU (300).

In other words, the instruction memory address (302)' is set to the instruction memory address (302)'.
10).

■ The instruction memory (310) is the instruction memory address (30
The memory contents corresponding to 2) are output as an instruction (311).

■ The cpU (300) inputs an instruction (311), interprets it, and executes it.

Nao, the operation from ■ to ■ is the basic clock generation section (320
') is performed in synchronization with the basic clock (321) output.

On the other hand, if the CPU (300) is in the execution state, that is, the execution control signal (301) is active, the write control unit (350) receives a write control signal (33) synchronized with the basic clock (321).
'l) is output to the trace memory (34Dlc). This write control signal (331) causes the instruction memory address (34Dlc) to be output.
02) is a trace memory (340) [
written. The write control signal (331) contains the address of the trace memory (340''), which is incremented by 1 each time the instruction memory address (302) is written to the trace memory (340).
The instruction memory address (302) output by IJ0) is written in a continuous area of the trace memo IJ (340).

Next, when the execution control signal (301) is changed from active to inactive, the CPU (300) enters a stopped state. simultaneous! Since the execution control signal (301) becomes inactive, the /c write control unit (330) also stops outputting the write control signal (331) and stops writing to the trace memo 'J (340). At this time, the trace memory (340) of the kite is stored in the CPU (300
) outputs the instruction memory address (30
This means that you have memorized the series 2).

Next, the read control unit (350) outputs a continuous control signal (351).
Output and trace memo! Output the contents of J (34[1) in order from the beginning. The comparator (360) compares the contents of the trace memory (340) output to number j as described above.

The address F limit value (361) and address upper limit value (362) output by the address range specifying section (363) are compared as follows. That is, when the output of the trace memory (340) F, etc. is A, if the following condition (address lower limit ≦A ≦address upper limit II) is satisfied, this A is assigned to the address range specifying section (
363) is within the specified address range, it is sent to the column position corresponding to the address range specification section (363) of the city 1 display section (390). If the first equation is not satisfied, the comparison unit (360) does not send A to the display unit (390). The comparison units (370) and (380) also perform the same operation as the comparison unit (360). Therefore, from the comparison section (360) to the display section (3
It is possible that A that is not sent to the comparison section (370) or (380) is sent to the display section (390). However, the address range specification part (363) 'a (
It is assumed that there are no friendly portions in the range specified by 373)% and C583).

FIG. 4 shows an example of the display when the above operation is performed on all the contents of the trace memo') (340).

In FIG. 4, (401) is a symbol string indicating that the row is the lower limit address value, and (402) (l-1: is a symbol string indicating that the row is the upper limit address value). (405) (
405) (407) are address range specification parts (
566) (376) (383) output the address lower limit value, (404) (406) (408) are the address range specification part (36m), (373), (38) respectively.
3) is the upper limit value of the address to be output. All numbers are hexadecimal. (409) is the trace memory (340
) address, (41Q) is a delimiter. In the example shown in Fig. 4, the contents traced first, i.e., the contents of address 0 of the trace memory C540) <411), are the lower limit value of the address (403) and the upper limit value of the address (404). range, so it will be displayed in the column directly below them. Trace memo as well! J (
The contents (412) of the trace memory (340) whose address value is address 6 are displayed in the center column, and the contents (413) whose address value is address E of the trace memory (340) are displayed in the right column. Note that (414) is a symbol string indicating the child at which cpU (300) stopped immediately before.

The display example in FIG. 4 displays the contents of the trace memory (340) from the beginning, but compared to the conventional example, it is easier to understand the structure of the address transition of executed instructions. I know there is. Therefore, (406) (404
) (405) (406) (407) (408) indicates the subroutine range, the line whose display column position has changed is the line where the subroutine call or return from the subroutine is made. You can understand the timing of the program, and you can understand the flow of the program at a glance without looking at the program lift.

Similarly, if the above address range indicates the range of the interrupt processing routine, the timing at which one interrupt occurred can be seen at a glance, and the display results can be read one by one as in the conventional example. Another advantage is that the troublesome work of searching for the start address of a chin is completely unnecessary.

As described in the detailed description of the invention, according to the program tracing device of the present invention, since a comparison section and an address range specification section of the conventional program tracing device MIC trace memory are added, the flow of the program can be divided into modules, subroutines, and modules. It is now possible to display timing diagrams in interrupt processing program units and arbitrary address units, making debugging f'
F: It becomes possible for the program developer at work to easily understand the flow of the program, which greatly contributes to improving the efficiency of depacking work.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional program tracing device.
FIG. 2 is an explanatory diagram of a display example of a conventional program trace device, FIG. 6 is a block diagram of a program trace device according to an embodiment of the present invention, and FIG. 4 is an explanatory diagram of a display example in the present invention. . (300)... central processing unit, (330)...
...Write control unit, (340)...Trace memory,
(350) ... successive control section, (360) (370
) (380)...Comparison section, (363) (373)
(383)... Address range specification section, (590)
・Display Department Agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. A trace memory that stores an address signal of a central processing unit, a write control section of the trace memory, a continuation side/bowl section of the trace memory, an address range specification section of the central processing unit, and a write control section of the trace memory. A program configured to include a comparison section that compares the contents of a memory and the contents of the address range specification section, and a display section that displays the output of the comparison section, and to display trace results separately for each specified address range. tracing device.