JPS5913424A - Gate driving circuit of gate turn off thyristor - Google Patents

Gate driving circuit of gate turn off thyristor

Info

Publication number
JPS5913424A
JPS5913424A JP57123552A JP12355282A JPS5913424A JP S5913424 A JPS5913424 A JP S5913424A JP 57123552 A JP57123552 A JP 57123552A JP 12355282 A JP12355282 A JP 12355282A JP S5913424 A JPS5913424 A JP S5913424A
Authority
JP
Japan
Prior art keywords
gate
thyristor
turn
switch
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57123552A
Other languages
Japanese (ja)
Inventor
Takashi Kobayashi
隆 小林
Yoshiyasu Hiroi
広井 吉保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57123552A priority Critical patent/JPS5913424A/en
Publication of JPS5913424A publication Critical patent/JPS5913424A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region

Landscapes

  • Power Conversion In General (AREA)
  • Thyristor Switches And Gates (AREA)

Abstract

PURPOSE:To turn on and off a gate turn off (GTO) thyristor only by one power supply with a simple constitution by using a switching circuit interlocked with the gate and cathode side of the GTO thyrustor respectively. CONSTITUTION:When the GTO thyristor Q1 is to be turned on, a switch SW1 is opened and a switch SW2 is closed. Since positive voltage applied to a terminal T1 is applied to the gate of the thyristor Q1 at the time, the GTO thyristor is turned on between the anode A and cathode K and current is made flow into a load RL by the voltage of a terminal T2. When the thyristor Q1 is to be turned off, the switch SW1 is closed and the switch SW2 is opened. Consequently, current flowing into the cathode K is interrupted and made flow out immediately from the gate G through a closed contact of the switch SW1 and the thyristor Q1 is rapidly turned off.

Description

【発明の詳細な説明】 本発明は、ゲート・ターン・オフ(Gate−Turn
−Of f 、 G T O)サイリスタと呼ばれるゲ
ート電圧の制御によりアノード電流を0N−OFF可能
なスイッチングサイリスタのゲートドライブのた従来前
記ゲート・ターン・オフ・サイリスタのドライブ回路と
しては種々のものがあったが、これらは2電源を要した
り、回路構成が複雑になったり、或いはスイッチング可
能な電流容量が取れなかったりしていずれも実用上の制
約となる問題があった。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides gate-turn off
-Off, GTO) There are various drive circuits for the gate turn-off thyristors, including gate drive circuits for switching thyristors, which are capable of turning the anode current ON and OFF by controlling the gate voltage. However, these devices require two power supplies, have a complicated circuit configuration, or cannot provide a switching current capacity, all of which pose practical limitations.

本発明は前記各種の欠点を除去したドライブ回路を提供
することを目的とする。
An object of the present invention is to provide a drive circuit that eliminates the various drawbacks mentioned above.

以下本発明をその実施例により図面と共に説明する。Hereinafter, the present invention will be explained by way of examples thereof with reference to the drawings.

第1図において、Qlはゲート・ターン・オフ・サイリ
スタで、A、に、Gはそれぞれそのアノード、カソード
、ゲートである。RLは抵抗等の負荷、R1は抵抗、S
Wl、SW2 、は互に連動して接点が開閉するスイッ
チで、SWlとSW2の接点の開放は片方が開の時は他
方が閉というように逆関係で動作するようになっている
。T1゜T2はそれぞれ正の直流電源電圧が印加される
電源端子で、これらは共通電圧を印加しても良い。
In FIG. 1, Ql is a gate turn-off thyristor, and A, G and G are its anode, cathode and gate, respectively. RL is a load such as a resistor, R1 is a resistor, S
Wl and SW2 are switches whose contacts open and close in conjunction with each other, and the contacts of SWl and SW2 operate in an inverse relationship such that when one is open, the other is closed. T1 and T2 are power supply terminals to which a positive DC power supply voltage is applied, and a common voltage may be applied to these terminals.

次に動作を説明する。ゲート・ターン・オフ・サイリス
タQ1をオンにするには、スイッチSW1を開に、まだ
スイッチSW2を閉とする。この時、電源端子T1に印
加された正電圧が抵抗R1を経由してゲート・ターン・
オフ・サイリスタQ1のゲートに印加されるのでター′
ト・ターン・オフ・サイリスタはアノードAとカソード
にの間がオンとなり、電源端子T2に印加された電圧に
より負荷RLに電流が供給される。次にゲート・ターン
・オフ・サイリスタQ1をオフにするには、スイッチS
W1を閉にすると共に、スイッチSW2を開とする。こ
の時、今までカソードKを流れていた電流は、スイッチ
SW2が開となるため流れることが出来ず、ゲートGか
らスイッチSW1の閉じた接点を介して早急に流出する
ので、ゲート・ターン・オフ・サイリスタQ1を速やか
にオフの状態とすることができる。
Next, the operation will be explained. To turn on gate turn-off thyristor Q1, switch SW1 is open while switch SW2 is closed. At this time, the positive voltage applied to the power supply terminal T1 passes through the resistor R1 to the gate turn.
Since the voltage is applied to the gate of off-thyristor Q1, the
The turn-off thyristor is turned on between the anode A and the cathode, and current is supplied to the load RL by the voltage applied to the power supply terminal T2. Next, to turn off the gate turn-off thyristor Q1, switch S
W1 is closed and switch SW2 is opened. At this time, the current that has been flowing through the cathode K until now cannot flow because the switch SW2 is open, and immediately flows out from the gate G through the closed contact of the switch SW1, so the gate turns off. - Thyristor Q1 can be quickly turned off.

即ち前記実施例においては、スイッチSW1とSW2の
接点を互に逆の状態で連動してオン・オフさせることに
よってターンオフ時に、ゲート・ターン・オフ・サイリ
スタQ1のカソード側を切り離す一方で、ゲート側を短
絡に近い状態で接地するだめゲート電流の排出が速やか
に行われ、しかも構造が簡単で、−電源(ゲートが)で
済む利点を有する。
That is, in the embodiment described above, the contacts of the switches SW1 and SW2 are turned on and off in a mutually opposite manner, thereby disconnecting the cathode side of the gate turn-off thyristor Q1 at the time of turn-off, while disconnecting the cathode side of the gate turn-off thyristor Q1. Since the gate current is grounded in a state close to a short circuit, the gate current can be quickly discharged, and the structure is simple, and the gate has the advantage of requiring only a -power source (gate).

第2図は第2の実施例を示すものである。同図において
Q2はpnp)ランリスタ、Q3はnpn)ランリスタ
FIG. 2 shows a second embodiment. In the figure, Q2 is a pnp) run lister, and Q3 is an npn) run lister.

R2は抵抗、T3はゲートパルスの入力端子で、他の第
1図と同じ符号は同一の名称を表わす。この実施例は第
1図の構成で、スイッチS Wl、 S W2に代りそ
れぞれpnpとnpnのスイッチングトランジスタを用
いた例であって、ゲートパルスの入力端子T3に電圧が
■1と72間で変化するスイッチングパルスを印加すれ
ば、先ず、電圧v2の正パルスによりトランジスタQ2
はオフ、またトランジスタQ3はオンになるので、ゲー
ト・ターン・オフ・サイリスタQ1のゲートに正電圧が
印加されてターンオンすると共に、そのカソードはトラ
ンジスタQ3のコレクタ・エミッタ間が低下抵抗を呈し
、負荷電流が流れる。次にゲートパルスの入力端子T3
のパルス電圧が■1に低下すると、今度はトランジスタ
Q2がオンになると共に、トランジスタQ3はオフにな
り、前記第1図に示した実施例の場合と同様にターンオ
フになる。上記構成によれば、ゲートパルスの入力端子
をパルス波形で制御することにより簡単にゲート・ター
ン・オフ・サイリスタをオンオフ出来る利点を有する。
R2 is a resistor, T3 is a gate pulse input terminal, and the same reference numerals as in other parts of FIG. 1 represent the same names. This embodiment has the configuration shown in FIG. 1, but uses pnp and npn switching transistors in place of the switches SWl and SW2, respectively, and the voltage at the gate pulse input terminal T3 changes between 1 and 72. When a switching pulse is applied, first, a positive pulse of voltage v2 causes transistor Q2 to
is off, and transistor Q3 is on, so a positive voltage is applied to the gate of gate turn-off thyristor Q1, turning it on, and its cathode exhibits a reduced resistance between the collector and emitter of transistor Q3, and the load Current flows. Next, gate pulse input terminal T3
When the pulse voltage decreases to 1, the transistor Q2 is turned on and the transistor Q3 is turned off, turning off as in the embodiment shown in FIG. According to the above configuration, there is an advantage that the gate turn-off thyristor can be easily turned on and off by controlling the gate pulse input terminal with a pulse waveform.

この場合ゲートパルスの電圧V1.V2を適当に選び、
或いは抵抗R2の値を選定して、トランジスタQ3のオ
ン電流は出来るだけ大きく、しかもオフ電流をターンオ
フ動作を損わない範囲で大きく設定すれば、ターンオフ
時に、過渡的に大きなスイッチング電圧がトランジスタ
Q3に印加されてこれを破損させることがないようにす
ることが出来る。
In this case, the gate pulse voltage V1. Select V2 appropriately,
Alternatively, by selecting the value of resistor R2 and setting the on-current of transistor Q3 as large as possible and the off-current as large as possible without impairing the turn-off operation, a transiently large switching voltage will be applied to transistor Q3 at turn-off. It is possible to prevent this from being damaged due to the application of a voltage.

第3図は、第3の実施例であって、抵抗R2の代りに抵
抗R3を用い、その一端をトランジスタQ2のエミッタ
側に接続した点でのみ第2図と異なる。上記構成で、ゲ
ート・ターン・オフ・サイリスタQ1をターンオンさせ
るに際して、オフ状態のトランジスタQ2のエミッタ電
圧を抵抗R3ヲ介シてトランジスタQ3のペースに供給
するととによってこれをオンにする一方、ターンオフ時
にも、トランジスタQ2のオンによりそのエミッタ電圧
の低下を検出してトランジスタQ3をオフにするように
したものである。
FIG. 3 shows a third embodiment, which differs from FIG. 2 only in that a resistor R3 is used instead of the resistor R2, and one end of the resistor R3 is connected to the emitter side of the transistor Q2. In the above configuration, when turning on the gate turn-off thyristor Q1, the emitter voltage of the off-state transistor Q2 is supplied to the pace of the transistor Q3 through the resistor R3, and the gate turn-off thyristor Q1 is turned on. Also, when the transistor Q2 is turned on, a drop in the emitter voltage of the transistor Q2 is detected and the transistor Q3 is turned off.

なお前記実施例で、スイッチング素子として、トランジ
スタを使用した場合について説明しだが、これらはFE
T、MOS等の半導体素子を用いて実現することも容易
である。
In the above embodiment, the case where a transistor is used as a switching element is explained, but these are FE.
It is also easy to implement using semiconductor elements such as T and MOS.

以上説明したように本発明によれば、ゲート・ターン・
オフ・サイリスタのゲートとカソード側にそれぞれ挿入
され互に連動して作動するスイッチング回路を使用する
ことにより、ゲート・ターン・オフ・サイリスタのター
ンオン、ターンオフの動作が一電源でしかも簡単な構成
により確実に行えるのでスイッチング電流容量も大きく
取れ、その工業的価値は大である。
As explained above, according to the present invention, the gate turn
By using switching circuits that are inserted into the gate and cathode sides of the off thyristor and operate in conjunction with each other, the turn-on and turn-off operations of the gate turn-off thyristor are ensured with a single power supply and a simple configuration. Since the switching current capacity can be increased, it has great industrial value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によるゲート・ターン・オフ
・サイリスタのゲートドライブ回路の回路図、第2図お
よび第3図は同じく第2.第3の実施例の回路図である
。 Ql・・・・・・ゲート・ターン・オフ・サイリスタ、
Q2・・・・・・第1のトランジスタ、Q3・・川・第
2のトランジスタ、RL・・・・・・負荷。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
51!
FIG. 1 is a circuit diagram of a gate drive circuit for a gate turn-off thyristor according to an embodiment of the present invention, and FIGS. FIG. 3 is a circuit diagram of a third embodiment. Ql...Gate turn off thyristor,
Q2...first transistor, Q3...river/second transistor, RL...load. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
51!

Claims (1)

【特許請求の範囲】[Claims] 直流電圧が印加されるゲートを有し、負荷と直列接続し
たゲート・ターン・オフ・サイリスタと、前記ゲートと
アース間に接続され、ゲートパルスによりオン・オフ制
御される第1のトランジスタと、前゛記タート・ターン
・オフ・サイリスタとアース間に接続され、前記第1の
トランジスタとオン・オフ動作が逆の関係で制御される
第2のトラ
a gate turn-off thyristor having a gate to which a DC voltage is applied and connected in series with a load; a first transistor connected between the gate and ground and controlled on and off by a gate pulse; A second transistor connected between the start-turn-off thyristor and the ground, and whose on-off operation is controlled in an inverse relationship to that of the first transistor.
JP57123552A 1982-07-14 1982-07-14 Gate driving circuit of gate turn off thyristor Pending JPS5913424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57123552A JPS5913424A (en) 1982-07-14 1982-07-14 Gate driving circuit of gate turn off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57123552A JPS5913424A (en) 1982-07-14 1982-07-14 Gate driving circuit of gate turn off thyristor

Publications (1)

Publication Number Publication Date
JPS5913424A true JPS5913424A (en) 1984-01-24

Family

ID=14863421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57123552A Pending JPS5913424A (en) 1982-07-14 1982-07-14 Gate driving circuit of gate turn off thyristor

Country Status (1)

Country Link
JP (1) JPS5913424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024188U (en) * 1983-07-20 1985-02-19 三菱電機株式会社 Gate turn-off thyristor control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024188U (en) * 1983-07-20 1985-02-19 三菱電機株式会社 Gate turn-off thyristor control circuit

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