JPS59133793A - Dial pulse receiver - Google Patents

Abstract

PURPOSE:To reduce the overhead of software which is needed for scan processing by providing a queue buffer memory which stores the count result of a dial pulse or the information on route abort information with correspondence to a circuit number under processing. CONSTITUTION:The multiplex LOOP signal obtained by the time division is supplied to a signal input terminal. A dial pulse counting logical circuit 12 decides whether the LOOP signal to be presently processed in effective or not. If the LOOP signal is effective, a dial pulse is detected from the present LOOP signal and the information obtained in a preceding period. Then the count result is stored in a dial pulse count memory 15. A deciding circuit 17 decides the inter-digit decision and count resignation of dial pulses or a hooking state and then stores the count result on route abort information of dial pulses counted by the circuit 12 into a queue buffer memory 21 with correspondence to the circuit number under processing. The information stored in the memory 21 is read out under the control of a control circuit 19 and via a signal output line 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a dial pulse receiving device for receiving dial pulses in an exchange.

(2) Background and problems Generally, in electronic exchanges, etc., when converting the dial pulse signal sent out when a telephone dial is turned into a dialed number of each digit, for example, a relay circuit receives the change point of the signal, Detection of conversion points, counting of dial pulses, determination between digits (completion determination for one digit), and detection of abandonment are performed under software control. Therefore, the amount of software processing required to receive dial pulses was enormous. Therefore, in a time division switch, a dial pulse receiving device has been developed in which counting of dial pulses, detection of abandonment, and determination between digits are all performed using logic circuits and memory.

FIG. 1 shows an explanatory diagram of a conventional dial pulse receiving device. In the figure, 1-0 to l-N are telephones, 2 is memory, 3 is an interdigit (SP) flag, 4 is a premature abandonment (CAM) flag,
5 represents a pulse counting result storage area, and 6 represents a scan processing section.

The inter-digit flag 3, the mid-term abandonment flag 4, and the pulse counting result storage area 5 are prepared only for the multiple variations of the dial number receiving device.Telephone 1-0゜1-1.
・The dial signal from l-N is counted in a time-division manner by a hardware logic circuit (not shown), and the count result is stored in the pulse counting result storage area 5 for each line number.゛.When the logic circuit receives a dial nockle signal for one digit, it turns on the inter-digit flag 3.Also, if the handset is flagged on during dialing, it is considered to be abandoned midway and the halfway abandonment flag 4 is turned on. On the other hand, the scan processing unit 6 sequentially scans the memory 5 from above under software control,
The information in the pulse count result storage area 5 for which the inter-digit flag 3 is on is read and processed. By reading, the inter-digit flag 3 and the pulse count result storage area 5 are cleared. Further, the mid-term abandonment flag 4 is also scanned at the same time, and if one that is turned on is detected, the dial information regarding that line that has been received up to that point is invalidated.

The principles of counting dial pulses, determining between digits, and detecting abandonment will be explained below using FIGS. 2 and 3.

The LOOP signal of the dial pulse arrives sequentially on each line by time division and is sampled as shown in FIG. 2, and the sampling period for one line is, for example, 4 ms or 13 m5.

The dial pulse signal focused on one line is, for example, signal 7 shown in FIG. 3, and FIG. 3 shows the case where the number of dial pulses is "3". Signal 7 to 4
The signal sampled at nl S is the signal L shown in Figure 3.
It is OOP. This signal LOOP is applied for one period, that is, 4
The signal delayed by ms is the signal LL. Signal LO
When the inverted version of OP is ANDed with the signal LL, the falling edge of the pulse of signal 7 is detected and three count pulses are obtained.

On the other hand, for example, 96 m
This is done by sampling 5. If there is no change in the signal 7 during this 96fils, the signal AP becomes "0", and if there is fcV change, the signal AP becomes "1". Signal AP 95
The signal APLL is delayed by m5. When the result of ANDing the inverted version of the signal AP and the signal APLL becomes rlJ, an inter-digit or mid-digit abandonment is detected. Whether it is between digits or abandoned midway,
Is signal 7 in the LOOP-ON state?
This can be determined by whether it is in the FF' state.

According to the conventional method explained in FIG. 1 above, the greater the multiplicity of the dial pulse receiving device, the more difficult it is to judge between digits, detect mid-term abandonment, and read the result of Goo-He-Le counting through software scanning processing. However, there is a problem that the overhead becomes large.

0) Purpose of the Invention The present invention aims to solve the above-mentioned problems and reduce the software overhead required for the above-mentioned scanning process.7>J%
Together, the objects are to provide a dial pulse receiving device with reduced line costs.

(4) Structure of the Invention In order to achieve the above object, the dial pulse receiving device of the present invention includes a dial pulse counting device that counts the pulses of the diamond pulse signal, in the dial pulse receiving device that receives the diamond pulse signal arriving at the signal pit. A logic circuit and a judgment circuit for detecting gaps between digits and abandonment in the middle are provided, and when the judgment circuit detects gaps between digits or abandonment in the middle, dial pulse counting results counted by the dial pulse counting logic circuit or abandonment in the middle are provided. It is characterized by a queue buffer memory that stores information in association with the line number currently being processed.

(5) Examples of the invention This will be explained below with reference to the drawings.

FIG. 4 shows the configuration of an embodiment of the present invention, FIG. 5 is an explanatory diagram of a queue buffer memory, and FIG. 6 shows the configuration of essential parts of an embodiment of the present invention.

In the figure, 11 is a signal input terminal, 12 is a dial pulse counting logic circuit (hereinafter referred to as ONT circuit), and 13 is a memory (which indicates that the handset is valid when receiving numbers).
ACT memo 9 (hereinafter referred to as ACT memo 9), 14 is a memory that stores the scanning results of one cycle of signal pits before (hereinafter referred to as LL memory)
, 15 is a dial pulse counter memory (hereinafter referred to as PC memory), 16 is a memory (hereinafter referred to as AP memory) that stores the detected pulse for detecting the interval (pause) of the dial pulse signal, and 17 is an interval between digits. and a determination circuit for detecting abandonment (hereinafter referred to as DET circuit), 1
8 is a memory (hereinafter referred to as APLL memory) that stores the results of one cycle before the AP memory 16; 19 is necessary for the receiving device and supplies locks to each circuit and memory in the receiving device, and also sends dial information as a signal; A control circuit 2 that transmits information to a central control device (not shown) via an output line 2o.
1 is l number detection information (SP
A Cuban sofa (QB) stores χ abandonment detection information (OAN), dial pulse counting results (DP), and line number information (ON) instructed by the control circuit 19.
))-f:su, 22('!,, SP signal fm, 23haOA N (g consequence, 24 UD P signal!, 25t
An i-ON signal line 26 indicates a signal line that provides write timing to the QB memory 21.

A time-division multiplexed LOOP signal is input to the signal input terminal 11 . ACT memo! 113. T, L memo! 1
14, PC memory 15, etc. are each multiplexed, and the information stored therein is inputted to the ONT circuit 12 after being shifted, for example, by a clock from the control circuit 19, and processed. The ONT circuit 12 processes the same line every l multiplexing cycles.

The ONT circuit 12 uses information from the ACT memory 13,
It is determined whether the LOOP signal to be processed currently is valid, and if it is valid, the dial pulse is detected from the current LOOP signal and the information stored in the LL memory 14 one cycle before, and the count result is It is stored in the PC memory 15. Also, in the AP memory 16, for example, at a period of 9gm5,
Information on whether or not there was a change in the LOOP signal during that time (A
P) is output sequentially. This AP memory! 6 is stored in the APLL memory 18 and read out from the APLL memo 918 with a delay of one cycle.

The DET circuit 17 uses the following logic to determine between digits of dial pulses.

(Liver-)△(APLI・)△(■)△(AC!T) =
1. Also, the following logic is used to determine abandonment or hooking.

(AP)△(APLL)△(LL)△(ACT) =
1. If the above digit interval judgment result is rlJ and the digit interval is detected, turn on the SP signal line 22fc, send the dial pulse counting result to the DP signal line z4, and send the write timing signal line 26 Turn on. Further, if the determination result of abandonment is a river, the OAN signal 3 is turned on and the signal line 26 is turned on.

When the signal 1a26 is turned on, the QB memory 21 stores information from the sp signal line 22, the CAN signal signal 3, and the DP signal line 24 as shown in FIG. 5, for example. At the same time, line number information of the ON signal line 25 is also stored in correspondence. Note that the inter-digit detection information of the SP signal line 22 is not necessarily required and may be omitted.

The information stored in these QB memories 21 is
(Fast In Fast 0ut), the signal is read out to the central control unit via the signal output line 2o under the control of the control circuit 19.

Therefore, according to the present invention, the scan processing section 6 shown in FIG.
There is no need for the software to scan for all the information of the multiple variations; only the valid information of the dial pulses will be provided.

FIG. 6 shows the QB memory 21 in detail including the peripheral portion. A signal line 27 supplies a frame pulse indicating a frame of an input signal, and a signal line 28 supplies a clock for operating the receiving apparatus.

Therefore, the ON signal line 25 is connected to the SP signal line 22, OAN
It is synchronized with the signals on the signal line 23 and DP signal line 24, and indicates the line number. The signal line 26 is (AP)△(
When APLL)Δ(ACT) = 1, a pulse appears, and therefore, only when an inter-digit or mid-digit abandonment is detected, the corresponding line number (ON), sp double signal CAN signal, DP scratch signal, and QB memory 21 are Loaded.

The signal line 30 is a signal line that conveys information to the control circuit ■9, but in addition to CAM, SP, DP, and ON, it also has QB memo 'J2.
．． One information line indicating the presence/absence of information in 1 is added. For this purpose, the act-ready DOR signal in the FIFO may be used.

(6) As described in detail, according to the present invention, by using the Cuban sofa memory, it is not necessary to prepare memories for SP, CAM, and DP flaw signals for multiple variations, and it is possible to imprint them. Therefore, the line cost can be reduced. Furthermore, when reading dial information from the central control unit, only the queue buffer memory needs to be accessed, and the overhead of scanning by software is reduced.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of a conventional dial pulse receiving device;
3 and 3 are diagrams for explaining the principle of counting dial pulses, etc., FIG. 4 is a configuration of an embodiment of the present invention, FIG. 5 is an explanatory diagram of a queue buffer memory, and FIG. 6 is a diagram of the present invention. The main part configuration of one embodiment is shown. In the figure, 11 is a signal input terminal, 12 is a dial pulse counting logic circuit, 13 is an ACT memory, 14 is a LL memory, 1
5 is dial pulse counter memory, 16 is AP memory, 17 is judgment circuit, 18 is API, L memory, 1
9 represents a control circuit, and 21 represents a Cuban sofa memory. Patent applicant Fujitsu Ltd. Representative Patent Attorney Mori 1) Hiroshi (1 other person) -563-? 5 Genius G Nagi

Claims (1)

[Claims] A dial pulse receiving device that receives a dial pulse signal arriving in the form of a signal bit includes a dial pulse counting logic circuit that counts the pulses of the dial pulse signal, and a determination circuit that detects gaps between digits and abandonment, A queue and a buffer memory are provided for storing dial pulse counting results or mid-term abandonment information counted by the dial pulse counting logic circuit in correspondence with the line number currently being processed when the circuit detects an interval between digits or a mid-term abandonment. A dial pulse receiving device characterized by: