JPS59133750A - Synchronism catching circuit - Google Patents

Abstract

PURPOSE:To attain the correct catch of synchronism which is scarcely affected by interferring and disturbing waves by delaying a demodulated base band signal for a fixed period of time and at the same time integrating the base band for said fixed period to limit the delay output with the integrated value defined as the limit level. CONSTITUTION:A delay circuit 17 delays the output of a demodulating circuit 8 for a prescribed period of time, and a limiter 19 limits the output of the circuit 17. Then the 1st and 2nd integration circuits 18 and 13 are newly provided to integrate the outputs of circuits 8 and 17. The output time width of the limiter 19 to the interfering wave is set smaller than that to a received signal 101. Thus a synchronism catching circuit which is scarcely affected by interfering and disturbing waves is obtained for the received signal in the frequency hopping spread spectrum communication. Thus it is possible to form effectively a multiple access communication system of spread spectrum having the interference.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization acquisition circuit used in a frequency hopping spread spectrum communication receiver.

FIGS. 1(a) and 1(b) are block diagrams of a transmitter and a receiver, respectively, in a frequency hopping spectrum communication system. The transmitter shown in FIG. 3A includes a frequency synthesizer 1. which generates a carrier wave whose frequency hops. A pseudo-noise code (Pseudo-noise code) that determines the hopping pattern
No1se Code (hereinafter referred to as PN code) generator 2. Information signal source 3. It has a modulator 4. This is exactly the same as the conventional modulation method except that the frequency of the carrier wave hops according to the PN code.

The receiver shown in FIG. 2B includes a frequency synthesizer 9 for generating a local signal 102. PN code generator 10; balanced modulator 7 for demodulating the carrier wave hopping to produce an intermediate frequency signal 103; Demodulator 8 for demodulating baseband signal 104. It has a synchronization circuit 11 that matches the hopping pattern of the received signal 101 and the hopping pattern of the local signal 102.

The information signal contained in the baseband signal 104 is extracted from the output terminal 12. FIG. 2(a) shows the received signal 101
2 is a diagram showing a frequency pattern of PN code generator 2, in which the frequency hops in accordance with the code pattern of the PN code generator 2.

(b) is a diagram showing the frequency pattern of the local signal 102, and similarly to the transmitting side, the output 10 of the PN code generator 10
The frequencies are hopping in accordance with the PN code represented by 6. Here, fl-11' f2-f2/,...
, f, -f5/ are all constant, and their values are selected to be equal to the frequency of the intermediate frequency signal 103. Received signal 1
When the hopping patterns of 01 and the local signal 102 match (hereinafter referred to as a synchronous state), the baseband signal 104, which is the output of the demodulator 8, becomes maximum and constant as shown in FIG. 2(C). Become. The circuit for bringing the local signal 102 into this synchronized state is the synchronization circuit 11, which consists of a synchronization acquisition circuit having an initial synchronization function and a synchronization holding circuit having a synchronization maintenance function.

Of these, the block diagram of the conventional method of the synchronization acquisition circuit is shown in the third section.
FIG. 4 shows the time relationship between the signals and frequency patterns of each part of this circuit. however.

The synchronization acquisition circuit of FIG. 3 includes the receiver circuit of FIG. 1(b) in its entirety. This method is called step search and consists of a balanced modulator, 7° demodulator, 89 frequency synthesizer, and 9. The PN code generator 10 is shown in FIG.
) is each circuit itself.

In addition to these circuits, an integrator 13 with an integration time Δτ, a timing signal generator 14 . Clock generator 15. A phase shift circuit 16 is provided which shifts the phase of the clock signal 110 by Δτ in synchronization with the timing signal 108 when synchronization cannot be acquired. The operation of this step search type synchronization acquisition circuit will be explained below. The clock signal 110 generated by the clock generator 15 passes through the phase shift circuit 16 controlled by the phase shift signal 109 generated by the timing signal generator 14.
The phase shifts at constant time intervals Δτ. The output 111 of the phase shift circuit 16 in the case of delay shift is shown in FIG. 4(a). Due to the clock signal 111 whose phase is shifted at a constant time interval Δτ, the phase of the hopping pattern of the local signal 102 is shifted in synchronization with the clock signal 111 as shown in FIG. Now, when the hopping pattern of the received signal 101 is shown in FIG.
The output 103 is as shown in the same figure (d). The integrator 13 is reset by the timing signal 108 and integrates the baseband signal 104 over a period of Δτ in synchronization with the phase shift of the clock signal 110. Therefore, the output 107 of the integrator 13 becomes as shown in FIG. 3(e), and the maximum output is obtained at the end of the section where the hopping patterns of the local signal 102 and the received signal 101 match. In this way, in the step search method, the clock signal 110
A synchronized state is obtained by periodic phase shifts of , and by searching for a state in which the output of the integrator 13 is maximum.

However, with the conventional circuit shown in Figure 3, the above operation can be performed without error when there is no interference or disturbance wave, but when a large interference wave is received, the synchronization state is lost. Even if the integrator output 107 is large, it is possible that a large integrator output 107 appears. For example, as shown in Figure 4), when a sine wave interference wave of frequency f8 is received, the output of the demodulator 7 is
4 is because this interference wave is added to the received signal 101 in FIG. 4(C).

The result is as shown in FIG. At this time, the output 1074 of the integrator 13 becomes as shown in FIG. Synchronous acquisition cannot be performed correctly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization acquisition circuit in which the synchronization acquisition of a received signal in single-frequency hopping spread spectrum communication is less affected by interference waves or jamming waves.

The synchronization acquisition circuit according to the present invention receives a spread spectrum signal and a local signal in which the frequency of a carrier wave is hopping in correspondence with a pseudo-noise code, and the synchronization acquisition circuit receives the spread spectrum signal and the local signal, and performs the spread spectrum signal for a period when the frequency difference between these two signals is a predetermined value. a demodulation circuit that generates a baseband signal with a magnitude proportional to the amplitude of the signal; a delay circuit that delays the baseband signal by a predetermined time; a first integrator that outputs an integral value; an IJ mitter that limits the output of the delay circuit by using the integral value as a limit level; a second integrator for outputting, a clock generator for generating a clock signal having the same period as the clock period of the spread spectrum signal, and controlling the phase of the clock signal according to the integrated value of the second integrator. a pseudo-noise code generator that generates a signal representing the pseudo-noise code in synchronization with the output of the phase control circuit;
and a frequency synthesizer that generates the local signal by frequency hopping according to the pseudo-noise code.

The present invention will be described in detail below with reference to the drawings.

FIG. 5 is a block diagram of one embodiment of the present invention, and FIG. 6 is a waveform diagram of various signals of this embodiment. In this example, the third
In addition to the conventional circuit shown in the figure, a delay circuit 17 with a delay time of 8τ. An integrator 18 having the same configuration as the integrator 13. I
A limiter 19 whose J limit level changes according to the output 113 of the integrator 18 is provided. The operation of the circuit having such a configuration will be explained next. Figure 6(a) shows
It is the output 104 of the demodulator 8, and represents a waveform when it is in a synchronized state at time Δ11 and receives interference at time Δt2. The figure (b) shows the output 113 of the integrator 18,
The limit level of the limiter 19 is set by the final value of τ for each of the outputs 113. The input signal 112 of the limiter 19 (fc) in the figure is a signal obtained by delaying the demodulator output 104 in the figure (a) by Δτ. The output 114 of the limiter 19 for this input signal 112 is:
Due to the limit level set by the output 113 of the integrator 18, the level for the force ξΔt2 is suppressed, as shown in FIG. Such an effect of the limiter 19 makes it possible to reduce the influence of interference waves on the synchronization acquisition circuit. If this is the case, the output time width of the limiter 19 for the interference wave is smaller than the output time width τ for the received signal 101, so at the output 107 of the integrator 13, the level of the interference wave component is mutually smaller than the signal wave component. Therefore, the timing signal generator 14 distinguishes one image component only when synchronization can be truly acquired.

This is because the phase shift of the phase shift circuit 16 can be stopped.

As described in detail above, according to the present invention, it is possible to provide a synchronization acquisition circuit in which the synchronization acquisition of a received signal in frequency hopping spread spectrum communication is less susceptible to interference waves or disturbance waves. Therefore, by using this synchronization acquisition circuit, a spread spectrum multiple access communication system that involves interference can be effectively constructed.

[Brief explanation of drawings]

Figures 1 (a) and (b) are block diagrams of a transmitter and receiver of the frequency hopping spread spectrum communication system, respectively, and Figure 2 shows the frequencies and signal levels of signals in each part to explain the operation of this receiver. 3 is a block diagram of a conventional synchronization acquisition circuit using a step search method, FIG. 4 is a diagram showing the time relationship between signals and frequency patterns of each part of this circuit, and FIG. 5 is a diagram of an embodiment of the present invention. Block Diagram,
FIG. 6 is a diagram of signal waveforms at various parts of this embodiment. (of) 1σ6 (b) Figure 1 Figure 3 (b) lf: 1fzf fs 1falf month ft 1
f-1も;lfglf,;1ful(c)1chi□1fl
fzlf, +1fdfdfdf71fx1f9(fta
lfAfal.

Claims (1)

[Claims] A spread spectrum signal whose carrier frequency is hopping in correspondence with a pseudo-noise code and a local signal are received, and the magnitude is proportional to the amplitude of the spread spectrum signal for a period during which the frequency difference between these two signals is a predetermined value. a demodulation circuit that generates a baseband signal, a delay circuit that delays the baseband signal by a predetermined time, and a first circuit that integrates the baseband signal with respect to the time and outputs an integral value when the time elapses. an integrator; a limiter that limits the output of the delay circuit using the integrated value as a limit level; and a second integrator that integrates the output of the limiter over the time and outputs the integrated value after the elapse of the time. , a clock generator that generates a clock signal having the same period as the clock period of the spread spectrum signal;
a circuit that controls the phase of the clock signal according to the integral value of the second integrator; and a pseudo-noise code generator that generates a signal representing the pseudo-noise code in synchronization with the output of the phase control circuit. , and a frequency synthesizer that generates the local signal with frequency hopping according to the pseudo-noise code.