JPS59131244A - Fault detecting system of signal processor - Google Patents

Abstract

PURPOSE:To decide immediately the fault of a signal processor by checking whether or not the transmission state of a start-stop synchronous transmission line is coincident with a transmission state corresponding to a transmitting indication of a central processing unit. CONSTITUTION:An indication for character transmission given from a central processing unit is sent to a processing circuit 6 via an interface circut 5. The circuit 6 analyzes each of transmitted indications and sends the state of transmission, an indication for transmission and the identification information to a line receiving circuit 7. A line output reading circuit 8 stores 8 bits designated by the circuit 6 to a buffer 18 in accordance with the state of transmission of (8X8) bits delivered from a buffer 13 and under the control of a reading control circuit 19. The circuit 6 detects the state of transmission of a start-stop synchronous transmission circuit 4 from the value of the buffer 18 and confirms whether the state of transmission is coincident with indication of transmission for (0) and (1) of the central processing unit. Thus a fault is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a signal processing device failure detection system, and particularly to a method for detecting a failure in a signal processing device, in particular, a system for detecting a failure in a signal processing device, and in particular, a system for transmitting state 0 transmission, state 1 transmission, and character transmission instructions from a central processing unit to an accommodating start-stop synchronized transmission line. A signal processing device failure detection method in a signal processing device that performs reception and transmission processing, constantly monitors the reception status of each of the asynchronous transmission lines, and notifies the central processing unit when a change in the reception status is detected. Technical background FIG. 1 is a diagram showing an example of an exchange to which the present invention is applied, and FIG. 2 is a diagram showing an example of the communication procedure in FIG. 1. In FIG. 1, the signal processing device 2 is connected to all the asynchronous transmission lines 4 accommodated in the network 1, and the signal processing device 2 is connected to all the asynchronous transmission lines 4 accommodated in the network 1. The state 0 transmission, state 1 transmission, and character transmission instructions transmitted based on the procedure described above are received, and the transmission processing for the corresponding asynchronous transmission line 4 is performed, and the reception status of each asynchronous transmission line 4 is is constantly monitored, and when a change in the reception state is detected, the central processing unit 3 is notified.

tc+ Prior Art and Problems Conventionally, in this type of exchange, the central processing unit 3 transmits communication at time t1 to the asynchronous transmission line 4, in which both the transmitting and receiving states are 0, according to the procedure shown in FIG. The signal processing device 2 sends an instruction to send state 1 to indicate the start.
After transmitting the data to the asynchronous transmission line 4, the reception state of the asynchronous transmission line 4 is
Monitoring whether or not a notification changing to state l indicating that communication is possible is returned from the signal processing device 2 at time t2 within a predetermined time,
If the signal is not returned, the signal processing device 2 is determined to be at fault. Similarly, after transmitting a predetermined character sending instruction to the signal processing device 2 at time t3, the signal processing device 2 notifies the return of a predetermined character from the asynchronous transmission line 4 at time t4 within a predetermined time. If no notification is received, the signal processing device 2 is determined to be at fault. Thereafter, similar determinations are made, and at time t5, a transmission instruction of state O is transmitted to the signal processing device 2 to indicate the end of communication, and then the reception state of the asynchronous transmission line 4 is set to state O, which indicates the end of communication. It is monitored whether or not a notification that changes to is returned from the signal processing device 2 at time t6 within a predetermined period of time, and if it is not returned, the signal processing device 2 is determined to be at fault.

As is clear from the above explanation, in the conventional signal processing device failure detection method, after the central processing unit 3 instructs the sending of the transmission state based on a predetermined communication procedure, a predetermined change in the reception state is returned. A failure of the signal processing device 2 is detected by monitoring whether the signal processing device 2 is not present or not. However, according to such a fault detection method, not only the signal processing device 2 but also the network 1
Since the asynchronous transmission line 4, terminal equipment, etc. are also included in the fault detection targets, means for further limiting the affected range is required. For example, it may be considered to connect the connection point of the signal processing device 2 with the node work l by loopback and check the transmission status instruction and the change in the reception status, but this would complicate the failure detection processing process and cause the central processing unit to 3, and because it takes a long time to determine the location of the problem, the reliability of the exchange is reduced.

1dl OBJECTS OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional signal processing device failure detection method as described above, reduce the signal processing device failure detection load on the central processing unit, and shorten the signal processing device failure detection time. The goal is to realize a means to shorten the time.

(e) Structure of the Invention The object of the present invention is to receive instructions from the central processing unit for sending state 0, sending state 1, and sending characters to the storage can start-stop synchronous transmission line, and perform sending processing, and to In the signal processing device that constantly monitors the receiving state of the transmission line and notifies the central processing unit when a change in the receiving state is detected, a line output reading circuit is provided for reading the sending state of each of the asynchronous transmission lines. , upon receiving from the central processing unit an instruction to transmit a state other than state 0 to the asynchronous transmission line which is transmitting state 0, inspecting whether the asynchronous transmission line is transmitting state 0; When a transmission instruction other than state 1 is received from the central processing unit to the asynchronous transmission line which is currently transmitting state i1, it is checked whether or not the asynchronous transmission line is transmitting state 1; This is accomplished by reporting a fault to the central processing unit when the test result is negative.

(fl　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing a signal processing device according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of the line output reading circuit in FIG. 3. Note that the same reference numerals indicate the same objects throughout the plan. In FIG. 3, the signal processing device 2 includes a line output reading circuit 8 in addition to the conventionally provided interface circuit 5, processing circuit 6, and line transmitting/receiving circuit 7.

In FIG. 3, states 0 and STATUS! arrive from the central processing unit 3 (not shown). The @1 and character sending instructions are transmitted to the processing circuit 6 via the interface circuit 5. The processing circuit 6 analyzes each transmitted instruction and selects the 8 for every 8 lines specifying the sending state O or l for the asynchronous transmission line 4.
The bit transmission state is transmitted to the line transmitting/receiving circuit 7 together with the transmission instruction and the identification information of the eight target lines. In FIG. 4, the transmission instruction coming from the processing circuit 6 is transmitted to the bus control circuit 9 in the line transmitting/receiving circuit 7, and the identification information of the eight target lines is transmitted to the queue number buffer 1o.

The queue number buffer 1o stores the subsequent 8-bit transmission status of the queue number buffers 12-1 to 12.
−8 is specified via the decoder 11. The 8×8 bit transmission states accumulated in the Cuban sofas 12-1 to 12-8 are transferred to the buffer 13 under the control of the line transmission control circuit 15 activated by the bus control circuit 9, and then transferred to the buffer 13 by the multiplexing circuit 14. The 64 lines are time-division multiplexed and transmitted to network 1. On the other hand, the line output reading circuit 8 selects the 8 bits designated by the processing circuit 6 from the 8×8 bit transmission state output from the buffer 13 of the line transmitting/receiving circuit 7 under the control of the reading control circuit 19. 16 and stored in the buffer 18 via the selection circuit 17. The processing circuit 6 controls the read control circuit 19 in the line output reading circuit 8 by transmitting a transmission state reading instruction to the bus control circuit 9 of the line transmitting/receiving circuit 7, and controls the read control circuit 19 in the line output reading circuit 8.
By reading the 8-bit sending status stored in
The transmission state of the predetermined asynchronous transmission line 4 can be detected. When the processing circuit 6 receives from the central processing unit 3 an instruction to transmit state 1 or a character to the asynchronous transmission line 4 which is currently transmitting state O, the processing circuit 6 determines the current transmission state of the asynchronous transmission line 4. ! f:, check whether it is 0;
If the state is not 0, a fault report of the signal processing device 2 is immediately sent to the central processing unit 3, and an instruction to send a state 0 or a character is transmitted from the central processing unit 3 to the asynchronous transmission line 4 which is currently sending state 1. When the asynchronous transmission line 4
It has a function of checking whether the current transmission state of the signal processing device 2 is in state 1, and if it is not in state 1, immediately reporting a failure of the signal processing device 2 to the central processing unit 3. Therefore, at time t1 in FIG. 2, when receiving an instruction to send state l indicating the start of communication to the asynchronous transmission line 4, which is currently sending state 0, from the central processing unit 3, the processing circuit 6 transmits the target asynchronous An instruction to read the transmission status of eight lines including the transmission line 4 is transmitted to the line transmitting/receiving circuit 7. The line transmitting/receiving circuit 7 stores the corresponding 8-bit transmission state from the line output reading circuit 8 in the buffer 18.

The processing circuit 6 reads the 8-bit transmission state stored in the buffer 18, checks whether the target asynchronous transmission line 4 is in state O, and if it is not in state O, the signal processing device 2
A failure report is sent to the central processing unit 3. Also, at time t3,
When a character sending instruction is received from the central processing unit 3 to the asynchronous transmission line 4 which is currently sending the letter Ml, the processing circuit 6
transmits an instruction to read the transmission status of eight lines including the target asynchronous transmission line 4 to the line transmitting/receiving circuit 7, and
The state of the target asynchronous transmission line 4 is determined by the sending state of the 8 bits read from 8! 31, and if the state is not l, a failure report of the signal processing device 2 is sent to the central processing unit 3. Further, at time t5, when receiving an instruction to send state 0 indicating the end of communication to the asynchronous transmission line 4 which is currently sending state 1 from the central processing unit 3, the processing circuit 6 transmits the state 1 to the asynchronous transmission line 4. An instruction to read the transmission states of the 8 lines including the transmission line is transmitted to the line transmission/reception circuit 7, and based on the 8-bit transmission status read from the buffer 18, it is checked whether or not the target asynchronous transmission line 4 is in state 1. If not, a failure report of the signal processing device 2 is sent to the central processing device 3.

As is clear from the above description, according to the present embodiment, the signal processing device 2 connects the central processing device 3 to the asynchronous transmission line 4.
When the transmission instruction for the transmission line 4 is transmitted, the current transmission state of the asynchronous transmission line 4 is read by the line output reading circuit 8, and it is checked whether or not it is in the transmission state corresponding to the transmission instruction. If negative, a failure report of the signal processing device 2 is immediately made. The central processing unit 3 that received the failure report,
A failure in the signal processing device 2 can be immediately determined.

Note that FIGS. 3 and 4 are only one embodiment of the present invention, and the configurations of the signal processing device 2, line transmitting/receiving circuit 7, and line output reading circuit 8 are limited to those shown in the figures. Although many other modifications may be considered, the effects of the present invention will not change in any case.

(gl) Effects of the Invention According to the present invention, in the signal processing device, the fault detection load on the central processing unit is significantly reduced, so the processing capacity of the central processing unit is improved, and the failure of the signal processing device is improved. Since the information can be determined in a short time, the reliability of the exchange is improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an exchange to which the present invention is applied, FIG. 2 is a diagram showing an example of the communication procedure in FIG. 1, and FIG. 3 is a diagram showing a signal processing device according to an embodiment of the present invention. , 4th
The figure is a diagram showing an example of the line output reading circuit in FIG. 3. In the figure, 1 is a network, 2 is a signal processing device, and 3 is a network.
is a central processing unit, 4 is an asynchronous transmission line, 5 is an interface circuit, 6 is a processing circuit, 7 is a line transmission/reception circuit, 8
1 is a line output reading circuit, 9 is a bus control circuit, 10 is a queue number buffer, 11 is a decoder, 12-1 to 12-
8 is a Cuban sofa, 13 and 18 are buffers, 14
is a multiplex circuit, 15 is a line transmission control circuit, 16 and 17
19 indicates a selection circuit, 19 indicates a read control circuit, and tl to t6 indicate time points. 6It5 ts 2nd
Figure 4

Claims (1)

[Claims] Receives state 0 transmission, state 1 transmission, and character transmission instructions from the central processing unit to the storage can asynchronous transmission line, performs transmission processing, and constantly monitors the reception status of each of the asynchronous transmission lines, The signal processing device that notifies the central processing unit when detecting a change in the receiving state is provided with a line output reading circuit that reads the sending state of each asynchronous transmission line, and the central processing unit sends out a state of 0. When receiving an instruction to send a state other than 0 to the asynchronous transmission line in the center, it is checked whether the asynchronous transmission line is sending out state O, and state 1 is being sent from the central processing unit. When receiving an instruction to send out a state other than state 1 to the asynchronous transmission line, it is checked whether the asynchronous transmission line is sending out state 1, and if the test result is negative, the central processing A signal processing device failure detection method characterized by reporting a failure to the device.