JPS59129889A - Group language learning apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a group language learning device consisting of one miscellaneous device and a plurality of slave devices, and in particular uses a random access memory as a storage medium for kidnapping. , in which the audio signals stored in the random access memory are time-division multiplexed and read out in accordance with the operations of each student, and are distributed and supplied to each child device.

<Background Art and its Problems> In a group language learning method generally called the LL-system (Language Laboratory System), the main content is the repeated practice of basic fixed sentences.

To do this, we first make duplicate tapes for each student, and the students play the duplicate tapes on their own basis using L/L tape recorders placed for each student to practice language skills such as English conversation. Therefore, in the conventional method as mentioned above, LL for the number of students is
The drawback is that the larger the scale of the LL-system, the greater the cost of producing the system.

In addition, the recording and playback operation of a tape recorder is originally a so-called sequential operation that is performed along the magnetic tape, and when a student arbitrarily selects the special Y section of the paulownia to practice, Rewinding, fast forwarding, etc. take time and it is not possible to respond to i selection immediately.

Furthermore, since each tape recorder operates independently, it is difficult to synchronize all the tape recorders so that all students can listen to the same sentence at the same time. cannot be used in synchronization with other devices.

<Object of the invention> The present invention has been made in view of the above-mentioned circumstances,
By using random access memory (hereinafter referred to as 1-RAMJ) as a storage medium for teaching materials in the LL-system, we aim to diversify the language learning method using the LL-system and also overcome the drawbacks of the conventional LL-system. The purpose is to remove old objects.

<Summary of the Invention> In order to achieve the above object, the present invention stores a data signal obtained by digitally encoding an audio signal for teaching materials at a predetermined sampling period in a random access memory provided in a miscellaneous device.
The gist thereof is to time-division multiplex read data signals from the random access memory without supplying them to each child device, and to distribute and supply the read data signals to each child device at the sampling period.

<Example> An example according to the present invention will be described below with reference to FIGS. 1 to 5.

First, before describing specific embodiments of the group language learning device according to the present invention, the basic configuration and operation of the present invention will be outlined.

As shown in FIG. 1, the group language learning device according to the present invention includes one miscellaneous device 1, a plurality of child devices 2 (for example, as many as the number of students),
2,2. It consists of...

The above-mentioned miscellaneous device 1 is provided with a RAM 3 for storing audio teaching materials for language learning, and this RAM 3 is provided with a RAM 3 for storing audio teaching materials for language learning.
Each data signal of the audio teaching material digitally encoded into a CodeModuL+1ion) signal is stored at a predetermined storage address (hereinafter referred to as j-RAM address). Note that the data signal Y is a signal of each sample value obtained by digitally encoding the analog signal of the voice lesson J at a predetermined quantization level.

In addition, the slave devices 2, 2, 2. ... is placed in each student's hand, and address registers 4, 4゜4, . . . specify RAM 71-res according to each student's operation.
A digital-to-analog converter 5 that decodes the data signal read from the RAM 3 into an analog signal according to the specification;
5,5. ..., and Hella 1 to Hong 6.6, 6. ...
It consists of:

The above-mentioned sharp device 1 Yoshiko device 2, 2.2 are connected by a signal line formed through a signal distributor 7.

A reference pulse outputted from a pulse generator 8 is supplied to the signal distributor 7, and each slave unit 2, 2, 2
．． The signal specifying the 1% AM at Vs of RAM 3 (hereinafter referred to as "RAM address signal") output by the operation of the address registers 4, 4, 4, . . . is synchronized with the above reference pulse. and is sequentially supplied to R'AM3 in a time-division manner. Similarly, each data signal read from the RAM 3 in accordance with the RAM address signal is transmitted to each child device 2, 2, 2, . The signals are sequentially distributed and supplied to the digital-to-analog converters 5+ 5+ 5+...

As mentioned above, the miscellaneous device of the group language learning device according to the present invention digitally encodes the audio signal for the teaching material at a predetermined sampling period and quantization level, and converts the data signal encoded by this into R.
AM3 and each child device 2, 2, 2 . ...
The data signals to be supplied to the RAM 3 are time-division multiplexed and read out to each child device 2.2.2. Distribute and supply to...

Then, each child device 2, 2. Digital-to-analog converters 5, 5, 5. ... decodes the data signal supplied at the sampling period, thereby supplying the audio signal for the teaching material to each student.

As described above, in the group language learning device according to the present invention, audio signals for teaching materials can be read out in response to each student's operation of the child device, similar to group language learning using a conventional tape recorder.

Next, specific examples according to the present invention will be described.

The group language learning device in this embodiment transmits and receives audio signals for abduction in the audio band of 40 [kHz] between one sharp device and 256 slave devices (!:(!:also 100
A device equipped with RAM that stores 0 seconds worth of audio signals.

In addition, in this example, since the audio signal in the audio band of 4.0 [kHz] is handled, the sampling frequency is set to 8.0 Ckl (z) (sampling period = 125 [μm]) based on the sampling theorem. Let's say that the quantization level of the data signal stored in the RAM 10 that stores the above 1000 seconds worth of audio signals is 3[I]itl.
The storage capacity of RAM 10 is the product of the sampling frequency, quantization bit, and storage time, so the storage capacity of RAM 10 is 80"" [Hzl x 8Toit:] x 1oool:se
e].

FIG. 2 is a block diagram showing the electrical configuration of the group language learning device according to this embodiment.

In this device, the address register 20 for specifying the RAM address of the RAM 10 is provided on the 1i100 side, and the address register 20 is provided on the 1i100 side.
56 word memory address AR.

A RAM with 1 to AR, 2'56 is used.

In addition, each of the above storage addresses ARI of the address register 20
-AR256 is each composed of 23 [bits], so that each memory address A, R] to AR256 is
The 223rd to 223rd RAM addresses can be stored.

In addition, since 2F; 84 cutting is 0°, each memory address AJ(,]~AR256 of the AR256 of the AR256
can specify the RAM addresses of all data signals (8-06) that can be stored in the RAM 10.

The address register 20 is supplied with various signals, which will be described later, that are output from an operating device 40 provided in the child device 101.

Then, the address register 20 sends the RAM address signal RAP to an adder 21 and a multiplexer (hereinafter 1-M
(referred to as PXJ) l 22 to the RAM 10.

Next, the operation device 40 has a forward/stop switch (hereinafter referred to as "F/8 switch") 41 and a normal/jump switch (hereinafter referred to as "N/8 switch") for specifying the operation mode of this device selected by each student. 4)
2, and jump destination address specification switch (rJM
43 (referred to as "P switch").

The above I''/S sui-nochi 41 outputs rN when the student selects the fort mode, and outputs a binary signal of "0" when the student selects the stop mode as the address operation signal OP to the adder 21 via the MPX 223. Supplied to one side of the input. When the adder 21 is supplied with rlJ as the address operation signal OP, the R, AM address signal RAP? which has already been supplied from the address register 2o? ζ
Add rlJ to J1. When "0" is supplied as the address operation signal OP, the R.
Address signal RAP is supplied as is to MPX526.

The JMP switch 43 is configured with 23 [bits] and sends a jump destination address signal JAP to specify how far to jump when a certain student selects a jump mode to be described later.
Supply to PX526.

The N/J switch 42 is the F/S switch 41 (!
:Similarly, the binary signal rlJ or rOJ is used as the operation mode selection signal MSP to connect the MPX5261ζ via the MPX424.
This switches the output signal of MPXs'16.

First, when the student specifies the normal mode, he supplies "0" to the MPX626 as the operation mode selection signal MSP, and thereby the output of the MPX526 is used as the new RAM address signal I (supplied from the adder 21). , A.P.
Also, when the student specifies the jump mode, rlJ is supplied to the MPX526 as the operation mode 1 selection signal MSP, and the output of the MPX526 becomes the jump destination address signal, ■AP, and any of these signals (RA
P or JAP) is supplied to the AR20.

Next, 50 is a pulse generator, and this pulse generator 50
is the sampling period (
A timing pulse of 48 g [n5ec], which is equal to the value obtained by dividing 125 Cμ] by the number of child devices (256 [units]), is supplied to the counter 51.

This counter 51 is composed of 3 bits,
The number "1 to 256" is output as a counter signal CP to the callan 1 corresponding to each of the first to 256th child devices 101 in synchronization with the reference clock pulse SP.

The counter signal CP is the M P
3, MPX325, MPX424, Address Regisge 2
0, and a demultiplexer (hereinafter referred to as j'-D-M
PXI) 11 input terminals 27゜28.29,3
0.12.

Then, this counter signal CP is, for example, a count number "n".
"When the counter signal CP of " is output, the signals X output from the controller of the n-th slave device are supplied to the n-th memory address of the address register 20 via the MPX 526. Then, the data signal stored in the predetermined location of R, AMl0 corresponding to the R, AM address stored in the nth storage address ARn of the address register 20 is transferred to the nth storage address ARn through the D-MPXI 1. child organ 1
Each of the MPXs 23, 24, 25, the address register gate 20, and the D-MPXl 1 are controlled so as to supply the signal to the digital-to-analog converter 13 of No. 01.

In addition, the counter 51 counts the reference clock pulse SP with an output period of 4881: n games and outputs 488 [nfIeC
] in the cycle from count number “1” to count number [2,56
A counter signal CP corresponding to J is output. Therefore, according to this counter 51, for example, the counter signal CP with the count number "l" is equal to the sampling period, 125 [μSeC
] is output at a period of .

Therefore, data signals are distributed and supplied to each child device 101 at a timing equal to the sampling period.

Next, the counter 51 inputs the reference clock pulse SP by 2.
The write dark reference pulse WSP, which is divided by 56 and has a period of 125 [mu] equal to the sampling period, is sent to the analog-to-digital converter 14, the digital-to-analog converter 11, the write signal generator WPG52, and the address designation counter. It is supplied as a synchronization signal to each reference pulse input terminal 15, 16, 54, 55 of WA-C53.

The address designation counter W'AC33 is 23 [bits].
], which counts the write dark reference pulse WSP and supplies an address designation signal WAP for designating RAM addresses from 1 to 223 to the MPX, 22.

Note that the M P'X 122 is switched between a read mode and a write mode by a mode changeover switch 56.
In the read mode, the address register 20 supplies the I (AM address signal RAP) to the RAM 10, while in the write mode, the address designation signal W output from the address designation counter WAC!53 is supplied to the RAM 10.
Supply AP to RAM1Q.

Further, the write signal generator WPG52 is turned on and off by switching the mode changeover switch 56.
state, that is, in the write mode, the write signal WP is set to R, A in synchronization with the write dark reference pulse WSP.
Supply to MIO.

Next, an audio signal for language learning is supplied to the audio signal input terminal 17 of the analog-to-digital converter 14, which is supplied with the write dark reference pulse WSP via the reference pulse input terminal 16. The analog-to-digital converter 14 converts the audio signal into a sample with a sampling period of 125 [μ] and a quantization level of 3.
[bit] is digitally encoded into a PCM signal.

Then, each take signal of the digitally encoded sample value is sequentially stored in the RAM at the timing of l 25 [: n5cc].
10.

Next, the operation of the group language learning device according to this embodiment as described above will be explained.

The operation of this device can be roughly divided into 10 RAMs for language learning materials.
There are two types of operations: a write operation in which the teaching material is stored in the memory, and a read operation in which the teaching material designated by each student is read out according to the operation of the operating device 40.

First, the write operation of this device will be explained.

This device is set to the write mode by switching the mode changeover switch 56, and thereby the MPX 122 outputs the addressing signal WAP supplied from the addressing counter WAC53 and supplies it to the RAM 10.

Further, the write signal generator WPG52 is also turned on, and the write signal WP outputted from the generator 52 is set to II, AM.
Provided to IO.

When analog signals (audio signals) A, B, C, etc. having waveforms as shown in FIG. 3 are supplied to the audio signal input terminal 17 of the analog-to-digital converter 14, those signals A, 13. c, ... is a sampling period of 125 [μ],
Digitally encoded with quantized level 8 [bitl, respectively "a, , a2" as data signals.

a3. a4. '..., anJ r+)1. l)
2. l)3. b4.・'=, bml 1-CI
, C2, C3, C4, "-, C1, J...Mountain"-'
are sequentially output and supplied to R and AMI O.

The above writing reference pulse WSP, 'each data signal al,
a2. a3. -, bl, .=, cl, -, Address register WAP and write signal WP are supplied to RAMID1 at the timing shown in FIG.

That is, the data signals al, a, 2. a3.
”-, bl.

. . , C1 . . . , the address signal wAP, and the write signal WP are all supplied to R and AMIO in synchronization with the write base pulse WSI).

Then, at the same time when the first data signal a1 is supplied to RAMI O, the addressing signal WAP and R
A write signal WP instructing to store the above data signal a at AM address "1" is supplied t1.
Data signals 1a and J are stored in RAM address "1" of M10.

The above storage operation is repeated at the following/[next 125 [μ]] timing, and the data signal "a2" is sent to the RAM address "2", and the data signal "a3" is sent to the RAM address "3".
”, the data signal rbm J is the RAM address “n +
m J to memorize it.

Therefore, from RAM address "1" of RAM10, R
Data signals from the first data signal "a," to the 8th]06th data signal are stored in order up to the AM address "8K06".

'Next, the reading operation of this device will be explained.

First, the write mode is switched to the read mode by operating the mode selection switch 5G.

From the collection, MPX, 22 outputs the RAM address signal RAP supplied from the address register 20, and R, A
Supply to Mlo.

At the same time, the write signal generator WPG52 outputs OF Ii
``When the status is good, the supply of the write signal WP to the RAM 10 is stopped.

This device can perform three types of reading operations as described below by operating the operating device 40 arranged for each child device 101.

That is, the first operation is to operate the N/J switch 42 to set the normal mode, and operate the F/S switch 41 to switch to the forward mode (hereinafter referred to as "normal forward mode"). ) stored in RAMI O by data signals al, a2 . . . are read out sequentially starting from the first.

Now, to explain the case where the first student (the student operating ARI) specifies the normal forward mode, first, the address register 20 is set in the initial state.
The first memory address of is cleared.

Then, Ill is supplied to the adder 21 as an address operation signal OP from the F/S switch 41 of the first student's controller 40 via the MPX 223, and the RAM address signal is incremented.

As a result, MPXs26 has RAM address [1(]+
0) A new RAM address signal is provided specifying J. At the same time, "0" is supplied to the MPX526 as the operation mode selection signal MSP from the N/J switch 42 via the MPX424, so that the MPX526
A RAM address signal specifying the address "1" is supplied to the first storage address ARI of the address register 20, and the storage address AR] stores "1" as a new RAM address.

The above operation is carried out during the period from when the counter signal CP with a count number of "1" is output from the counter 51 until the counter signal CP with a count number of "2" is output, that is, 488
[This is carried out during n5ccl, and after the counter signal CP with the count number "2" is output, the second memory address of the address register 2o is stored based on the operation of the second student in the same way as in the case described above. Add a new RAM address to AR2.
I remember Lesca Ina.

Then, after the counter 51 outputs the counter signal CP with the count number r256 J,
e) After) Counter 51 again outputs the counter signal CP of callan 1 to number "1". Similarly to the above case, the address register 2o outputs the RAM address signal specifying ■' LAM address "1". Supplied to RAM10,
As a result, R and AMlo are stored in the RAM address rlJ, and the data signal a is supplied to D-MFXI 1, and D-
MPXll distributes the data signal al to the digital-to-analog converter 13 of the first student.

At the same time, the first storage address AR, l of the address register 20
is the RAM address [1] added by the adder 21.
A new R, AMM address specifying 2(+++)J is stored.

Next, the second operation (operating the N/J switch 42 to set the normal mode, operating the F/s switch 41 to switch to the knob mode 1- (hereinafter 1-)- 1, no stop mo 1'J (!: when) RA from ni
This is a case where the tail signal is not read out from M10, that is, in this case, in the first operation of Ai, F
The /S switch 41 outputs “0” as the address operation signal QP.
'' is supplied to one side input of the adder 21, the RAM address is not incremented and the memory address of the address register 20 is maintained in a clear state.
There is no output signal from the .

What if you switch from normal forward mode to normal forward mode at any time? This is as described above (the RAM address is not incremented by the adder 21, but a new RAM address is sent from the adder 21).
, M address designation signals continue to be supplied to the designated storage address of the address register 20.

Therefore, RAMIO always supplies the same Cheeky H number to the child device, and student ζ is not supplied with audio teaching materials.

That is, when the normal stop mode is set, RAM10 outputs a signal that is not decoded to the audio signal, as shown in the column of the second student (/162) in FIG.

Next, the third operation is to operate the N/J switch 42 to set jump mode, and to specify the jump destination address with the JMP switch 43, from any teaching material (data signal corresponding to) desired by the student. This is a case where the data is read out.

Now, the nth student (the student operating ARn) is
We will explain the case where we try to read out the audio signal B of the th teaching. First, the initial state is the same as in the first operation (normal forward mode +x), and the address register 20 is read out. 11th memory address A
Rn is cleared.

Then, by specifying the destination address In+]J with the JMP switch 43,
6, jump photon 1-rus rn via MPX325
A RAM address signal specified by +IJ8 is supplied.

In addition, the MPX 526 uses rlJ as the operation mode selection signal MSP supplied via the MPX 424 to send the RAM address signal specifying the jump destination 1-res "n11" to the nth storage number A of the address register 20.
Rn, and new R, AI is stored in the storage number ARn.
Jump destination RAM address “n+” as M address
J is memorized.

Then, after +25 [Lμ overturn], when the counter signal CP with the count number "n" is output from the counter 51 again, the nth memory address A Rn of the address register 20 is accessed again and the previously stored jump destination The RAM address signal that specifies the RAM address [n+lJ is R, AM
It is supplied to IOl and one side input of the adder 21.

As a result, the take signal stored in the RAM address [n+l Tallu analog converter 13
distributed and supplied to

In addition, in this third operation, 11'' is then supplied to the adder 21 from the F/S switch 41 as the address operation signal OP, as in the first operation, so that the jump destination address specified by the student is Following the stored data signal b2. b3. b4. ...
are sequentially read out as subsequent data signals.

As is clear from the above description, in the group language learning device in this example, the first and third students specify the normal forward mode, and the second student specifies the normal straf mode. In addition to specifying
When the 256th student attempts to read from the second teaching material B, the data signal output from the RAM 10 is 488 [n5ec] synchronized with the counter signal CP.
As shown in the vertical column of Fig. 5, "a+J IVJ
ral, J... "bl", "a2""0""a2"
・“b2”, “a3” [-s J “a3J・,・”b
3", -, "anJ rm"ra-J-"bll", "
"bl", "end", "bl"..."bn+1", etc.

In addition, those data signals are first transmitted by p-Mpxii.
"al" [-a2] "a3" for the th and 3rd students
"... "an""I51""bl1...", and the 256th student receives "b+l [-b2" [
bJ...[bmj rclJ j-cJ...] are distributed and supplied sequentially.

Since the distribution and supply of the digital signal to each student is performed at a period equal to the sampling period 125 [μ'+ec], the readout signal is read out in step 1. The taken signal is decoded into the original analog signal (audio signal) by the decicle-analog converter 13.

Incidentally, the audio signal of the teaching material is naturally supplied to the fourth to 255th students who are not mentioned in the above explanation in the same manner as described above.

<Effects of the Invention> As is clear from the above description, the present invention uses random access memory as a storage medium for audio signals for teaching materials,
The audio signals sampled and stored in the random access memory are time-division multiplexed read out, and the read data signals are distributed and supplied to each child device, allowing each student to learn the language on his or her own basis. This makes it possible for all students to practice the same sentences at the same time, and for language learning to be synchronized with other devices such as video tape recorders.

Furthermore, although the random access memory itself is relatively expensive, the larger the scale of the system, the lower the cost per student. It is particularly effective when applied to

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the basic principle of the present invention, Fig. 2 is a block diagram showing the electrical configuration of one embodiment of the invention, and Fig. 3 is a waveform showing the audio I word of language learning materials. Figure 4 shows the diagram of each signal when the group language learning device shown in Figure 2 is to store the audio signal shown in Fig. It is a figure which shows the output signal of the group language learning device which memorize|stored the signal. 10...... Random access memo'l (R
AM) 11・・・・・・・・・Temultiplexer (D-
MPX) 20...Address register 21.
......Adder 22...Multiplexer l (MPX,)
23...Multiplexer 2 (MP
2) 24...Multiplexer 4 (M
P X4 )25...Multiplexer 3
(MP X3) 26...Multiplexer 5 (MP Written amendment (white side 583 2) Kazuo Wakasugi, Commissioner of the Patent Office, Tsukimasuguchi, Showa Iwa 1, Indication of the case, 1988 Patent Application No. 4276 2, Name of the invention Group language learning device 3, Person making the amendment Relationship to the incident Patent applicant address: 6-7-35, Kitashinayo, Tokyo Parts Store Name (
21g) Sony Corporation 6 Sakaki Representative Norio Ohga 4, Agent 〒105 6, Column ``Detailed explanation of 1 invention of the specification subject to amendment'', Drawing 7, Contents of amendment (7-1) Details From page 8, line 20 to page 9 of the same book
The sentence "Then, the address register 20 supplies...R, AMIO" written across the third line of the page is corrected to the following sentence. "Then, the address register 20 supplies the RAM address signal RAP to the adder 21, and also sends the RAM address signal RAP to the RAM10 through the multiplexer (hereinafter referred to as rMPXJ) 122.
supply to. (7-2) [125 Cn5cc] J described on page 14, line 14 of the specification is converted to 1125 [μse
c] Correct it as J. (7-3) rD-MFXl 1 J described on page 19, line 20 of the specification as rD-Ml)Xi I
Correct it with J. (7-4) “Figure 2” in the drawing will be corrected as shown in the attached sheet.

Claims (1)

[Claims] A data signal obtained by digitally encoding an audio signal for teaching material at a predetermined sampling period is stored in a random access memory provided in a miscellaneous device, and a data signal to be supplied to each child device is read from the random access memory. A group language learning device characterized by performing division multiplex reading and distributing and supplying read data signals to each child device at a sampling period.