JPS59121933U - Broadcast receiver display circuit - Google Patents
Broadcast receiver display circuitInfo
- Publication number
- JPS59121933U JPS59121933U JP1392483U JP1392483U JPS59121933U JP S59121933 U JPS59121933 U JP S59121933U JP 1392483 U JP1392483 U JP 1392483U JP 1392483 U JP1392483 U JP 1392483U JP S59121933 U JPS59121933 U JP S59121933U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- output
- control circuit
- turned
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図・第２図は、従来の電界強度指示計。第３図〜第
５図はこの考案の一実施例を示し、第３図は発光ダイオ
ードの詳細外観および回路図、第４図はこの考案のブロ
ックダイヤグラム。第５図は電界強度とＦＭ−ＡＭの出
力電圧強度を示す図である。
図において、４は収納ケース、５は第１の発光体、６は
第２の発光体、７は第２のトランジスタ、８は第３のト
ランジスタ、９・１０・１１は抵抗、１４は第５のトラ
レジスタ、１５は第６のトランジスタ、１６は第７のト
ランジスタ、１７は第８のトランジスタ、２８はコント
ロール回路、２９は第２の制御回路、３０は第３の制御
回路、３１は発振回路である。なお、図中、同一符号は
同一部分を示す。Figures 1 and 2 show conventional electric field strength indicators. 3 to 5 show an embodiment of this invention, FIG. 3 is a detailed external appearance and circuit diagram of a light emitting diode, and FIG. 4 is a block diagram of this invention. FIG. 5 is a diagram showing electric field strength and FM-AM output voltage strength. In the figure, 4 is a storage case, 5 is a first light emitter, 6 is a second light emitter, 7 is a second transistor, 8 is a third transistor, 9, 10, and 11 are resistors, and 14 is a fifth , 15 is a sixth transistor, 16 is a seventh transistor, 17 is an eighth transistor, 28 is a control circuit, 29 is a second control circuit, 30 is a third control circuit, and 31 is an oscillation circuit. It is. Note that in the figures, the same reference numerals indicate the same parts.
Claims (1)
分割されて入力される第１のトランジスタと、この第１
のトランジスタの出力を受けて第１の発光体をドライブ
する第２のトランジスタと、上記の電圧を同時に受けて
第２の発光体をドライブする第３のトラレジスタスタと
、第１の制御回路からの出力により上記の電圧をオン−
オフする第４のトランジスタと、第１の制御回路からの
出力により発振を開始する発振回路と、第２のトランジ
スタに接続されてこれを発振回路からの出力を受けてオ
ン−オフさせる第５のトランジスタと、同時に第２のト
ランジスタに接続されてこれを第２の制御回路からの出
力を受けてオン−オフさせる第６のトランジスタと、第
６のトランジスタに接続されてこれを第１の制御回路か
らの出力を受けてオン−オフさせる第７のトランジスタ
と、第３のトランジスタに接続されてこれを第３の制御
回路からの出力を受けてオン−オフさせる第８のトラン
ジスタとからなる表示回路。a first transistor into which a voltage that changes depending on the strength of the electric field is divided by a plurality of resistors and input;
a second transistor that receives the output of the transistor to drive the first light emitter, a third transistor that simultaneously receives the above voltage and drives the second light emitter, and a first control circuit. The above voltage is turned on by the output of -
a fourth transistor that is turned off, an oscillation circuit that starts oscillation by the output from the first control circuit, and a fifth transistor that is connected to the second transistor and turns it on and off in response to the output from the oscillation circuit. a sixth transistor connected to the second transistor and turned on and off by receiving an output from the second control circuit; and a sixth transistor connected to the sixth transistor and turned on and off by receiving an output from the second control circuit; a seventh transistor that is turned on and off by receiving an output from the third control circuit; and an eighth transistor connected to the third transistor and turned on and off by receiving an output from the third control circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1392483U JPS59121933U (en) | 1983-02-02 | 1983-02-02 | Broadcast receiver display circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1392483U JPS59121933U (en) | 1983-02-02 | 1983-02-02 | Broadcast receiver display circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59121933U true JPS59121933U (en) | 1984-08-16 |
Family
ID=30145298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1392483U Pending JPS59121933U (en) | 1983-02-02 | 1983-02-02 | Broadcast receiver display circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121933U (en) |
-
1983
- 1983-02-02 JP JP1392483U patent/JPS59121933U/en active Pending
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