JPS59121431A - Discriminating circuit of character code - Google Patents

Abstract

PURPOSE:To process a sentence containing KANJI (Chinese character) and KANA (Japanese syllabary) in a simple and quick way by referring to a flag register to discriminate whether the 1st byte of the data transferred on a data bus is equal to the 1-byte data of an information exchanging code or the 2-byte data of KANJI code for exchange of information. CONSTITUTION:A comparator 5 compares the data (9F) 16-notation stored in a register 3 with the 1st byte of a register 2, and a comparator 6 compares the data (EO) 16-notations stored in the register 4 with the 1st byte data of the register 2. The outputs of both comparators are sent to a control circuit 8 via an AND circuit 7. The circuit 8 performs comparison and discrimination on the basis of the highest bit value of the 1st byte data of the register 2 and the output of the circuit 7. Then the result of discrimination of the 1-byte data of code for exchange of information or the 2-byte data of KANJI code for exchange of information is stored to a flag register 9. Then the register 9 is referred to for discrimination of the 1st byte of the data transferred.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a character code identification circuit for identifying information exchange codes and information exchange Kanji codes that are mixed in data.

Structure of conventional example and its problems Traditionally, symbol-like codes used for information exchange were 8-bit, 1-byte codes such as ASCy codes and JIS codes, so data containing information exchange codes processing was a single byte unit, but as Japanese information processing became widespread, it became necessary to encode kanji and hiragana, which were not previously used, and the conventional 1-byte code was unable to do so. Because not everything can be coded,
It is encoded in 2-byte units like Kanji codes for information exchange. Therefore, the conventional single-byte processing has become a complex process involving a mixture of 1-byte information exchange codes and 2-byte information exchange Kanji codes, making it possible to realize one-Japanese information processing. The complicated processing of mixing two types of code systems was a heavy burden on program creation.

Purpose of the Invention The present invention has been made to solve the above-mentioned conventional problems, and is capable of handling 92 types of information exchange codes by identifying the information exchange codes and information exchange Kanji codes that coexist on the data bus. It is an object of the present invention to provide a character code identification circuit that makes complex processing involving mixed code systems simple and fast.

Structure of the Invention In order to achieve this object, the present invention provides a data register capable of latching data on a data bus, a first register and a second register for storing comparison data, and a third register and second register that can latch data on a data bus. It has a first comparison circuit and a second comparison circuit that respectively compare the data of the two registers, and compares the data of the data register with the data of the first register and the second register by the first comparison circuit and the second comparison circuit, respectively. The control circuit identifies the character code from each comparison result and the data value of the data register, and stores the identification result in the flag register.
This makes it possible to know the identification result simply by referring to the flag register.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawing is a block diagram of a character code identification circuit showing an embodiment of the character code identification circuit of the present invention. In the drawing, 1 is an 8-bit or more data bus through which data including information exchange codes and information exchange Kanji codes is transferred.
2 is a register that can latch the data on data node 1.

Register 3 and register 4 store comparison data that is compared with the data on data bus 1 latched by register 2, and the data in register 2 and the data in registers 3 and 4 are stored in comparison circuit 6 and comparison circuit. 6, and the outputs of the two comparison circuits are input to AND gate 7,
The output of AND gate 7 is input to control circuit 8. The result identified by control circuit 8 is stored in flag register 9. A data bus control line 1o for controlling the data bus 1 is input to the control circuit 8.

The operation of an embodiment of the character code identification circuit configured as described above will be described below.

The code system applied to this embodiment is as follows.

1) The code for information exchange in 1-byte units is an ASC■ code and a J-S 8-bit unit code.

2) Kanji code for information exchange in 2-byte units is JISC-6
The first byte of the code defined in 226 is (so)1e
decimal〈1st byte ((AO) hexadecimal and (DF) hexadecimal〈
The second byte is a code obtained by a code conversion method in which the first byte is soft to satisfy the condition of hexadecimal <(FF), and the second byte is software to satisfy the above condition of the first byte.

In the figure, data on a data bus 1 of 8 bits or more to which data including information exchange codes and information exchange Kanji codes are transferred is - a control circuit to which a data bus control line 1o that controls the data bus 1 is input. 8 is latched into the register 2 in correspondence with the data bus control line 1o, and the latched data is input to the comparison circuit 6 and the comparison circuit 6 and control circuit 8. Comparison circuit 5 compares the data (9F) hexadecimal stored in register 3 with the first byte data of register 2, and comparison circuit 6 compares the data (10) 1e hexadecimal stored in register 4 with the data (10) hexadecimal of register 2. The first byte data are compared, and the outputs of the comparison circuits 5 and 6 are input to an AND gate 7, and the output of the -AND gate 7 is input to a control circuit 8. In control circuit 8, register 2
The first node (the most significant bit value of the item data and the output of the AND gate 7, i.e. -(9F) based on 16, the first node data <(ICO) based on 1s), the first
The identification shown in the table is performed, and the identification result of whether it is 1-ite data of the information exchange code or 2-ite data of the information exchange kanji code is stored in the flag register 9.The most significant bit value of the first byte data is Since "o°" indicates a 1-byte code, the output of the -AND gate 7 is applied when the most significant bit value of the first byte data is "1°".

Therefore, the first byte data of the data transferred using data bus 1 is the 1st byte data of the information exchange code, or the 1st byte data of the 2-byte data of the information exchange code.
It is possible to identify whether it is a byte or not by simply referring to flag register 9.
It is designed not to be affected by bites.

As described above, according to this embodiment, the first bit of data transferred on the data bus of 8 bits or more is 1-byte data of an information exchange code or 2-byte data of a Kanji code for information exchange. can be identified simply by referring to the flag register, which has the advantage of simplifying and speeding up complex processing involving the coexistence of two types of code systems when processing Japanese information that includes both kanji and kana.

As described in detail, the present invention uses a flag register to determine whether the first byte of data transferred on a data bus is 1-byte data of an information exchange code or 2-byte data of a Kanji code for information exchange. Because it can be identified just by reference, it not only has the advantage of simplifying and speeding up complicated processing involving two types of code systems when processing Japanese information containing kanji and kana, but also makes it easier to process Japanese information that includes both kanji and kana. By incorporating this circuit into a processor that performs processing, the above identification result is set in a flag when data is accessed.

The present invention has the advantage that it can be applied to processors that can easily and quickly perform complex processing as described above just by determining the flag.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the character code identification circuit of the present invention. 1... Data bus, 2, 3.4... Register, 6.6... Comparison circuit, 7...
AND gate, 8... Control circuit, 9...
-Flag register 10... Data bus control line.

Claims (1)

[Claims] a data register capable of latching data transferred on a data bus; a first comparison circuit that compares data in the data register with data in a second register storing first comparison data; and a second comparison circuit that compares the data of the first comparison circuit and the data of the second register storing the second comparison data, and a second comparison circuit that compares the data of the second comparison circuit and the second comparison circuit, and A character code identification circuit specially designed to include a control circuit that determines the identification of a character code, and a flag register that stores the identification result of the control circuit.