JPS59117843A - Data transfer control system - Google Patents

Abstract

PURPOSE:To obtain a data transfer control system at low cost by constituting the code of data packet of an HDLC format and the control signal of a short frame in the packet transfer between plural computers via an exchange. CONSTITUTION:When a work station WS 1 being a computer communicates data by packet exchange via a node processor NP7 of an exchange to a computer WS4, the WS1 encodes the data packet in the HDLC format and the control signal in the HDLC format so that an interval between flags is a short frame and transmits them to the NP7. A line corresponding section LINF(l) 8 of the NP 7 uses the control signal of the short code constitution for the processing only for the WS 1 and the LINF(l) 8, stores only the data packet and the data packet is transferred to the WS 4 via an LINF(m) 9. Thus, the data transfer control system of low cost is obtained without requiring a special control interface line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data transfer control system between a computer and a switching device, and in particular, the present invention relates to a method for controlling data transfer between a computer and a switching device.
It has an unusual short frame structure in terms of format,
The present invention relates to a data transfer control method that transfers data packets in an easily identifiable information format so that the receiving side ignores them as data packets.

[Technology background]

FIG. 1 (- As shown in the example, when data communication is performed by packet switching between workstations (computers) via a node processor (switching device) NP, there is generally a communication between the workstation and the NP internal line correspondence unit LINF. A method is used in which control signals are used to check whether the buffer memory of the other party is empty or full, and data is then transferred.

In this way, other than data packets sent and received between end-to-end workstations (2.

An example of a method using control signals will be explained with reference to the control sequence diagram in FIG. 2.

Figure 2 shows the source workstation C1), the destination workstation (-), and the line corresponding part L of the NP.
Control signals sent and received between INF (J) and (s) 8 END G, , RECV Rgq, ,
RECV G, and.

A sequence of data packets DataP is shown.

NP is a transmission buffer memory S in LINF.

When the BtLF becomes empty (2), a send permission signal 5 is sent to the source workstation to prompt it to send a data packet.
Send ENDG. Similarly, NP is also. When the reception backup memories R and BμF in LINF become full.

A reception request signal RECVRgg is sent to the receiving workstation (2) requesting reception of data.

send. When the reception destination workstation completes reception preparation, it returns a reception permission signal RBCVG to the NP.

Like this, the control signal of 5ENDG or RECvG is received and received, and after confirming that the other party is in a receivable state, the data bucket (Data bucket) is transferred.

Conventionally, in order to transmit and receive these control signals and data, devices have been configured using one of the following two methods.

(2) Transfer both end-to-end data packets and buffer control signal packets using an LSI such as HDLC (high-level data link control procedure).

(2) Only data packets are transferred using an LSI such as HDLC, and buffer control signals are sent and received using a separate (=dedicated) control line.

However, according to method (■), each line corresponding section of the NP LIN
F has functions equivalent to HDLC LSI.

A packet disassembly and assembly function is required. Therefore.

Conventionally, these functions have been realized by hardware such as LSI and software by a processor, but as the scale of hardware increases.

Packet analysis is performed using software.

The disadvantage is that it takes a long time.

On the other hand, according to method (2), the only function required in each LINF of the NP is the buffering control function for data packets, but there is a need to cross many interface lines between the workstation and the NP. The distance between the workstation and the NP is sometimes several hundred meters or more, which makes it uneconomical, and the workstation is also installed in a general office, which causes handling problems. There was a drawback.

[Object and structure of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer control method that improves the drawbacks of the conventional method described above, does not require an increase in the number of interface lines between a workstation and an NP, and has a simple LINF hardware configuration.

The main point of the present invention is to focus on the fact that ordinary HDLC LSIs have a function to ignore short frames that are less than a specified value.
Since the LSI does not respond to control signals, separate means for detecting only the control signals is provided so that the control signals can be easily distinguished from the data packets.

To achieve this, the present invention provides a system in which a plurality of computers are connected to a switching device having a data storage and exchange function via a communication line, and packets are communicated between the plurality of computers. Data buckets transferred to to-end))i, control signals transferred in HDLC format and used only between computer and switching equipment.

It is characterized in that it is encoded and transferred in the HDLC format so that the length between flags becomes a short frame.

[Embodiments of the invention]

The present invention will be explained below based on examples.

FIG. 3 shows the HDLC frame format. In the figure, F is Flet51 indicating a frame boundary, and is represented by a pattern "01113110".

A is an address field indicating a data transfer destination, and C is a control field, which holds frame type, transmission or reception sequence number, and other control function bits.

Engineering is an information field.

Transfer data is placed. Fe2 is a frame check field in which a CRC code is placed.

9 The main functions of a typical HDLC LSI are as follows.

■ Sending out F l a g pattern for synchronization.

■ Guaranteeing the uniqueness of synchronization patterns by zero insertion and zero deletion - Sending side: 7 Rays 1 (A, C, I, Fe2).

If there are five consecutive 1's, '0' is inserted unconditionally.

In other words, it is ensured that six consecutive '1's do not form an F pattern.

Receiving side: After 5 consecutive “1”s in the frame, the receiver receives '0'.
”, delete it. In other words, delete the “0” inserted on the sending side and restore it.

■ Flag Short frames within 25 bis are ignored.

■ Continuous transfer of Fal during idle time.

■ Between the software functions of the processor, A.

C, I par) data is interfaced.

FIGS. 4 and 5 are block diagrams of an embodiment of the present invention constructed based on the prior art described above. Figure 4 shows
The configuration of the line corresponding section LINF in the node processor NP is shown, and FIG. 5 shows the configuration of the transmission adapter of the workstation. Further, FIGS. 6(α) and (h) show a schematic operation flow.

In Fig. 4, 1 and 4 are workstations.

2.5 is the host processor, 3.6 is the transmission adapter, 7
is the node processor NP, 8.9 is the line support section LI
N F (J), (m), 10 is a transmission buffer memory S, Bu, F, 11 is a reception buffer memory R, BtLF.

12 is a control signal detection circuit 5LDET, 13 is a control signal generation circuit Si GEN, and 14 is a packet detection circuit PK.
TDET, 15 is a data bus contention prevention circuit cNT.

16 is a bus driver/bus receiver circuit DV/RV, 1
7 is a selector switch SEL, 18 is a data bus, 19
indicates a control bus, and 20) i control bus control circuit Loopgr.

In FIG. 4, Si DET 12 , Si
GEN] 3°5BL17 are the characteristic components added according to the present invention.

In addition, in FIG. 5, 2α is the microprocessor MPU
, 2A is a main memory, and 2c is a control memory, which are components of the host processor 2 in FIG. 3 is a transmission adapter, 21 is an HDLC controller, 22 is a selector switch control output port 5WCNT, 23 is a control signal detection circuit 5iDET, 24 is a control signal generation circuit 8i
GEN, 25 is a selector switch SEL, and 26 is a processor bus.

Control signal 5ENDG, used in this embodiment.

RECVRgg, RECVG have a short code structure that is an abnormal short frame in the HDLC frame format and is therefore ignored. An example is shown below. Note that (X) represents hexadecimal display.

S END G, :Flag-X'''01'''-
FlagRBCVRgq: Flag ・X”+02
”-FtagRECV G, :Flag・
X "03"-Fitag First, the operational functions on the NP side will be explained according to FIG. Workstation 1
The signal sent from NP is LINF(J)
of S, BtLFlo and 5iDET12. The S number DET12 has a pattern matching detection circuit, and the second
The RECVG signal shown in Figure 2 and the start and end signals of the data packet are detected. The SiBuFIO is controlled by the start and end detection signals of the data packet and stores only the data packet in the received signal.

The case where a signal is sent from LINF to workstation 1 is as follows.

1) S, BuF 10 becomes empty, and R, B
When zcF11 is empty, the 5ENDG signal generated by 8iGEN13 is sent out via 8BL17.

1i) After R, BuF1-1 is full, RECVG,
The RB CV Rg q signal is sent until the RB CV Rg q signal is received.

1ii) After receiving the RE CV G, signal, R, Bml"1 until all data packets have been sent.
Send the contents of 1.

ly) S, BuF 10 in use, R, BuF
When ll is empty, Play is sent.

Although the function of the exchange control section of the NP is not directly related to the present invention,
For example, 8. After storing data packets in Bt and FIO, the data packets are transferred onto the data bus 19 in bursts. Also, R, BuF from data bus 19]
PKTDET is used to import data packets into
14.

The PKTDBT 14 constantly monitors the data bus 18, and when it detects a data packet with an address (A field) directed to it, it sends it to R, BμFl.
Work on l. The CNT 15 uses the control path 19 when performing an exchange.

Control is performed to prevent data bus contention and rival R, B+LF contention.

Next, the operational functions of the workstation shown in FIG. 5 will be explained. FIGS. 6(α) and (h) schematically show the operational flow.

The transmission adapter 3 constitutes a direct interface from the processor bus 26 to the NP, and connects the 9 functional blocks 21, 2.
2.23 is an input/output port for MPU2α. According to the program stored in the control memory 2C, the MP02g executes the sequence shown in FIG.

The HDLC 21 follows instructions from the MPU.

According to the jHDLc frame format shown in FIG. 3, the F, A, and FCS parts are assembled before and after the data and transmitted, or the received data packet is disassembled to check for abnormalities, and the data part is handed over to the MPU 2α. Also when Idol.

Continuously transmit Flα1 pattern.

The 5WCNT22 executes the 5WCNT22 according to the instructions from the MPU2α.
Switch EL25 and check the output of HDLC21, that is, data packet or idle flag, S i
The output of GBN 24, RBCVG shown in FIG.
Send any signal.

S i D B T 23 identifies the control signal sent out from the NP, 8ENDG, signal or RECVRg
q.

When a signal is detected, it notifies the program side by setting the designated bit of the input/output port in the 9th circuit.

For example, when the 5iDET 23 receives RF or CVRaq, it secures a memory area for receiving the data packet, sets registers in the HDLC 21, etc.

Next (= Switch SFliL25, send the RBCVG signal from 8iGEN24 to NP, and as a result, when the beginning of the data packet transferred from NP is received, 8E
Switch L25 to HDLC21 side. The HDLC 21 transfers the received data to the MPU 2α.

〔Effect of the invention〕

As mentioned above, according to the present invention (=according to the conventional HDLC
The controller LSI is used as is to transfer data packets and control signals.

9. By making the short frame code structure ignored by the HDLC controller and detecting it with another simple hardware circuit. A low-cost data transfer control system can be realized without the need for special control interface lines.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a data communication system using a general node processor, Fig. 2 is a control sequence diagram, Fig. 3 is an HDLC frame format diagram, and Figs. 4 and 5 are diagrams of an embodiment of the present invention. Configuration diagram, Figure 6 (α), (h)
is an operation flow diagram. In the figure, 1 and 4 are workstations, 2.5 is a host processor, 3.6 is a transmission adapter, 7 is a node processor NP, and 8.9 is a line support unit LINF (7), (→, 1
0 is the transmission pie 7 memory 8. B@LF. 11 is a reception buffer memory, R, BWF, 12.23 is a control signal detection circuit 8iD'ET, 13.24 is a control signal generation circuit 8iGEN, 17.25 is a selector switch SEL, and 21 is an HDLC controller. 22 represents a selector switch control capo 8WCNT. Patent Applicant Fujitsu Limited Representative Patent Attorney Fumihiro Hase (and 1 other person) 1 Eyes λ Figure P 't-3 [D

Claims (1)

[Claims] In a system in which multiple computers are connected via a communication line to a switching device having a data storage and exchange function, and packets are communicated between the multiple computers (-), packets are transferred end-to-end between the computers. The data packet is H
A data transfer characterized in that control signals transferred in DLC format and used only between a computer and an exchange device are encoded and transferred in HDLC format so that the length between flags is a short frame. control method.