JPS59117359A - Bidirectional digital data communication equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates generally to bidirectional digital data communications, and more particularly to PSK communications for communicating with digital data processing devices.
(Phase Keying) Transmission and reception of PSK modulated signals using a modem over a pair of wires at different frequencies. It is about compassion.

Discrete component bidirectional digital data transmission devices are well known in the prior art. These devices include PSK type modem components.

Single semiconductor Tetsuzori FSX (Frequency Shift Keying)
Modems are known in the prior art. No. 269,214 [Integrated Circuit Fs+x
See "Modem." FSK schemes have certain disadvantages in that they require large bandwidths and relatively slow data rates.

The PSK modem used in this invention provides all the necessary modulation, demodulation, and filter functionality on a single chip. The analog functions of the circuit are implemented using switched capacitor technology.

The digital data processing device is connected to transmit digital data to and receive digital data from a PSK modem fabricated on a single semiconductor chip. Switched capacitor technology is used for analog functions implemented in the form of field effect transistors and capacitors.

In particular, field effect transistors are metal oxide semiconductors (MO
SFET). The digital circuit of this invention is also MO
SFET is used.

Switched capacitor technology is known (December 1, 1971E)
(See Bell System Technical Journal, Vol. 58, No. 10, Issue 0), which in the preferred implementation corresponds to a resistor combination connected to one input of an operational amplifier, but not connected to the other inputs of the same amplifier. is connected and its output is fed back to its one input via a capacitor.

The modem transmitter includes a buffer adapted to communicate with various types of modem receivers at the other end of the line. The transmit buffer is bypassed when the digital data processing device operates synchronously with the corresponding device at the other end of the line. Depending on the modem protocol, the buffer scrambles the digital data and the PSK modulator modulates the carrier frequency appropriate to the selected protocol.

When the bit rate from the digital data processing hardware is lower than the bit rate of transmission, the buffer adds a stop bit to the end of the character. The sharp buffer is
When the bit rate from the digital data processing hardware is higher than the required bit rate of the transmission line, one bit out of four stop bits or one out of eight stop bits, depending on the protocol selected. It also serves to remove the bits.

The transmitter portion of the modem includes an encoder that receives a train of digital pulses from the buffer and translates these pulses into phase shift information. In this preferred embodiment, 4
Phase PSK is used.

That is, phase shifts at 0 degrees, 90 degrees, 180 degrees and 270 degrees are significant and determined by the chosen protocol. Two bits (bibits) are required to represent these four phase shifts, and the dibits are produced by the encoder. The bi-bit is used to provide a clock date signal for the transmitter analog portion.

Transmission {H 4d analog part is made up of ■ channel and D channel. A date clock signal derived from one dibit is applied in one channel,
Key clock signals derived from other dibits are added on other channels, and these provide a digital representation of the channel combined with the cosine of the carrier. The channels are added at such times that they provide information combined with the sine of the carrier. The two channels are combined to provide a single channel PSK wave train.

The transmitter also includes a filter to receive the channel signal at Pf3 for the expected gain and phase distortion of a transmission line, such as a telephone line.

In this preferred embodiment, the modem's receiver receives P from the transmission line.
A filter is provided to receive the SK modulated waveform, and the filter is designed to compensate for telephone line O gain and phase distortion. The gain of the filter can also be adjusted by an automatic gain control circuit that optimizes the gain.

The carrier recovery circuit receives the modulated waveform into a filter, gain control P8, and separates it into an et channel (carrier cosine) and a Q channel (carrier sine).

A clock recovery circuit recovers clock timing from the ■ and Q data information to provide a clock to extract incoming information at the appropriate time.

The receiver includes an adaptive geometric filter for receiving E-channel (baseband) and Q-channel (baseband) information;
Unwanted signals cross-coupled from the combined transmission lines are removed from these basebands.

The receiver includes a decoder that decodes the sampled baseband information into dual-bit information that is combined to form a series of digital signals.

Finally, the receiver is equipped with a buffer that is bypassed in case of synchronously occurring data. When an incoming data character has more than one stop bit, the receiver ignores the pre-stop bits. If the incoming data lacks a stop bit, the buffer adds an appropriately wide stop bit to maintain synchronization. Also, if the incoming data is scrambled, the buffer does not scramble it. The generated digital data is then sent to digital data processing hardware.

The main object of the invention is to provide a data transmission device using an integrated circuit PSK model in which a single integrated circuit chip is virtually self-contained.

Another object of the invention is to provide an integrated circuit P with analog and digital functions implemented on a single semiconductor chip.
An object of the present invention is to provide a data transmission device equipped with an SK modem.

Another object of the invention is to provide a data transmission device with modulation, demodulation, filter, and clock and carrier detection functions on a single semiconductor chip.

Yet another object of the invention is to provide a data transmission device with an integrated circuit PSK motif implemented in switched capacitor technology using MOEIFET circuits to achieve analog functionality.

These and other objects of the invention will become more apparent in the detailed description below.

FIG. 1 is a block diagram of the entire device. Data terminal equipment 5 is shown as the digital, data processing hardware of the present invention. In this preferred embodiment, the terminal device 5 is described in detail in Texas Instruments Manual No. 2265938-9701, 1980 Edition,
This is a Texas Instruments Model 787 portable communications data terminal. The digital data processing hardware can of course be any digital computer, terminal device, or any other hardware source that sends or receives digital data.

A terminal device 5 is shown connected to a transmit buffer 11 having an output connected to a transmit encoder 12 . Transmit encoder 12 sends code information to transmit analog 13, which sends a PSK modulated waveform to transmit equalization circuit 14 (in this preferred embodiment). The above 5m circuit is clocked by the transmit clock made from the signal OSC N0, the PSK modulation waveform hill 0'VA is the receive filter 19 operated by the receive AGO 19VC which adjusts the gain of the input signal.
received by 8. The carrier recovery circuit 20 is the filter 1
6, separates it into a baseband signal, adaptively equalizes the baseband signal, and removes crosstalk between the transmitter and receiver transmission lines. The base phase signal is sent to a clock recovery circuit 21 and a receive decoder 22 which recover the clock used in the transmission to decode the baseband signal. The output of receive decoder 22 is shown input to receive buffer 23 .

From FIG. 2, a block diagram of the transmit buffer 11 is shown. The DTE clock generation circuit 25 receives a control signal FAS.
T and HLFSPD are shown having a clock input of 4 Mfiz. Its output is 1 6 XDTE, which is the input of start-stop counter 60. The output of the start/stop counter 60 is the output of the character bit counter 6.
5, input sampling circuit 75, and DET-8C! T sink circuit 130 is the signal DTE applied to VC. Character bit counter 65 also has signals C1 and C2f: which determine the length of the added character. Its output, signal ENDOHAR, is sent to stop bit detection circuit 70. The input sampling circuit 75 receives the applied input signal XM.
TD i and its output goes to stop bit detection circuit 70 and FIFOloo. The output signal 5TOP of the stop bit detection circuit 70 is sent to the DTE-EIOT sink circuit 130.
Then, the process proceeds to the start/stop counter 60.

Input BELL/RV X' FAST and 4 MHz
A SOT clock generation circuit 40 having an output clock 16XSCT provides an output clock 16XSCT that is applied to an SCT clock circuit 90 and a DTE-8OT sink circuit 130. EIT
O clock circuit 90 is applied with control signal HLFSPD and its output signal NH30T is applied to DTE-8CT sink circuit 130. The output of the clock circuit 90 is FI
Also added to FOloo and stop bit insert/delete control circuit 140.

DTE-6OT sink circuit 130 provides output signals S 5TOP and 5DTE that are applied to control circuit 140 . The control circuit 140 is also coupled with the signal YO/8 and provides an output signal to the OUTP/DOWN counter 80 and the FOUT 100. UP/DOWN counter 80
also applies a signal to F engineering FO100. F engineering FOi 00
provides an output signal FOUT which may or may not be scrambled depending on the modem's selection.

6A and 3B illustrate the data terminal device (
FIG. 2 is a connection diagram of the DTE) clock generation circuit 25. FIG. Externally supplied oscillator square wave signal (4.03 in this preferred embodiment)
2MHz frequency, hereinafter referred to as 4MHz)
is applied to a buffer circuit 26 which provides a "false" output after inverter 27 and a "true" output after inverter 28, while the true output is applied to clock generation circuit 330. Clock generation circuit 3
3 provides clocks 1 and 2 that are 180° out of phase. The true output from buffer circuit 26 is inverted by inverter 29 and applied as an input to NOR gate 31 and as an enable signal for NOR gate 32. The output of inverter 29 is inverted by inverter 1'30 to provide the NoRr"-)32(') input and the enable signal for NOR/7""-gate 31. NOR gates 31 and 32 are crossed. Combined, NOR gate 31 provides clock 1 and NOR gate 32 provides clock 2. Clocks 1 and 2 are used for the timing of the DTE clock generation circuit 25, the pseudo-random shift register made up of these clip-flops by providing clock inputs for these clip-flops FF10-FF1B. The Q output of the 7-rip, 70-horn 10 is connected to the D input of the clip-flop 11, and its Q and. −
The output is programmable logic play (PLA) as shown.
3 Connected to B. The interconnections between the remaining clip-flops are identical, but of course PLA 3 B
There are variations in the devices selected in . exclusive OR
Circuit 34n7! j-supplies the exclusive ○R of the logic of the tube flops 14 and 18]~, supplies the D input of the clip 0.70 tube 10. The pseudorungs L, SHIFT and SHIFT rasters are connected in a known manner to provide an output signal 16DTE- which is 16 times the desired operating frequency.

What should be noted as we proceed with this specification is that the signal ptj3
+3' V (The following "-" represents the inversion of the signal,
In the drawing, the reversal is represented by a bar above the signal symbol. Signals FAST and HLFSPD, and their inverses select the PLAO line and connect circuit 25.
The counting operation is controlled in a desired manner to provide the desired function. The origin of signals FAST and HLFSPD will be explained later.

SOT clock generation circuit 40 provides the transmit data clock and is similar to circuit 25. its clocks 1 and 2
is the same clock generation circuit 41 as the clock generation circuit 33 described above.
is supplied to. The clock generation circuit 410 input is the same as the circuit 330 input, ie, it is a true output from buffer circuit 26.

The Q output of the 7 Ritsuzo clock 20 is connected to the D input of flip-flop 21 and is also connected to PLA 42. The remaining flip-flops 7'' are interconnected in exactly the same way.
The output is connected to the PLA. The devices selected within the PLA are performed as shown in a conventional manner to obtain the desired output. In this particular embodiment, the signal BELL/RV
and its inverse, and the signal FAST and its inverse are PLA
42 selection inputs. Exclusive OR circuit 45
provides exclusive OR outputs from flip clocks FF 25 and F'F 27. The exclusive OR circuit 44 is
Provides the exclusive OR output of flip clocks FF 21 and FF' 22. These outputs are in turn exclusive-ORed by an exclusive-OR circuit 43 whose output supplies the D output of flip-flop 20.

OR gate 48 receives its inputs from the first two lines of PLA 42, and OR gate 49 receives its six inputs from the next three lines of PLA 42.

NOR gate 46 receives its four inputs from lines 3-6 of PLA 42. AND) f″'-t 51 and 52 are OR date 48.4 with clock 1
Receives input from 9 and 9 respectively. hNDr-)51 and 52 are cross-linked NORr-53 and 540
Provide input. NOR date 53 is signal 16SCT-
and the NOR key "-) 54 provides a signal 16SCT, which is 16SCT at the frequency of the desired transmit input signal.
It's double.

Inputs C1 and C2 shown in FIG. 3B represent the number of bits in the particular character to be transmitted. That is, when they are combined, 8.9.10 or 11 bits are selected. Signals c1 and C2 are buffered through buffer circuits 61 and 62'ff: identical to buffer circuit 26, and the two outputs and their inverses are applied as select inputs to PLA 6B of character bit counter 65 shown in FIG. 6C. Added. Toggle Fritsuno Clock FF 35-
FF 38 provides a counting mechanism. The count is set by addressing the PLA 68 being combined. Flip-70 FF 39 provides an 11'' output on its Q terminal when a character of the correct bit length is read, clocking 7-bit flop 70, the stop bit detect flip clock.

The Q-output of the stop bit detection flip/70 tube 70 is:
"Start" bit is data manual XMTD and XMTD-
is '0' when received via rOJ, and the 'start' bit is also rOJ. The symbols "1" and "0" are entirely arbitrary, with "1" representing positive voltage and "0" representing 0 ports in this preferred embodiment. These values are "true"
It is sometimes expressed as ``and 1 false'' and ``1 no i'' and ``low'', respectively.

The Q-output of the stop bit detection flip clock 70 is “
0'' and is gated out by the Q output of flip-flop 39. 7 Rituzo Flop 70 Q-
The output is N0R) f″′-Toro301 inputs,
The output signal 16 DTE- is received by the output signal 16 DTE-. At the end of the startup bit, flip clock FF
The Q output of 39 goes to ``0'', thereby preventing any further transfer of the Q output of stop bit detect flip-flop 70 and outputting the signal i 6 DTE- to gate 63.
to be input constantly.

PLA6B is activated by signals C1 and C2 to provide 8.9.10 or 11 bit characters. P.L.
A 58 is Fritsuzo, 70 Tsuzo FF 35-FF38
provide a logic structure connected to the flip-flops to cause these flip-flops to count the number of selected bits.

The Q output of flip clock FF39 provides a preset input for each flip-flop FF35-FF313 and provides one input for NORr-)680, while the other input of the same gate is provided by signal DTE-. . The output of NOR date 66 is clip 70
The Q-output of the same seven flip-flops provides the clock input for flip-flop FF36, while the Q-output of the same seven flip-flops provides the clock input for flip-flop FF36. flip clock FF37
and Flfi' 38 are interconnected in the same manner.

Clip clocks FF 35-FF 38 all have their respective Q and Q-outputs connected to PLA 5 f3 as shown to ensure correct counts are obtained. The counting operation of the character bit counter is initiated by the 00 output from the Q terminal of rep clock FF 39 in conjunction with the [IDTE- signal while clocking flip-flop FF 35. Counting continues until the predetermined character pit length is obtained, at which point flip-flop 39 goes high, providing clocking for stop bit detect flip clock 70.

As mentioned above, the 16 DTP-signal is N0R4”-Toro3
゛Through Toggle Flip Flora 7' FF3
0- causes a counting operation of FF 33, thereby dividing the input frequency of 16 DTK by frequency DTE'4.

The modem of this invention can be used depending on the device that is compatible with the modem.
Designed to operate synchronously and asynchronously at various frequencies. By creating a frequency that is approximately 16 times the expected data rate o, it becomes possible to extract data near the midpoint of each bit.

This is illustrated in Figure 4, where the input data is illustrated as signal XMTD and the split sampling signal is illustrated as DTE. , DTKI shows a possible shift of 29.5 bits from the center, and DTE2 shows a 10.5% shift from the center. These movements are the result of different input frequencies.

This is the deviation that can be accepted, and the signal DTE is the 30th
The input sampling clip shown in the figure is used to clock the flip-flop's 7" FF 75, which has a data signal XMTD applied to its J input and a signal XMTI) applied to its input. The Q-output of flip-flop FF 39 is connected to the preset input of flip-flop FF 4 Q, which is clocked by the 5TOP signal.
added as one input.

The Q output from flip-flop FF 40 provides one input of NOR date 96, while the other input of the same date is flip clock FF 33 of start-stop counter 60, which also provides the J input of clip-flop FF 41.
is provided by the signal DTP- from the Q output of . NO
The output of R gate 96 provides an input to flip-flop 410 whose Q output is signal 5DTE- and whose Q-output is 5DTIn.

The Q output of the input sampling flip clock 75 is yoRq
The other input of the 0NOR gate 121 is 5T.
This is an OP signal. Input extraction flip flora f75(r
)Q-output provides one input of NORr-to 122, while the other input of the same date is provided by the 5TOP signal. The output of 1qoRif-) 121 provides input to the flip 70 FF48 and NOR date 1
The output of 22 provides the J input of flip-flop FF 48. The 7-lip, 70-tube FF 48 has 5STOP and 5STOP- on its Q and Q-outputs, respectively.
provide a signal. Extracted DTK and ST OP
Double signal therefore flip-flop FF 41 and 1
゛F48, as well as DTE, SOT, and
is generated by a combinational circuit illustrated as 5YNO130.

80T clock generation circuit 40 is shown in FIGS. 3A and 3B. Clock generation circuit 41, which is the same as clock generation circuit 33, receives input from oscillation buffer circuit 26 and provides output clocks 1 and 2. Clocks 1 and 2 are dynamic flip-flops FB" 20-
Provided as clock input for FF 27. These clip-flops and PLA 42, together with the logic introduced therein, are combined with a similar frequency circuit to provide output signals 16STO and 16sTc- at frequencies approximately 16 times the expected input data frequency. Provides a shift register. Frequency Jj31. is the input signal BELL/
RV and its inversion and added to PLA42. Great, FAST input and its inversion are also available in PLA.
May be added to 42. Flip 70s 7'
F・1”2O-FF27 Q and Q-output PLA
It is connected to the 42 JI^Uara line. An exclusive OR circuit 44 is provided with an exclusive OR function of the outputs of flip 0, clock FF'l1, and FF22. Exclusive OR circuit 45 provides an exclusive OR function of the outputs of flip clock FF 26 and FF 27. Exclusive O
The outputs of R circuits 44 and 45 (are the inputs of exclusive OR circuit 43, and the outputs of circuit 43 are flip 0 and clock F
Provides the D input of F 2 Q. SOT clock generation circuit 40f7) Output is provided from 1iox+r''-to 54.
No. 16 16SCT- provided from f-t 53 is provided from appropriate logic circuits 46-54 as shown.

Referring now to FIG. 8, the 80T clock circuit 90 is illustrated in detail. Flip clock FF 55-
FF 59 is a 16 sc'r clock generation circuit 40
The input signal 1.6 sc'r from the
Divide by 32 using all clocks. Signal 16 sc'r
clocks flip-flop 55, while its Q output clocks flip-flop 56, and so on. The Q-output of flip-flop FF55-FF58 provides the input for the NOR date 132.
9 is clocked by signal 80TA and its Q input is provided by signal DBTA, which is the 60011z clock. The Q-power of the 7 Rizzo flop 1rF59 is applied with the signal DBT-. AND gate 131 has signal HLFSPD and signal DBT-i applied as inputs and provides a final output to I;OR data 1-132. NOR gate 132 provides an input for NOR date 134 and, via inverter 133, provides an input for NOR gate 135. Signal 5OT- is each date 13
4 and 135 other inputs. N0R)f'+
- 134 provides an output signal NH8CT, N0R)f
- port 135 provides signal H80T. The Q-output from flip clock FF58 is connected to AND gate 1370.
Provide input. Signal cSEI is inverted by inverter 139 and provides the other input of AND gate 137.

It also provides one input of AND date 136 with the other input provided by signal TCLK. A
ND gates 136 and 137 output the signal SCT.
FIGS. 6B and 3C detail the structure of FIFO 100. The FO100, along with auxiliary logic circuits, includes six flip-flops FF50, -FF51 and FF5.
It is made from 2. The sampled data input of FIFO 100 is output as signal FalfoN (N0Rr-)1
20, is inverted by an inverter 119 and applied to the J input of the flip-flop FF52, and is also applied to the input of the flip clock without being inverted.

Signal PIFON also provides an input to each exclusive OR circuit 105 and 108 and AND gate 102. Flip-flop FF 52 is clocked by the signal MDTK, and its Q-power is exclusive OR data) 10
Provides 5 inputs. The other signals for this exclusive ORpt''-) are the signal BO and its inverse BO-.
F provides the J input of 51 and is inverted by inverter 116 to provide the input to F. flip clock F
The Q-output of F51 provides one input of the exclusive 0R) f''-gate 108, the other input of the four-digit signal B1.
and B1-. The output of exclusive-OR gate 108 provides an input to the J terminal of flip-flop FB"5.3 and is also passed through inverter 118 to
The same flip clock requires human power. Flip clock FF 51 has inputs provided by ANDNOR gates 10610 and 111.
) 112. Signals B1 and BO provide inputs to NOR gate 106, while the output of the same provides one input to AJD date 111, which is inverted by inverter 107 to AND 'y'
-) Provides 109 inputs. The signal MDTE is inverted by an inverter 115 to provide each AND data) 110
and L11'7) provide one input. Flip
The clock operation of the clock FF 5 l depends directly on the values of the signals B1 and B1-.

Slip 70 knob FF 5 Q is 3 AND keys
The signal MDTE is clocked by a circuit 113 containing a NOR gate with a gate input; 114, circuit 1
13 two AND r-tris provide one input.

Signal EMPTY provides one input of the AND date and is also inverted by inverter 117 to provide another single input of the AND date of circuit 113 as shown. The output of inverter 117 is an AND key.
) 103. Circuit AND key
) 103 other inputs are slip 70 7'FF''5
is provided by the Q output of o. Signals BO and B1 provide NOR (G) 1010 inputs and EMP
AI goes up with TY signal, ID q" -) L O2
provides an output that is added as an input to the . Al
(D) f′″-ts 102 and 103 are signal FIFO
Provides input for NOR date 104 with output of UT.

As mentioned above, the transmit buffer provides various transmission speeds. The stop bit may be removed if the incoming asynchronous data is freezing fast with respect to the buffer's sending word capability. Asynchronous data speed. If the speed is exceptionally low, a stop bit may be added. This is FIFOl
oo, is accomplished by the interaction between up-down counter 80 and stop bit insertion/delete control circuit 140.

Consider first the up/down counter 80 shown in Figures 81!6B and M2C. The up/down counter 80 is a flip-flop FF42, Fp
43, FF 45 and FF 45 and associated control circuits. Each slip-flop is reset by No. G3 ETD- from the modem receiver circuit, which will be explained later. Slip-flops FF, 42 and Fil' 46 are clocked by the signal F[JP1
1. Ru. Flip 70 tube FIF43 and PF 4
5):j:Clocked by the signal F_DOWN. Exclusive 00 circuit 86 provides an exclusive OR of signals BQ and B1. The output of exclusive OR circuit 86 and its inversion by inverter 91 is output to exclusive OR circuit 83 .
Provides all 84.8γ and 88 inputs. Noritsuno Flops I'''b゛42, FF43, FF45 and F
F 45i. Nabi Vko. - Output, each, exclusive OR
1*: 1 path 83, 84, 87, and 88 other inputs. Exclusive. R circuit 83.84.87
and 88 outputs are the slip clock FF
'42, F all 143, provides the J input of FF 45 and FF 46, and the inverted input. Exclusive OR circuit 81 consists of 20-tube FF 42 and FI"
43 to output signal B.
Q and is inverted by inverter 82 Vc to provide an output signal BO-. Exclusive OR circuit 89
provides a mutual OR of the outputs of flip-70 uFF 45 and FF 46 to provide output signal B1, and inverter 94 provides signal B1-. It is.

FIG. 5 shows details of the stop bit insertion/deletion control circuit 140. r,
It is a II diagram. The extraction stop signal 5STOP is a flip
7e + 7' yb゛6 ocr) :r Provides clock input for human power and flip 7o 61.

Signal 5STOP- provides power to flip-flop FF 6Q. Slip 0 flop FF 5 Q. and. - Each output is a flip-flop FF
5 Provide manpower to J and I. Signal H80T provides a serial reset input of slip 0 clock 'FF51. Slip 0 Flora-i FF 61. Output (d) provides one input of Nox gate 143, but the other input of the same date is (U 1/8) from the receiving 1g circuit.
- Provided by. Noritsuno Nrobu FF (i
1.

The output provides preset inputs for toggle slip flora f FF 133 and FF 64 while NOR
The output of gate 143 is a toggle flip-flop F.
Provides a preset input for F52. Flip-flop FF 64 Q-output is 7 rip/70 tube FF
The Q output of FF63 provides the clock input of j@th order flip-flop FF62. Each 7-rip clock FF 52-FF
The Q output of 64 provides one input to NOR gate 144, while the output of the same r gate provides one input to NOR gate 145. The other input of NOR gate 145 is signal 5STOP-, the output of which provides the clock input for flip clock FF 64.

oRr-) 1460 One input is NOR gate 144
is the output of Flip Clock FF5.
This is the J output from 1. The output of oRr-to 146 is NA
ND r-) 1470 provides one input, while the other input of gate 147 is provided by signal B1. N
The output of ANDmate 147 is the signal DEiL1iiTE-
and this signal is inverted by inverter 148 and cross-coupled with NOR date 149.
51 inputs.

The output of NOR date 151 provides one input of NOR date 152, while the other input of gate 152 is provided by signal EMPTY, and the output of NOR date 152 is inverted to one input of exclusive OR circuit 153. The signal ADD- provides two inputs. Other inputs of exclusive-OR circuit 153 are signals NH8CT, DELETE- and H3OT. The output of circuit 153 is OR gate 14
2, while the other input of the same r-) is the signal 5STOP-. The output of OR gate 142, along with signal 5DTE-, provides the input of NAND gate 141, while the output of DATE 141 is signal MDTE, which provides the clock input of toggle flip-flop F60. .

Figure 9 shows F' which controls the operation of the UP DOWN counter.
Indicates generation of UP and F DOWN signals. Signal MDT
E is inverted by the inverter 177 and becomes N0Rr"-
signals B1 and B.
O- provides input for AN:Dr″'-)178.

Signals 5STOP and ADD- are ANDr-to 1800
Provide power. AND gates 178 and 180 are n
oRr-)1790 input, whose output is the signal FUP.

Signal H8CT is inverted by inverter 181 and N
Provides one input to OR gate 182. ``Signal 4PTY provides another input to NOR gate 182. Signals S 5TOP and DFiLETK- are AN
It provides the input of the D gate 183, but its output is l!
Provides another input for OR date 182.

The output of NOR date 182 is F_DOWN.

Figure 60 shows rtc in detail 7' CFIFOi 00
U O.

1.2 or 6 bits are retained. The contents are UP
It is controlled by a DOWN counter 80 and a stop bit insertion/deletion control circuit 140. Control circuit 140 receives a signal 1/8- from the receiver circuit, which when high indicates that the circuit provides one additional stop bit for every eight characters. If the signal is low, one stop bit is provided for every fourth character. When the stop bit is present, F
(2) Depending on the contents of F0100, an extra stop bit may be added or deleted. The control circuit 140 has six toggle flip-flops FF.
62-FF 64 keeps track when the stop bit is set. UP DOWN counter 8
0 is a Gray coded counter whose count is controlled by the state of signals F_DOWN- and F_UP which are sequentially controlled by various signals shown in FIG. If the speed of the incoming data signal is too high,
A stop bit is inserted at a certain point depending on the entry speed. If the incoming data rate is too slow, the stop bit is removed. The UP/DOWN counter 80 controls the setting of the FO stage and allows addition or deletion depending on the state of the FO.
The application of 5BEELLRv is shown. Also, 6DOBPS
The input is applied to a buffer circuit 171, which is the same as buffer circuit 26 (like buffer circuits 172-175), and is passed through an inverter 164 to an AND date 166 and a NOR
Provides a false output on date 163. The overspeed signal (0VSPD) is applied to buffer 172 as one input to its false output U NOR date 1670 and via inverter 161 as one input to AND data 162
used as one input. Synchronous/asynchronous signal (S/A
) is applied to buffer circuit 173 whose true output is used as one input of NOR date 156 and inverter 157'! i-via N0R1:f-to15
Used as one input of 8. Signal S/A also provides one input to NOR gate 167. Signal P
D is applied to a buffer circuit 174 whose true output is used as one input of NORpf-to 156 and as the second input of NOR date 160. N
The output from the OR gate 160 is the signal PE. The signal BELL/RV received from the outside is the buffer circuit 1.
75, whose true output is the final input of NORf''-) 156 with signal V22 as output and 140R)f''-to1 with signal VAD as output.
59 is used as the final input. The signal VAD is AND
It also provides one input for pf-to 162;
-) O output it - provides one input of the NoR date 163; The output from NOR date 158 is gate 163
The signal V22 provides the final input, the output of which is the signal HLFSPD.

The output from NOR/7' gate 167 is signal FAST.

This logic simply provides the signals used to control the various parts of the transmit buffer.

Now, from Fig. 7A, an important selection circuit is shown.
The signal S/A (synchronous/asynchronous) is the most important. That is, when that signal is high, synchronous mode is selected and all of the aforementioned circuits are bypassed. As shown, signal S
/A and signal XMTD provide the inputs of AND gate 181, while signal S/A- and signal FOUT provide the inputs of ANI) F"-gate 180. AND dates 180 and 181 are NOR'd. The output signal 5DATA- of the date 182 is the S/
Comes directly from 'OUT from XMTD when A is high or from F when S/A is low. Irukamojim・
Depending on the choice of protocol, the signal 5DATA- can be scrambled or sent to the flip-flop FF7Q.
- It is sent unscrambled through a 17-stage register created by FF 87. signal PE, i.e. N
The output from the OR date 160 is inverted by an inverter 183 and dated to a NOR gate 184.
One input of R gate 185 and AND gate 1
86 inputs. Signal 5DATA- is NO
R date 185 and
Provide input. The output of inverter 183 is NOROR
- provides one input of gate 188, while the other input of the same gate comes from the output of exclusive OR circuit 206 by line 207. The outputs of NORr-to) 87 and 188 are
Provides 0 Å force. r-) 189 and 190UNoR
r-) 1910 input.

These series exclusive OR circuits then output the signal 5DAT
A-'i Inverter 193 to flip-flop F
Add it to the J input of F70 or directly to the input. The Q and Q-outputs of flip-flop FF7Q are connected to the J and inputs of flip-flop FF71, respectively. Remaining flip-flop FF 72-
The interconnections between FFs 870 are exactly the same.

The exclusive OR circuit 206 is a flip 70-tube FF84.
and flip-flop: l? 'l? ' Provides exclusive oR44 capability of the output from the '87. Exclusive OR circuit 2
The output of 06 is applied to the logic described above, and the incoming data is transferred to a pseudo-random shift block constructed by flip-flops F'F 7Q -FF 87, depending on the state of signal PE, which is pseudo-random enable. Scrambled in the register. If PK is high, the 100th is scrambled by the contents of the 14th and 17th flip-flops. If PE is low, there is no scrambling operation. Modem The scrambling of some of the floor calls is to prevent long periods of time without any signal transitions, which could disrupt the operation of the phase-locked loops used in modems. If long times occur even with the scrambler method, a counter 208 is used to compensate for such contingencies.Counter 20
8 includes flip-flop FF85-FF g5. Signal HLFSPD and its inverse are added to exclusive OR circuit 194 V' along with signals DBT and 5CTA to provide signal SCMOK at the output of exclusive OR circuit 194. Signal SOMCK provides the clock input for toggle flip 0 clock FF 88, while its Q output provides the clock input for toggle flip clock TI"F 89, below the concave sphere toggle flip flop F on 94.Flip 70-tube FF 94
The Q and Q-outputs of are respectively flip clock F
Provide input to J and F95. Flip clock FB''95 is also clocked by signal 50M0K.

The Q output of flip-flop IFF 95 provides one input of NAND gate 192, while the other input of the same date is provided by the Q output of flip-flop FF70 of the scrambler. The output of NAND gate 192 is toggle flip clock FF8 B-I'
Provides 94 preset inputs.

Q-output of flip-flop FF94 is NOR)
184, while the other input of the same date is an inverted pseudo-random enable signal, as previously shown.

Counter 208 monitors the data passing through the scrambler by looking at the Q output of flip clock FFγ0, the first flip-flop in the flip clock chain. NAND date 192 presets flip-flops FF8B-FF94.

Continuous mark (1) from FF70) If IJ song exists, NAND r-) 19'2 output is O, flip-flop FF, 84-1, F94
When 0FF94 is set, which allows the count up of 0FF94, the signal FT causes the inversion of the next bit going to the scrambler. Good luck, Flip Clock FF
The 8-bit signal at 95 changes to cause a preset operation of the counter.

In this method, counter 208 receives one from the scrambler.
Once filled with a set of 1's, the next bit to the scrambler is forced to be a space following some protocol to prevent remote data loop packing.

The m7B diagram shows phase code logic with circuitry that determines the specific phase for a given modem protocol. That is, two bits of data (bi-bit) select four different phases. This selection for various protocols is shown in Table 1 below.

Table 1 BELL V 22 Generation (120011z) Generation (1200Hz)
Answer , (240011z) Answer (24
00Hz) 00 +90' 00
+27001 0 01
+18011 +270 1
1, +9010 +180
10 0V jl raw (2250Hz) Answer (115
0f(z)00 +270 00
+9001 +9.0 01
+27011' +180 11
+180'1[], 0
100 The current phase is added to the previous phase, with or without a phase shift. PLA l 9
8 receives inputs from logic circuits, but these inputs j
Next, the input depends on the modem protocol used. The answer/generation signal A10 is added to the AND gate 203, but the other inputs of the same date are BELL/RV-
It is. The signal v22 is applied to two inputs of the NOR gate 202, while the input of the same gate is an AND gate.
4203 output. Signal VAD is PL
A 19 Directly supplied to B, 1 force in/guita 19
It is inverted by 9 and added to PL8 to 98.

The output from NOR gate 202 is directly inputted and is also inverted by inverter 201.

The circuit 196 is constructed by a pair of AND gate inputs of N0RF"- and LFSPD-.
On one of the ND dates, the signal HLFSPD is also -)t!
It is added to the AND gate of 2. The Q output of the 71-nop flop FF 71 is added to the input of 4111 of one AND date, and the Q output of the flip-flop FF 70 is added to the other input of the 17) AND date. The output of circuit 195cONOR gate is signal D1-, which is applied directly to PLA 198 to output signal D1-.
It is inverted as 1 and is also added to PLA i 98. The Q output of flip-flop FF 7 Q is the signal D
2, the Q-output is the signal D2-, and each P
Added to LA 198. The output signal of PLA 198 is ABl depending on various choices.

It selects the device on the signal VADidPLA19B and also selects the selection circuit, especially the NOR key (211).
and AND gate 2130 provides one input.

Signal D1 provides another input to NOR gate 211 and one input to UAND gate 212.

Signal D2- is the 6th human power of NOR date 211 and A
l) D) f-Provides other inputs of gate 212. The outputs from NOR gate 211 and AND gates 212 and 213 provide three inputs to NOR gate 214,
The output signal AB 21rf of gate 214 provides one input of 2Zat adder 221. The sum is bit D
are represented by IN l and D output N2 and their respective inversions from the Q and Q- outputs of flip-flops F91 and FF92.

In short, the transmit buffer provides a digital circuit implemented in MOS for receiving asynchronous data and transmitting it in a synchronous format. If the received data is synchronous, the circuit is bypassed. The user can select the specific mode of protocol desired. When selected, a combination of dibits is set and the data may or may not be scrambled to select the appropriate carrier frequency.

FIG. 10 shows clock generation circuits 232 of FIG. 3A with inputs from clock pants 726, 180
A pseudorandom shift register 230 is shown fed with clock 1 and clock 2 that are 0 out of phase. Flip clock FFl0I-F10B is PLA 231
and combined logic circuits, pseudorandom
Configure shift register 230. The inputs of PLA 231 are signals VAD and its inverse, and A10 and its inverse.

The respective outputs of flip flop FF 107 and FFID 8 are exclusive ORed by circuit 235. 7 lip-flop l"l' 102 and F2O
The respective outputs of 3 are connected after exclusive OB by exclusive OR circuit 234. Exclusive OR circuits 234 and 23
Each output of 5 is a flip clock FF101.
are exclusive-ORed by a circuit 233 providing J inputs of . Clocks 1 and 2 are Flip FF
101-FF 108 is clocked. Output signals φ1 and φ1- are generated by selection circuit 236, and output signals φ2 and φ2- are generated by selection circuit 237.

NOR gate 238 has an input from PLA 231 and its inverted output is connected to flip Flora 7'jFF.
101-B'F108 provides preset inputs. Signals φ1 and φ2, and their respective inverts, provide clock signals for switched capacitor circuits used in the transmitter and receiver circuits. They occur at a rate 16 times faster than the desired carrier frequency.

FIG. 11 shows a circuit for generating sine and cosine r-to signals for the in-phase and quadrature analog channels to be described. Signals φ1 and φ2 are cross-coupled NOR'7''-) 242 and 243, respectively.
is input, and the output of NOR gate 243 is AND
/7'--provides input for 245. Selection signals VAD and A10 are applied to exclusive OR circuit 241, the inverted output of which provides the other input of AND gate 245 and directly connects one input of AND gate 244. ANDr”-t 244 and 2
The output of 45 provides the input of NOR'7'-to 247, the output of which is a flip-flop FF.
111 and is inverted and applied to the input of the same flip-flop. The Q output of the clip flon 71'FF111 is connected to the AND gate 244.
and clocks the toggle clip flop FB'112.

The output of NOR gate 241 provides one input of oRr-) 248, while the other input of date 248 is the signal φ
2- provided by. The output of OR date 248 is N
AND) f- provides one input of gate 249, while the other input of gate 249 is provided by signal φ1-. Clip clock FF111 is NAND)1″
' - is clocked by the output of port 249. This clock operation is based on Clip Flock FI!゛Provides 111 synchronization. The Q output of flip-flop FF112 clocks toggle flip-flop FF113, while the Q output of FF113 clocks toggle clip clock FF114. flip clock FF
The Q-output of 112 clocks clip-flop FF116. Q from flip-flop FF113
The output provides the J input of flip-flop F116;
The Q-output of flip-flop 'FF 113 provides an input to clip-flop F116 and clocks flip-flop F115. The Q output of flip-flop FF114 is the flip-flop FF1.
15 J inputs, and one input of circuit 2510 and one input of circuit 252. circuit 2
51.252.253 and 254 are identical to each other and are 1-to-2 with outputs providing inputs for NOR gates.
is made from input AND dates. The Q-output of 7 Ritsuzo flop FF 114 is connected to circuits 251 and 2
52 inputs. flip clock FF
The Q output of 115 is connected to 1 of circuit 253 and circuit 254.
Provide two inputs. Q-output is connected to each circuit 253 and 2
54 inputs. Signals φ1- and φ2-
Circuits 251, 252, 253 and 254 respectively
provides one input for the The output of circuit 251 is a cosine signal φ2. The output of circuit 252 is a cosine signal φ1. The output of the circuit 253 is a sine signal φ1Q, and the output of the circuit 253 is a sine signal φ1Q.
The output of 54 is a sine signal φ2Q.

FIG. 12 shows a digital circuit that generates a signal that determines whether a signal input to an analog circuit is inverted. Exclusive-OR circuits 256-259 provide output signals φ1L, φ2L, φILQ% and φ2LQ, respectively. Circuit 256 receives signals φ1- and DI:N1, and φ2- and DI:N1-.

The circuit 257 inputs the input signal φ1- and the input signal N1-1 and φ2.
- and D-engine N1 are received.

Circuit 258 connects signals φ1- and D-N2, and φ2- and D
Receives work N2-.

Circuit 259 receives φ1- and D-type N2-1 and φ2- and D-type N2.

If φ1L is equal to φ1 and φ2L is equal to φ2, signal VXMT is inverted. If φ1'LI is equal to φ2 and φ2L is equal to φ1, the signal VXM
T is not inverted.

Figure 16 shows the generation of the signals BBS and BBS- used in this transmitter circuit, which puts a top notch on the square wave to make it look a little like a sine wave.The signal DBT is applied to flip-flop FF 1180. input, inverted and applied to the J input of the same flip-flop. The clock is provided by signal 5OTA, which is inverted and the Q-output is applied to the input of inverter 262 with output signal BBS. The Q output of clip clock FF11-8 is inverted by inverter 261 to provide signal DBS-.

Before describing the analog circuit, reference should be made to FIGS. 14 and 15. Taken with Figure 11,
The generation of various digital signals is obvious. 11th
The signals φ1 and φ2 applied to the illustrated circuit are shown in FIG. 14 as non-overlapping clock signals. When transmitting with high band frequency signal A, clip clock FF
111 (Illustrated as DJ large input clock frequency divided by 2. Clip Flora 7'FF11
1 clock signal B is shown to occur in each of the signals φ1 and φ2 in the 0 flip-flop FF.
The output of '111, signal C, is shown at the same frequency as signal A, but displaced therefrom. 1st
In this portion of FIG. 4, the composite waveform results from the output of N0RPr9-to 243.

Next, a signal is created by disabling the output of NOR date 243 to provide a low band frequency.
In the ``transmit low band'' part, signal B is shown the same as signal φ2, and signal C is shown as signal B when it is in the transmit high band.
It is 1/2 of the frequency of .

FIG. 15 shows the signal passing through FIG. 11, but for the sake of clarity the frequency of signal C is clearly
It is illustrated as twice its frequency in the figure. In fact, it is shown on an expanded time scale. Signal D1, the Q output of flip clock FF112, is shown at 1/2 the frequency of signal C; signal E1, the Q output of clip flop F''l13, is shown at 1/2 of the frequency of signal F; , that is, clip flop FF11
The Q output of signal G, ie, flip-flop FF115, is shown at the same frequency as signal F, but shifted with respect to it; the Q output of signal G, ie, flip-flop FF115, is shown at 1772 of the frequency of signal E; Q
The output is at the same frequency as signal E, but shifted from it.

The inverted Q-output of clip 0 clock F'F116 is the signal OGT, and the inverted Q-output is the signal SGT
It is. The signal OGT is used to construct the top notch of the cosine signal, and the encrypted SGT is used to construct the top notch of the sine signal.
Used to configure the notch.

These are explained below.

As mentioned above, the four binary values (bibits) are represented by four phases, and these phases depend on the selected modem protocol. Since the four digital pits are represented by one phase shift, the baud rate is 1/2 the pit rate. As a standard, the baud rate is on the order of 600, while the bit rate is on the order of 1200 bps. Each pair of pits is used to select one of four possible phase shifts, depending on the answer or generation mode, the switch or the particular modem protocol selected.

From these selections four possible carrier signals 1150 and 2250 and 1200 and 2400 are obtained.

Now referring to FIGS. 16A and 16B, the transmit analog circuit 13 is shown. Reference voltage Vxmt is the voltage at which the switched capacitor circuit operates.

In this preferred embodiment, VXmt is +5'/2 V. The MO8 operating voltage is +5■. Reference voltage vxm
The first circuit in which the t% signals BBS and BBS- are added together with various phase signals provides level shifting, shaping and first order filter functions. When referring to field effect transistor components, electrodes alternately refer to source and drain, and are the sixth connection or date.

Voltage level Vxmt is applied to one electrode of transistor T2, which is dated by signal φILQ. The other electrode of transistor T2 is connected to one electrode of transistor T8 and one of each capacitor C3 and c4.
connected to two terminals.

The other electrode of transistor T8 is grounded and is turned on by signal φ2LQ. The other terminal of capacitor C4 is connected to one electrode of transistor T4, the other electrode of which is grounded and applies the signal BBS- to its date. The other terminal of capacitor C4 is also connected to one electrode of transistor T6, which is dated by signal BBS and whose other positive terminal is connected to one terminal of capacitor c8 and of each transistor T12 and TIO. connected to one electrode. The terminal of transistor T10 is grounded and is dated by signal φ2. The other terminal of transistor T12 is connected to the negative input of arithmetic JQ width amplifier 226 and one terminal of capacitor c7.

The positive terminal of operational amplifier 266 is grounded. Its output goes through the controller C7 and is connected to its negative input.
I'm here. The output of operational amplifier 266 is connected to transistor T14.
is connected to one electrode of the transistor T14U signal φ
1, the gate electrode and the other electrode are connected to the transistor T.
160 connected to one electrode, transistor T i 5
II) The sacrum electrode is grounded and footed by the signal φ2.

The part described in detail above sets the voltage reference level to VXnlt
The signals φ1, φ2, φ2LQ and φ
ILQ, gives a mixture by the interrogator. The violet action is achieved by adding signals BBS and BBS- which notch the square wave input to make the square wave more similar to a sine wave.The filter action n, conventionally produces the signal Qfout.
method is accomplished by operational amplifier 226 and associated components.

This is a quadrature signal. The generation of in-phase signals is illustrated above in the same circuit as described, except that the signal φ
1L work and φ2L work are φILQ and φ2LQO.
added instead. The output signal is f. It is ut.

Referring again to the signal Qf out, it is the series two outputs created by operational amplifiers 267 and 268, and 269 and 272, and their combined circuits.
is added to the 4th order filter section. The in-phase partial filter 270id has the same structure as the quadrature-phase filter 271. The use of in-phase and quadrature methods is known in the prior art, and the combined output signal is mixed with the cosine of the carrier wave. ut
Q mixed with s and the sine of the carrier. This is a relatively simple way to provide ut.

Signal worker. 8. is connected to one (7) electrode of the transistor T48 which is sidated by the signal φ2■, the other electrode is connected to one electrode of the transistor T49f7), and one terminal of the capacitor 027 and the capacitor 0
It is connected to one terminal of 28. Transistor T4
9 is gated by the signal φ1, and the other electrodes are grounded. The other terminal of capacitor 02B is connected to one electrode of each transistor T46 and T47.

Transistor T46 is dated by signal SGT, and the other electrode is grounded. Transistor T46 is the signal C
GT and the other electrode is connected to the other terminal of capacitor C21, which in this case is connected to capacitor 0.
37 and also connected to one terminal of a transistor T51 gated by signal .phi.2 and whose other electrode provides the negative input of operational amplifier 273.

Signal Q. ut is connected to one electrode of transistor T410, which is gated by signal φ2Q, and the other electrode is connected to one terminal of capacitor 0290 and one terminal of capacitor 031. It is also connected to one electrode of transistor T420, but transistor T42 is dated by signal φ1Q and the other electrode is grounded. capacitor 0
The other terminal of 29 is connected to one electrode of transistor T45, which is dated by signal cGT and whose other electrode is grounded.

One terminal of the capacitor (329 is also connected to the transistor T44
is connected to one terminal of transistor T44
is dated by the signal SGT and the other electrode is connected to one electrode of the transistor T43, and the other electrode is connected to one electrode of the transistor T43.
43 is turned on by signal φ1, and the other electrodes are grounded. One electrode of the transistor T42 is grounded, and is connected to the other electrode of the transistor T41 by the signal φ1Q.

Signal PSKout is generated as the output of operational amplifier 272 and its associated circuitry. That is, capacitor 032-
036 are connected together at one end to one electrode of transistor T47, while transistor T47 is connected to the signal φ2. has been done. The other electrode of transistor T48 is grounded and it is dated by signal φ1. Capacitor C32-0
The other terminals of 36 are connected to switches 5w1-5w4, respectively. Other terminals of switches 5w1-8w4 are
It is connected to the negative terminal of operational amplifier 273. They are also connected to one terminal of capacitor 036, while the other terminal of capacitor 036 is connected to the output of operational amplifier 273. Switches 5w1-5w4 are selectively activated by signals VLT, VHT, BLT and BHT, respectively. Signal VLT is connected to signals VAD- and A10
signal VHT is a NOR function of signals VAD- and A10; signal BLT is a NOR function of signals VAD- and A10;
and A10, and the signal BHT is the signal V
AD and A/〇-0NOR functions. Depending on the appropriate selection, the appropriate amount of capacitance can be switched in or out of the circuit to adjust the selected modem voltage and thereby set the appropriate P.
A SKOut signal is provided. It should also be noted that the shape of P SK □ u t depends on the signal VG, T added to the carrier cosine and the signal SGT added to the carrier 0 sine. The easy switching in and out of multimode circuit capacitors, such as that represented by operational amplifier 273 and its associated capacitors and switches to obtain the desired filter characteristics, creates parasitic capacitance problems. There is. From FIG. 17, a circuit is shown that eliminates the problem of parasitic capacitance. Figure 17 shows the signal ■. U,
An operational amplifier is shown, with its positive terminal grounded and a capacitor C connected between its output and its negative input. Its negative input is in series with transistor T51, which is gated by signal φ2 and whose counter electrode is connected to a capacitor with one terminal of 1C,
It is connected to one electrode of transistor T52 and one terminal of each transistor T59, T2O and T61. The signal vin is applied to one electrode of the transistor T55f/), while the transistor T55 is connected to the signal φ1
and the other electrode is connected to the transistor T54.
is connected to one electrode of capacitor KIC, the other terminal of capacitor KIC, and one terminal of 2C1 to 3C and 40 to each capacitor. 20. to the capacitor. 3C! The other terminals of 4c and 4c are transistors T61 and T2, respectively.
Connected to the other electrodes of O and T59.

Transistors T59, T2O and T61 are dated by signals M4, M3 and VCM2, respectively.

Transistors T56, T57 and T58 are connected to voltage references between capacitor 4Q and transistor T59, capacitor 30 and transistor T60, and capacitor 20 and transistor T61, respectively. These are the signals M~4%M3− and M
2- It is gated by Nyo. The circuit in Figure 17 is the 16th circuit.
It is noteworthy that the circuit resembles the output circuit in Figure A. For example, switch SW1 corresponds to a combination of transistors T56 and T59, and signals M4- and M4 are respectively data).
It is clear that it is added as a fig.

The absence of transistors T56-T5B creates problems when one or more capacitors are switched out of the circuit. Although the switching transistor used may have a high off-resistance, the capacitance between its terminals is still small. This capacitance is connected in series with the capacitor that is switched out.

The combination of these two capacitors is seen in parallel with other capacitors that are switched into the circuit. This creates a larger effective capacitance than desired. o The synthesized filter response is deflected from the desired response.

This problem is magnified by the number of capacitors being switched out of the circuit. When a capacitor is switched out of the circuit as shown in FIG. 17, the appropriate transistors T56-T58 are dated and the switched out capacitor is connected to the reference voltage. Thus, the switched out capacitor appears as a stray capacitance between the reference voltage and the stray insensitive connection point of the stray insensitive switched capacitor filter. Therefore, capacitors that have been sinched out no longer shift the filter response.

This switching device is used throughout the switched capacitor circuit of this invention.

The signal PSKout Yes1 is sent directly to the transmission line.

However, it has been found that both magnitude and phase are distorted by transmission over the commonly used telephone lines. To compensate for this distortion, another filter operation is performed. In the preferred embodiment, the signal PS
Kout is applied to a fourth order filter consisting of operational amplifiers 274 and 275 and associated circuitry as shown in FIG. Switches EI W 5-SV/23 are all described with reference to FIG.
Switched into the circuit by T. These capacitors provide the correct hell gain switch-in for testing purposes. The capacitor between the output of the filter and the switch sw (i and SW7) that receives the ALOT signal is
Signals VLT, VHT, BLT, O, respectively.
and the switch swB -swl operated by BHT.
1 selects from capacitors 059-062. In a similar manner, capacitors C47-050 are placed in the circuit between the input and output of operational amplifier 2γ4, selected by switches 5w16-5w19, respectively, activated by signals VLT-BHT as described above. Yet another bank of parallel capacitors 043-0, each switched by switches 5w12-5w15
46 is connected between the output of operational amplifier 274 and the input of operational amplifier 275. Switch 5w2O-sW
Another bank of capacitors C3l-C54, switched by 23, is connected between the output of operational amplifier 275 and its negative input. Capacitor 055-058
are connected in series with capacitors 047-050, respectively, to the output of operational amplifier 275 with output signal VO2T.

This filter described above is used to determine the magnitude of telephone line signal attenuation, etc. At this point, the signal VO2T is transmitted just below the telephone line. However, it has been found that the phase is distorted with magnitude, and in this preferred embodiment,
The signal o2T is the input of another 4th order filter with a capacitor and a sinch rebank as described above to compensate for phase distortion.

Although FIG. 19 shows this particular loading, signal VO2'T provides the input of a second order filter consisting of operational amplifier 276 at the input, operational amplifier 277 at the output, and associated circuitry as shown. Signal VO2T is the input signal from the output of the magnitude equalization filter of FIG. Capacitors 067-069 are selectively switched into the circuit via switches 5w25-5w27 by selection signals VHT, BHT and LBANDTK. Signal LBAND
T is the negation of the NOR function of signals BLT and VLT-. 1 for each capacitor 064.065 and 066
The two terminals are connected in series with capacitors C67, 068 and 069, respectively. Capacitor 064-
06617) The other terminals are connected together to one I7) electrode of each transistor T78 and T79. signal φ
The other electrode of transistor T79, dated by 2, is grounded. Transistor T78u is gated by signal φ1 and connected to one terminal of each capacitor c82-089 and the output of operational amplifier 277. The other terminal of the capacitor 082 is connected to the signal L ban
d connected to switch 5W35 operated by T-. The other terminal of switch s W 36 is connected to the signal V
LT, VHT are connected to one terminal of each switch sw2B-sw31 operated by XBLT and BHT respectively. Capacitors 071-074 are
5-sV/28-5W31, respectively. Capacitor Cγ5 is connected in parallel with the switch and capacitor combination from the output of operational amplifier 276 to the negative input. The positive input is grounded. The other terminal of the capacitor 083 is connected between the switch 5w28 and the capacitor 071. capacitor 084
The other terminal of is connected between the switch 5w30 and the capacitor Cγ3. Another bank of parallel capacitors C77-081 is placed between the output of operational amplifier 276 and the input of operational amplifier 2770. Signal V
Switches 5W32-8W35 operated by LT, VHT, BLT and BHT are connected to capacitor a
77-a80v are V-connected for switching, respectively. Yet another flat parallel capacitor 085-
089 is connected between the output of operational amplifier 277 and the negative input.
It has been placed. The positive input is grounded. capacitor 0
85-089 are selected by switches sW37-sw4Q, while signals VLT, VHT, BLT and BIT are the respective activation signals. Container C
90-C! 93 are connected in parallel, one terminal of each capacitor is both fed back to the circuit input, and the terminals of the pond are respectively connected to switches 5W37-8W40 and capacitor 085.
-088. Output signal TXALB
Now under the telephone source, ready for transmission, both magnitude and phase distortions are adjusted.

The waveforms shown in the M2O diagram generally indicate the conversion of a digital signal to an analog signal. Signal operator N1 is shown as a set of digital bits.

The bit pattern shown is 1.0, 1. ．． 1,0.0. The shaped input represents the desired waveform described above with the top of the digital waveform notched. It is noted that in the set of two 1's and two 0's, there is a notch between the two 1's and between the two O's, rather than a continuous level. Signal P
SKOut is a filtered analog signal corresponding to digital signal DIN1 before amplitude and phase attenuation is compensated for.

Signal ROVA is received at the other end of the transmission line and becomes signal TXPA after transmission and field distortion. The signal ROVA is the first
It is received by a receive filter section 18 shown in the figure. A certain control signal is utilized in the receive filter. To understand these signal sources, please first refer to FIG. Pseudo-random shift register 290 is PLA
300, flip clock 'FF121-Fl'l
27 and associated logic circuitry.

The 4 MHz clock is applied to clock generation circuit 293, which is the same as clock generation circuit 33 described above.

Clocks 1 and 2 from the clock generation circuit 293 are
Used to clock dynamic flip-flops FF121-FF127. flip flop FF1
The Q output of 21 provides the D input of flip-flip FF 122, and so on. Flip Flip Q
and Q-outputs all provide inputs for PLA 300. The 70 reset terminal of flip-flop FF 121 is grounded and signal R20 applies the preset input to the remaining flip-flops FF 122-FF 127. Clock signal CK from clock generation circuit 293
In addition to providing the input clock to Flip-Flip, 1 also provides the output signal FROKi. The Q outputs of flip-flop B″F126 and FF127 are AND
The Q-output t/'1 AND r+-gate from these 7 lip-flops provides 28,602 inputs. AND dates 285 and 286 provide inputs to NOR gate 287;
The output of this r-t 287 1t'xNoRr-) 289
Provides one input. Signal VAD-1L ban
d-1 and ALT provide the inputs for NOR date 288, while the output of this gate 288 is AND date 2
91 provides one input. Signal R20u, NORF
The output of ``''-) 289 and the output of AND)f''-) 291 provide the NOR date 2920 input. , the output of this gate 292 provides the D input of flip-flop FF 121. The selected line of PLA 300 receives signals 811-813,
R11-R13, 821-823, and R21-R23 are provided.

FIG. 22 shows the signals R21-R24 (NoRy-) 302
and the output of this date is the inverter 303.
A simple circuit is shown which provides an output signal 2o. At that time, R20 is always 1 when any of the signals R21-R24 is 1. Signal R as described above
20 provides presets to six flip-flops and provides gate operation to two gates.

FIG. 26 shows the generation of signal θ7. Signal 811-813
and 821-823 provide inputs for OR gate 294. Signals R11-R13 and R20 are OR-
295 input. The outputs of OR gates 294 and 295, along with the signal rr+cxl from FIG. 21, provide the two inputs of each AND gate 296 and 297, respectively. These two AND dates provide the inputs of cross-coupled N0R)f''-gates 298 and 299, while the output of gate 299 is inverted by inverter 301 to provide an output signal θγ.

FIG. 24 shows the generation of signals ALT and φ3 and φ4. Signal θ7 is toggle flip-flop FF12
9 and its Q output clocks toggle flip-flop FF128. flip flip F
The Q output of F 128 and F"FI 29 is NoR'f
-) ' 306 , the output of which is added to the NOR date 309 and via an inverter 307 to the NOR gate 308 . N0R) f + - gates 308 and 309 are NOR gates.
cross-coupled with the output of transistor T91
Provides a tate signal for The output from NOR gate 309 provides the gate signal for transistor T92. One electrode of transistor T91 is connected to the voltage VDD, the other electrode of 'rg1o is connected to one electrode of T920, and the other electrode of T92 is grounded. The connection between transistors T91 and T92 provides signal φ3.

The circuit that generates signal φ4 is the same as the circuit that generates φ3, except that the input signal is a flip clock 0F.
The signals ALT and Q- from l-'129.

FIG. 25 shows the generation of signals φ7 and φ8.

The signal θ7 is inverted by the inverter 311 and converted into a NOR
Provides one input for date 314. Inverter 31
The output of 1 is inverted by an inverter 312 and becomes a NOR
Provides one input for date 313. NOR gate 3
13 and 314 are cross-coupled. JOR gate 314 provides output signal .phi.7 and NOR gate 313 provides output signal .phi.8.

FIG. 26 shows the inputs of the receiver section of the modem. Input signal R
The OVA is applied to a continuous anonymous filter 18A. Filter 18A is comprised of a series resistor R1 connected in series with a parallel combination of resistor R2 and capacitor C101. The other end of resistor R2 is operational amplifier 281
Provide positive input for . Capacitor 0 other terminal is comparator 28
Connected to the negative input of 1. One positive input of comparator 28 is connected to AC! through capacitor 0102'. Bonded to ground. The output of comparator 281 is fed back to its negative input,
and provides an output signal 0AAIII'.

The signal (1!AAF provides anonymous filter 18B(7) input.

The signal 70AAF is applied to one electrode of the transistor T81 dated by the signal φ7, the other electrode of which is connected to one terminal of the capacitor c10317) and to one electrode of the transistor T82.

Transistor T82 is gated by signal φ8,
Its other electrodes are grounded. capacitor ClO3
The other terminal of is connected to one electrode of transistor T83 and one electrode of transistor T80. The transistor T80 is gated by the signal φ8, and its other pole (is grounded).
31d: gated by signal φ7, the other electrode of which is connected to one negative input of operational amplifier 2820; The positive input of operational amplifier 282 is grounded and its output is connected to its negative input through capacitor 0104. Its output is also connected to one electrode of the transistor T84, which is dated by the signal φ7, and its other electrode is connected to one terminal of the capacitor ClO3 and to one electrode of the transistor T85. Transistor T85 is dated by signal φ8 and its other electrode is grounded. The other terminal of the capacitor ClO3 is connected to one electrode of the transistor T860 and the transistor T8
connected to one electrode of 7. transistor T86
is gated by signal φ7, and its other electrode is grounded.

Transistor T87 is turned on by signal .phi.8 and its other electrode is connected to the negative terminal of operational amplifier 283t7) and also to the input of anonymous filter 18B which is tapped through capacitor 0109. The positive input of operational amplifier 283 is grounded, and its output is connected to the signal ROV
I will provide a. Its output is connected to its negative input through capacitor 0108 and also to the negative input of operational amplifier 282 through capacitor C107. Operational amplifier 28
The output of 3 is also connected to one electrode of transistor T89, which is dated by signal φ7, and the other electrode is connected to one electrode of transistor T880 and to one electrode of transistor T80 through capacitor 0106. . Transistor T88 is the signal φ8
The other electrode is grounded.

In short, the generation of the signal ROV-N results from filtering by a combination of continuous and sampled low-pass filters. These filters act as anonymous filters that prevent high frequency signals from entering.

ROV IJ No. t8 provides the input for the PSQ receive filter 180. It's a moat, signals LBANDR and LBAN
DR- also provides an input signal. In addition, input signal BLRXB
HR, VLR and VHRrJ: Outputs from NOR gates 316-319 (also U) as shown. Signals VAD and EFAlo provide inputs to NOR gate 316. Signals VAD and EFAlo- Provides input for NOR date 317. Signals VAD- and EF
Alo- provides the input for NOR gate 318. Signals VAD- and EFAlo are NOR game day 1!
IM') provides input. Control signals siA[1-5 and LG,1-5 also provide inputs to the R8K receive filter 180.

Now from FIGS. 27A and 27B, signals 5M0-5
The occurrence of LGl-5 as well as LGl-5 is shown.

Signals SMQ and 6/1 (are the inputs of OR gate 321, whose output provides one O input of NOR gate 322. 100 L OV/6 is the AND date 3
22 other inputs, whose output is AND goo) 32
5f7) Provide one input. NOR Day) 325Q
The other input is the signal DOWNi- from the automatic gain control circuit. The output from NOR'7''-to 325 is the signal MD.
OV/N is 1. It consists of an OR gate 324, an AND date 326, and a NOR date 327, and the signals SM5.6/1, LG5, and A for the OR gate 324.
OR gate as input for l-ID/f-to-326
The output of G324, No. 1g [JPl, and NOR De8
The same circuit with the output of AND gate 326 for gate 327 generates signal M[JPl. Circuit 328-
333 are identical and consist of two (7) two-power AND gates, each with an output providing the input of a NOR gate. Signal M UPl is connected to each circuit 328-33
Provide one input of 3. The output of circuit 328 provides the flip-flip FF 131 OK input and is also inverted to provide the positive input of that flip-flip. The Q output of flip-flop FF 131 provides another input to circuit 329. The Q-output provides another input to circuit 330. The output of circuit 329 provides an input to flip-flip FB' 132. NOR
Date 336 provides the positive input of flip-flop F'F132. One input of NOR gate 336 is provided by the 0 output from circuit 329. The other input is provided by NOR gate 334, which has three inputs. .

One input is the Q-
The output causes another input ↑Flip Flip'
Due to the Q output of FF 132, the 60th human-powered flip
(1) Q-output from flop FF 133, respectively. Flip-flop FF″132
The Q output of provides another input to circuit 328.

It also provides another input for circuit 330.

Circuit 330 provides an input to flip-flop FF' 1330 and is inverted to provide the J input km of that flip-flop. The Q output of flip-flop FF 133 (provides another input to circuit 329).
Provides another input of 8. Signal 5TEP and signal 6/1 provide the inputs of N0R4''-to-337, whose output clocks flip-flops FF131-FF133. Signal 6/1 provides the preset for these six 7-lip clocks. do.

Signal DOWN O, 1: HI S MQ ij: AND
'l''-) 361. Signals SM5 and UP provide AND r-) 3620 inputs. Signal 6/1 provides one input of ORF''-) 363 and its other two The inputs are AND date 361 and 3
This is shared by the output of 62. NoRr-)3
The output of 63 is NOR-connected with the 5TEP signal, and the NO
The R gate 338 is a clip clock FF 134-
Provides a clock signal for FF 136.

The output of the circuit 331 is the J of the flip clock FF134.
It is connected to the input and connected to the input via the inverter. The Q output of the flip-flop 7'FF 134 is connected to the input of the circuit 333, and the 2-output is connected to the first ANDr-) of the circuit 332.

The output from circuit 332 is clip-frog FF135.
is connected to the J input of the It also provides one O input to NOR gate 341!7), the other input of which is provided by N0Rr-) 339. The input of the NOR gate 339 is the clip flop FF 134
Q output from , Q output from flip clock FF135
- output, and the Q output from clip 0 flop FF 136. Clip Freon 7'
Q-output of FF135 is input to circuit 3310 and circuit 3
It is also connected to the 330 input. The output of circuit 333 is connected to the J input of flip 70 tube F'F 136 and is inverted and connected to its input. The clip-flop F1''136[7) Q output is connected to the circuit 3310 input and the Q- output is connected to the circuit 3320 input.

Flip 707' FF131-FF133 and the associated logic circuitry described above form part of a counter that counts up or down in 1 dB increments, depending on the output of the automatic gain control circuit described later. . The output of this counter is NO which makes the output signal SMQ-8M5.
This is realized by R gates 342-347. The input of the NOR date 342 is the clip clock FF131, F
□N0 which is the Q-output of F132 and Fl"133
Rr-to 3430 human power is 7 rip-flop FF 1
The outputs of 31 and FF 132 and FF 133 are the OQ- outputs of 3440 and the Q outputs of clip clocks FF 131 and FF 132 and the Q output of flip-flop FF 1.
3:1) Q-output. The NOR date 3450 input is the Q output of each flip/70-tube FF 131-FF133. The inputs of NOR gate 346 are the Q output from flip-flop FF 131 and the Q output from each of the seven flip-flops F'F132 and FF'133. NOR gate 3470 input is flip front 7'
Q from FF 1.31 and FF 132 and the Q output from flip-flop It'F 133.

Clip Fron 7'' FF134-FF136 and associated logic circuits can be set to
dBf7) form the part of the second counter that counts in increments.

6 The output of the aB counter is the signal LG1-LG5 and L
It is represented by OW6. Signals LG1 and LG
2 are NAND) f-to 352 and 353 respectively
come from. Signal LG3 comes from inverter 354. Signals LG4 and LG5 are each connected to a NOR gate 355.
as well as 356. Signal LOW6 is NOR key.
It comes from 357.

Furthermore, the above 5TEP signal is connected to the NAND gate 376.
The inputs are the signal φUP from AGO and the output of OR'7''-to 375.
The inputs of 75 are the signals UP and DO from the AGO circuit 19.
WN and the output from the inverted NOR7"-to 373. The input of NoRr-) 373 is NOR)f
″-)-339 and 348.

The input of the NORrto 348 is a flip-flop FF.
134 and the Q-output of FF 136 and the Q-output of flip-flop FF I 35.

NAND date 352 is each 7 Ritsuzo clock FF13
4 and an input Q- from F'F136.

NAND gate 9-353 is flip-flop FF13
5 and the Q output from FF 136.

Inverter 354 inverts the Q- to O output of flip 70-tube FF 136. N0R)f+-to 355 has inputs from the Q output of flip-flop FF134 and the Q output of flip-flop FF136.

NoRr-) 356 has inputs from the Q-output of flip-flop FF135 and the Q-output of flip-flop FF136. NO providing output signal LOW6
R) f-to 357 is Flip Flora 7″FF 13
It has an O input from the Q output of 4, FF 135, and FF 136.

This second counter depends on the signal from the AGC circuit 19.
0 counting up and down in 6 dB increments. Therefore, depending on the desired adjustment, the increments of change would be up or down in steps of 1 aB or 6 aB.

FIG. 28 shows the generation of signal 6/1 and signal F8DT. The signal X0RAGO from the AGC circuit is inverted and p
, NDr −) 0AN providing one input of 366
The other input of Dr-to 366 is the inverted signal LG5.
It is. AND) f-to 366 provides one input to cross-coupled NOR date 368, and the output of r-) 36B is signal 6/1, which is the input to NOR date 369. When signal 6/1 is no, the 6dB counters are activated, except for the 1aB counter.

Another input of NOR gate 368 is N0R)f-
This is the output from port 369. Signal SM5 is inverted and N
It is applied as one input to OR gate 367. Signal IIG5 is inverted and applied as another input to NORr-to 367, and finally signal UPi- (from the AGC circuit) is applied as one input. NORke9
- The output of date 367 provides one input for NOR date 369. Another input to the NOR)f''-)369 is provided by the signal BSR8T from the 6 dB increment counter.Finally, the power-up circuitry
Provides 369 4th personnel.

Signal MKEDT- is applied as one input of NOR gate 371, and the output of NOR gate 368, signal 6/1, is applied as the other input. NORr-to3
The output of 71 is the signal EDT.

Figures 29A-29E, when placed together as shown, constitute a schematic of a receive filter.

Telephone lines, which are common transmission lines over which phase-shifted signals are transmitted, have a pair of wires, one for the low band and the other for the high band.

For example, the low band frequency is about 1200 bps,
The high band is about 2400 bps.

When the low band is received, there will be high band pickup. Additionally, telephone lines distort the amplitude and phase of the signal. The purpose of the receive filter is to remove unwanted high-band and low-band interference to compensate for distortion in the telephone line. At the transmitting end, it is desirable to use an equalization circuit to minimize distortion. At this receiving end, distortion is further minimized by a receiving filter.

The receive filter of FIGS. 29A-29E consists of seven sections, each section being a fourth order filter similar to the fourth order filter described above. The difference between each fourth-order filter lies in its transfer function. In addition, in each of these filter parts, the modem
It may be appreciated that capacitors may be switched in and out of the circuit to adjust the frequency response of the protocol and the gain determined by the AGO controller 19.

First, from FIG. 29A, signals BHR and VHR are NoR.
r−)3890 input, but the composite signal LB
ANDR is used through this filter. A certain switch 5w4Q, which is the same as the switch in FIG.
The NDR isolates the filter as desired, as controlled by the NDR. Signal ROVIN is switched into the circuit by switch 40. The first part passes through switches 42 and 43 to operational amplifier 3860 and capacitor A117-,
Selectively introduce a119. Switches 5W45 and 5 activated by signals VLR and BLR respectively
The introduction of capacitors C125 and 0126 by w47 to the input of operational amplifier 387 changes the capacitance depending on the protocol.

The output signal from operational amplifier 387 is vol which passes through transistor switch T111 to the second portion of the filter comprised by operational amplifiers 388 and 390 and associated circuitry. Capacitor switch network 370
has the following four capacitor switch circuits connected in parallel.

That is, the switch 5w53 is activated by the signal VHR.
and capacitor C111, switch 5w54 and capacitor C112 operated by signal BHH, switch 5w55 and capacitor C113 operated by signal VLR, and switch 5w56 and capacitor C114 operated by signal BLR. This circuitry is used, by way of example, to further illustrate the filter and, depending on the protocol, provides a variable capacitance input to operational amplifier 388. Signal VHRXBHR, LB
ANDR is switch 5w4B, 5w4g, 5w respectively
Capacitor C133, C134, C135 by 5Q
Switch in. Capacitor C! 141-014
3 are switched to switches 5w57.5w58.5w59 by signals LBANRD-1VLR, , BLR, respectively. These capacitor punctures are
An additional, selectable capacitance is provided to operational amplifier 390 with output signal vo2.

The signal vo2 is the sixth filter of the filter as shown in FIG. 29D.
switched in to the part. Signal VO2 enters transistor T115, but the same capacitor switch arrangement as capacitor switch circuit 395 of FIG. 29A is placed across operational amplifiers 391 and 3920 of the 4th order filter 02 of this sixth section. Another capacitor switch network 398 placed between amplifiers 391 and 392 is similar to capacitor switch network 395 except for the value of the capacitance. Finally, yet another similar capacitor switch network 397 provides a capacitance to be added to the fixed capacitance at the input of operational amplifier 391. operational amplifier 392
The 0 output from is the signal vo3 which is introduced into the fourth part of this filter as shown.

Signal 03 is switched into the fourth part through transistor T116. This section has a capacitor switch network 377 similar to capacitor switch network 370 connected to the input of operational amplifier 394, except for the capacitor values.

Another such network 376 is operational amplifier 39
3 is connected to the output of a differential amplifier 394. Yet another similar network 375 is connected to operational amplifier 3.
The output of 93 and the operational amplifier ρ3940 are connected to the tune of human power. The additional capacitance to the operational amplifier 393 input is switched in by signals BHR, VHR, VLR, and BLR in a network similar to that previously described for network 370. The output of this fourth part is number vo4, which is shown in Figure 29E as being in the fifth part.

The signal vo4 enters the transistor T117, and the arithmetic increase 1
It is shown providing one input to a section made from M-units 401 and 402 and associated switches and capacitors as shown. Operational amplifier 4020
Capacitor switch network 3 connected to input
The 82 is similar to the 370 except for the capacitor values. Similarly,
Capacitor switch network 3 similar to network 370
83 is from the input of the operational amplifier 401 to the operational amplifier 402.
is connected to the output of Operational amplifiers 401 and 402
Another similar circuitry 385 is connected between. Finally, similar circuitry 384 connects operational amplifier 401
Connected to 0 input. The output from operational amplifier 402 is signal Vo5, which is shown entering the sixth stage of the filter in Figure 29B.

Signal vo5 enters the sixth stage through transistor T118, which is comprised of operational amplifiers 403 and 404 and associated switched capacitors.

In this section, the capacitors are switched in and out of the circuit in a capacitor switch network similar to that described above, but the switches are switched in as shown in FIG.
It should be noted that it is activated by the signal SMQ-8M5 from the aB step counter. The capacitor switch network has six capacitors that are switched in and out by switches each activated by signals 19MO-8M5. This network serves as an input to one operational amplifier 40:11'). Capacitor switch network 381 connected to the SO input
is also similar to capacitor switch network 370. Capacitor switch network 380 connected across operational amplifier 4030 is similar to network 370. Similar circuitry is connected between operational amplifiers 403 and 404.

Switch capacitor network 378 is operational amplifier 804
T:r) Connected to both ends. Signal B similar to network 406
Switch controlled by MQ-SM5
A capacitor network 407 is connected to the input of operational amplifier 404. Operational amplifier 404f7) output is signal V
It is O6. It can be seen that this filter O response does not only depend on the Zolot call, but also on the automatic gain control circuit 19 which controls the counter providing the signals 5M0-8M5.

FIG. 290 shows the seventh and final portion of this receive filter, where signal vo5 is connected to capacitor switch network 41.
It is introduced into the fill via 0.

Network 410 provides signal L to the input of operational amplifier 408.
5 switched in by G1-LG5 respectively
Consists of several capacitors. A similar network 411 is connected between the network 4100 input and the output of operational amplifier 409. A switch capacitor network 373 similar to network 370 is connected across operational amplifiers 408.

Circuitry 374 similar to circuitry 370 connects operational amplifier 408
and 409. Similarly, the circuit network 370
A capacitor-switch network 3 2 similar to 37 is a circuit network 37.
Selectively apply a force to the capacitance of 3 [1 less. Circuit network 3
A network 371 similar to 70 is connected to one side of each network 373 and 372 via a transistor switch. The gain of this 0 part is the gain of AG in addition to other gain components.
From the counter controlled by OM path 19V, signals I,
Controlled by G1-TJG5. Output I δ FRO
V is now filtered and ready for phase shifting.

Figure 0, in block diagram form, depicts automatic gain control and related circuitry. ROV filter 18A, 1dB step'
18B and 6dB step 18C represent the above-mentioned (7) 7-step reception filter; in this case, reception filter 1
8A represents the first 5 parts, 1 aB step 18B
represents the 6th part, 6dB Sten 7'18 clrJ
- represents the seventh part. The 1 dB step and 6 dB step provide logic 19E1 or signals 5M0-8M5 and LGi-LG5 in FIGS. 27A and 27.
It is controlled by the logic shown in Figure B. Counting circuit 19D represents a counter for 1 aB and 6 dB increments, which is also detailed with respect to FIGS. 27A and 27B.

The rest of the automatic gain control device to be explained is the rectifier 19A1.
They are a filter 19B and a comparator 19C. In this preferred embodiment, rectifier 190 is a negative rectifier;
If the incoming signal exceeds the voltage reference level, it is inverted. If the incoming signal is below the reference level, it will not be inverted. The rectified signal Q is filtered,
A comparison is then made to determine whether the signal is too high or too low. Depending on the decision, the UP or '[)OWN signal is
Generated for the counter in Figure 7B.

31A, comparator 405 and operational amplifier 406,
and a rectifier circuit constituted by related circuits as shown. In fact, the capacitor and transistor switches shown along with operational amplifier 406 provide a first order filter function such that the output signal RECTD from operational amplifier 406 is rectified and slightly filtered. From there, it , a 31st circuit consisting of operational amplifiers 407 and 408, which together with the 0 support circuit shown constitute a quartic section.
Proceed to section 19B shown in Figure A. The output from the operational amplifier 408 is the signal FIL.

A comparator circuit 19C for comparing the input signals with the signal and producing adjustments to these signals (7) is shown in FIGS. 31A, 31B,
and shown in FIG. 310. Figure 61A is NOR
The clock φ4 is shown as one input of the date 423. The other input is signal 6/1. NOR'f”-to42
2 is added with 6/1- and the Q output from the flip clock FF143.

The outputs of NOR gates 422 and 423 are added to the NOR date 424 inputs. This logic arrangement consists of 4 clocks, 7 rip clocks, FF 143
is used to clock flip clock FF144, which in turn clocks flip-flop FF145. Figure 28 shows the generation of a signal 6/1 which is turned on by a long carrier detection (if signal) to speed up automatic gain control. In either case, the Q output of the flip 70-tube FF 145 is a NOR '7''-t426.7) Provide one υ input,
The Q-output of that flip clock is NOR date 42
7, while the other input for both of these dates is provided by the Q- of flip clock FF 144. The outputs from NOR gates 426 and 427 provide a latch circuit 4280 that provides output signals φDOWN and φσP. Its output also provides the latch circuit 429 D input, but its output signal is φ
DOWNA and φσPA.

The signal B and F circuit shown in FIG.
r-) to the negative input of transistor T124
is dated to the positive terminal of comparator 409 by signal φ[7PA passing through. Coupled to the negative input of the switched comparator 409 is a signal 5M01 or N
The output of the ORr gate 431 causes the transistor T121 to
There is a signal LOW 6 that is dated. Signal φUPA
- is added to both NOR dates 431 and 432. Signal 6/1. ↓ is applied to NOR gate 432, and signal 6/1 is applied to hoRr-) 431.

The same circuit is connected to the positive terminal of comparator 4098'), except that signal φDOWNA- is substituted for φ[JPA-. Also, the applied signal is 8M5 or LG5
It is. Next, these two circuits determine the output of comparator 409 which is directly connected to latch circuit 411.
The other input of 9 is φDOV! N, and the other inputs are φ[J
It is inverted for latch circuit 412 which is P. Signal U
Depending on the state of these latches, PI or UPI- is output from the latch circuit 412 by the signal DOWN.
1 or i DOWNl- is high from circuit 411. AND circuits 413 and 414 and NOR circuit 45 (
1':> AND OR/7"-to combination is NAND
provides the signal X0RAGOOUT, which is an input to r-t 416. The 5TEP- signal (FIG. 27B, the inverse of the 5TEP signal) clocks a flip-flop FF1.50 with a Q output that provides a zero output for NAND date 416. The output of NAND date 416 is 4 υ toggle flip 70 knobs I'F' 146- F)' 1
NOR7+ provides 49 preset inputs and
-G418 No.1 pQ input card is provided. Flip
Flop FF 146-F:E' 149 counts and determines whether the change in tJ is long enough to make a change.

The outputs of these O flip-flops are applied to 140R gates 417 and 419.

NOR gate 417 is flip-7o7uFF
15 Preset Q, NOR'7''-to 419 is N
Provides another input for OR date 418. NOR
) f"-) 418 is the input signal φ[TPA, the output of which clocks flip-flop FF146, which in turn clocks flip-flop FF 147, and so on. N0RF"- The output from the NAND gate 419 also provides an input to the NAND gate 420 and an input to the NAND gate 421Q1.
420, the output of which is the signal UP-. Signal MDOWN 1 (from Figure 27A) is NA
ND game) 421 (7) (7) provides an input, and its output is the signal DOWN-.

The AGOl path (provides a signal that increases or decreases the amplitude of the incoming signal if a sufficiently long period is involved and the magnitude is found to be too large. The signal created above is passed to the receive filter 18. Used in circuits that produce actual amplitude changes.

FIG. 32 is a block diagram of a digital pressure controlled oscillator used in the data recovery loop of the receiver. The illustrated divider has an input of 4 Mllz. Zolotokor is also an input. At the end of the count signal RP5, the divider 4
variable divider 4 providing a reset signal VOLSR to 50;
Sent to 70. Variable divider 4700 output provides one or two inputs (fixed divider 5009), but divider 500
The output of is a mixed clock for cosine and sine functions.

Fixed divider 500 also provides clock signals φ52, φ54 and φ58 to count control circuit 520. A/D converter 480 has a loop error voltage FVIN input and provides a 6-bit output to count control circuit 520. Count control circuit 520 signals variable divider 470 in response to a 6-bit input V from A/D converter 480 to provide E and F i7.

In order to complete the istonization of the incoming signal, it must be divided into two phases, and the phase shift circuit will now be described. Control signals utilized in the phase shift circuit and not identified by kneading size are illustrated in FIGS. 66-35.

Figure 33 shows six clip-flops FF151-FF.
153, flip flop 7'F'F 151 is clocked by phase φ5 and the Q output of the clip flop which clocks the subsequent flip clock. AND gate 430 is clip flop FF 1
51 to QQ, output and inverted signal LBANDR
receive. ANDNO dates 4 and 431 are NOR
Date 432Q provides two inputs, but NOR Date 432i') output signal is 0K125.

In FIG. 34, signal OK 125 is the input signal of the circuit shown in FIG. From 7 lip flops 154! 7) The Q output provides the D clock for clip flop FF 155 and connects to the J input of clip flop FF 157. The Q output from flip-flop F'F' 155 provides the J input of clip clock FF 156, and the Q output from clip-flop Fl" 155
The output provides input to flip-flop FF 1570. The J and Q inputs of clip clock FF 157 are provided by the . and Q outputs of flip-flop FF'' 154, respectively.
I will provide a. Inverted slip 70 tube FF156
The υQ-output provides control signal w128. Inverted clip clock FFI 57oQ output is signal OGR
I will provide a. The inverted signal CGR provides the signal BGR.

Figure 65 shows the timing signal n used in the phase shift network.
Indicates occurrence. AND-NOR circuits 434-437 are N
2 2-person AND) f that provides the input for the OR gate
The signal w128 is generated from the circuit 434.
)) one, Q AND 8-digit input and one of circuit 435! 7) Provide AND date entry method. signal w12
8- provides one input of circuit 434 and one input of circuit 435. Signal w127 provides one input to circuit 4360 and one input to circuit 437. signal w
127- provides one input to each circuit 436 and 4370. Signal φ5- provides power for each circuit 434-431. Similarly, the signal φ6- is applied to each circuit 434-4.
37 inputs. The outputs from circuits 434-437 are clock signals φ5S%φ68, respectively.
They are φ5c and φ6c.

Figure 36A shows a pseudorandom shift register (divider) 45o that provides a fixed count for the digital voltage controlled oscillator of the receiver circuit. A clock generation circuit 449, which is the same as the clock generation circuit 33, generates eight flip clocks forming a shift register and a signal VC! Ls
Provide clocks 1 and 2 that clock the ninth flip-flop which resets the eight clip 0 flops when R is received. Signals VAD and VA, D-
1 and LBANDR and LBANDR- provide control for the PLA. Output signals from PLA are 5P5A, 5P5B, RP5A, RP5
B, 5P5A, 5P5B.

and the remaining four lines of PLA combined and inverted through NOR date 451 provide signal RPB.

Figure 36B shows the digital voltage controlled oscillator clock signal φ
5 and φ6 are shown. Input signal 5P5A and 5
P5Bil'':j: is the input of OR gate 452,
Input signals RP5A and RP5B are OR gate 457
is the input. The O output from these two OR dates is
All provide inputs to each AND gate 453 and 456 clocked by the D signal VCLKi from pseudorandom shift register 450. AND ) gates 453 and 456 (f7) outputs provide inputs for cross-coupled Q NOR dates 454 and 455, respectively, while the output of NOR gate 455 is inverted to provide signal φ5.
I will provide a.

Signal φ6 is generated in substantially the same manner as shown in FIG.

Signal RP6 provides one input directly to AND r + - gate 463 . Signals 5P5A and 5P6B provide inputs to OR gate 461 which provides inputs to AND gate 462. AND) f″′-t462 and 463
Both receive their second human power from signal VOLK1.

AND)! NO cross-coupled with NOR gate 459 with inputs coming from ports 462 and 463
The R data) 4580 output provides clock signal φ6. Clock signal φ5 is an input in FIG. 62 that produces various other clock signals.

Figure 360 shows the signal V as ANDN-D1464
CLK1 and R'P5 are shown. A word Q168 from flip-flop FF168 in FIG. 66A is AN
N0Ft gate 466 cross-coupled with NOR gate 467 with input provided by D gate 464
provides one input for the The output of N0R) f-to 466 is inverted to trapezoid signal PSETX.

Flip-flops FF187 and FF1 are shown in FIG. 36D.
88 and FIT' 189. The 4MHz input of the clock generation circuit 465, which is the same as the clock generation circuit 33, is
Output clocks 1 and 2 are provided to clock flip-flops FF 187-FF 189. Exclusive O
R circuit 468 is) 1 nop flop juice 18 ends '7J
D input 9 (to do this, flip-flip FF
188 and FF 189's Q and Q-outputs.

Flip-flops FF 187, FF 188, and FB"181') Q, outputs of each exclusive OR
Circuit 4720 provides one input. Each exclusive OR circuit 472-474 is provided by a signal D-lE- and -F, respectively. The generation of these signals is as follows. The output of each of these exclusive OR circuits 472-474 provides a NOR date 476f7) input, with one additional input being the signal PSETX from FIG. 360. N
The output of OR'7''-to 476 is sent to shift register 45.
It is applied to the D input of the zero flip-flop 'FF 168 to preset the eight flip-flops that make up its shift register.

FIG. 37A shows the signals φE1φF1 and φF− used in the analog-to-digital converter used in this receiving circuit.
Indicates the occurrence of Signals APSET and φ2■ provide flip-flop FF190 and NOR date 4670 inputs. The output of NOR gate 467 is inverted to clock flip-flop FF190, which outputs an OQ ratio of NAND 4771Q 1 '').
Input k Provide f Ruo NAND 'f”-447
The other input of 7 is the signal φ5. NAND gate 9-47
The output from γ provides one input to the NOR gate 478, which is inverted to provide one input to the NOR gate 478. NOR gates 478 and 479,
Output signal φE(il-provider NOR7''-to 478
and cross-coupled with a 140R gate 479 that provides the output signal φF and the inverted φF−.
5, FF 176 and FF177 are shown, where flip-flop 7'FF177 is clocked by the signal QF-, flip-flop FF176 is clocked by the Q output of flip-flop F'F175, and flip-flop FF177 is clocked by the Q output of flip-flop F'F175. Flop FF
Toggled by the Q output from 176. The Q and Q-outputs from Flip-Flip 1"Fl 75-I'F177 are NoRr-)481-488 such that NOR-Flip1"Fl 75-I'F177 represents the count of a combination of six 7-lip-flops. The NOR gates 481-486 av outputs are combined in the steam signal AD6 and the inverted AD5- to AD, respectively.
I and inverted ADl-. NOR gate 4
The 87 to 0IJXl force is inverted and the signal L'r CH
- provide. The output of NOR DE"-) 488 is inverted to provide signal PSET-.

FIG. 370 shows a 6-bit binary representation representing the presence of an analog voltage.
8-FF 183'e shown. These flip-flops are clocked by the outputs from NOR gates 501-506, each of which is clocked by the signal φ
provided by F1 and AD6- to ADi-. The Q output of flip-flop FF l 7 f3 is inverted to provide signal AB6, and the Q- output is inverted to provide signal AB6-. flip clock FF 17
9- Q-output of FB' 183 is each signal AD5
, AD4, AD3, AD2 and ADl to provide signals AO5- to AOl-. All of these O signals are inverted to provide signals AO5-AO1.

Signals AB6 and DAO[JT (from FIG. 37D) are exclusive-ORed in circuit 498 to provide inputs to flip-flops I"F'17B-FF1830, respectively, and are inverted to
Provides QJ input.

Signals PS ET- and φF are the inputs of NOR gate 496, the output signal of which provides input to the circuit of FIG.
-AT'SE also provides preset input for FF182
It is T.

Signal LAT OH- and signal φF are connected to NOR gate 49
7 inputs, but their outputs are each output newsletter S.
and S-11v14 and M4-1M3 and M 3-1M2 and M
2-1M1 and lA1-Latch circuit providing 1M0 and MO- 490.491.492.493.494.495
Provides 0 manpower. When flip-flop FF178 is set, S=1 and 5-=O, and so on. These 0 output signals are soft and represent the contents of the flip clock described above.

FIG. 37D shows a capacitive divider network used in the centrifugal approximation of the digital value of the human input signal.

As shown, the high signal VADH, which in the preferred embodiment is about +1 volt, and the signal VADL, which is about -1 volt, provide voltage reference inputs.

Capacitor C160, KO160, K2O160, K2
O160, K40160 are signals AC1, Ac1, AC3, respectively from the OK bit counter circuit in FIG. 37B.
Selected by Ac1 and Ac5. Another bank of equal sized capacitors id is activated by the inversion of the signals described above. In one case the voltage should be applied and in the other case the voltage should be subtracted. The constant is equal to 2, so if 0160=1, then K'0
160 = 16.

Since the capacitors are connected in parallel, they are added together, so the input voltages are J/31, '/31,
”/31 increments, etc. Voltage FVIN
, that is, the comparison with the voltage at which A/D conversion is performed is the third
This is done by a comparator 515 with an output signal DAO[JT used to divide the exclusive-OR circuit 498 of FIG. Therefore, the flip-flop Fl"178-PFlB3 of 61 is counted until the comparison is made. Then, at the count of 7 from FIG. 37B, the contents of the flip-flop 490 -4
Kate was kicked out in 1995. At the eighth count, the flip'' flop is preset.

FIGS. 38A and 38B are combined to form circuit 5
20 shows the occurrence of signal R1, E-1 and F-Cr'). Figure 38A shows the signals λ42, SXMi, s, MO
and 81 and exclusive OR gate 516.517.51
8 shows their inversions combined respectively. The output from circuit 516 provides one input to NOR gate 526, the other input of which is provided by No. 15 φ58. The output of the inverted circuit 516 is NORf
'''- provides one input of circuit 519, while its other input is provided by signal φ52-.Circuit 5179
) output provides one input to NOR data ) 521f7J, the other input of which is provided by the output from NOR gate 519 and signal φ54. The output of inverted circuit 51 provides one input to NOR key 524, while the other input is provided by signal φ54-. The output of circuit 518 provides one O input of NOR gate 522, the other O input being provided by the outputs of NOR gates 519 and 524, and signal φ52. The 0 output from NOR gates 526, 521 and 522 is a NOR with signal L/S as an output.
Date 523 provides three inputs.

In FIG. 38B, signal L/S is seen as one input to PLA 525, either directly or inverted. Signals S and S
-1M3 and M3-1M4 and M4- are all PLA 52
5'7) Input signal. The output signals from PLA 525 are signals D-1E- and F-, which are the r-) signals for exclusive-OR circuits 472-414 in FIG. 36D.

Figures 39A and 39B, shown in combination, are schematic diagrams of the phase shifting, mixing, summing, and general filter circuits (7) that provide the output base Teisignal CO and IC9. Signal FRC■, the output of operational amplifier 409 shown in Figure 29C, provides the input for these circuits. The positive terminal of the operational amplifier 442 is grounded, and its negative terminal receives zero power from the various combined capacitances that are based on the selected global call and form a full range filter that does not affect the magnitude of the signal, but only the phase. Therefore, zero phase shift is the output from operational amplifier 442. On the other hand, operational amplifier 4430 is arranged to shift the phase by 900 degrees at its output. The output of operational amplifier 442 is sent to buffer filter 44.
6 and its output is the signal PSO. The output of operational amplifier 443 is the input of buffer filter 447, the output of which is signal PS9. Signals p SQ and psg enter an identical mixing circuit except that gate signals are added with conditions of 00 and 9D0. For example, the 39th A
In the figure, signal PSO passes through transistor T140 and is gated by signal φ6avc. Signal SP9
is passed through transistor T133 by signal φ6S. In FIG. 69, the signal Ps.

is caused by signal φ6S, and signal P89 is caused by φ5c.
- It has been written. If you examine these circuits, you will find that they are the same except for the gate signal 0 phase. Third
The mixing circuit shown in Figure 9A consists of capacitor 0152-0
154, and c156 and c157Vc charges are stored.

Transistor T132, when gated by signal φ6, transfers charge from these capacitors to capacitor c1.
55, whereby the signals are summed. The operational amplifier 444 and associated capacitors are connected to the output signal
That is, it provides a first order filter that creates an in-phase channel signal. Similarly, operational amplifier 445 provides an output Ig 109, a 1-boh angle phase Q channel signal.

FIG. 40 is a schematic diagram of a buffer filter 446 (same as buffer filter 447). Operational amplifier 442
The output of φ to avoid any beats in frequency
Capacitor C150 is passed through T130 by a signal φ7 which is now four times the frequency of φ3 and φ4.
provides an input to a buffer filter 446 that passes through. Operational amplifier 440 and its associated capacitors and switches provide a switched low pass filter. Operational amplifier 441 and its associated circuitry, including resistor R5, provide a continuous filter with output signal PSO.PSO provides all inputs to the mixing circuit described above.

FIG. 42A shows the generation of clock signals φC and φD(7). Clock generation circuit 531, which is the same as clock generation circuit 33, receives a 4 MHz input and provides clock 1 and clock 2 outputs that clock flip clock uFF 191, while its Q and Q-outputs clock flip clock FF 192. used to clock the The Q output of flip-flop 7' FF 192 clocks the toggle 7-retro flop Fl'' 193. The Q output of the inverted flip-flop FF 193 is the signal φC and the inverted Q-output is φD. .

Figure 42B shows the generation of clock signals P68 and P58. As shown, signal φ58 is cross-coupled 1yoRr
-) D provides one input directly, and the other is inverted,
Provides one input for the other cross-coupled NOR dates, but
1(oR/7″+−thorn) provide output signals P68 and P58, respectively.

The clock pulses used to transmit data to the receiver must be recovered to ensure accurate timing of the incoming data.

As in the transmission process, the data needs to be clocked as close to the center as possible. A clock recovery loop is required to extract from the incoming data the clock used for the original data transmission.

Below is a detailed circuit description of the clock recovery loop.

1. From FIG. 41, the generation of signals φ5, φ6, φ5Q and φ6Q is shown. Signal engineer R and signal DB
R passes through transistor T135 and is inverted and applied through transistor T137 as signal φ5-f: gate exclusive ○Rr-) 53 (I') input. The exclusive OR circuit 530 passes through transistor T136, is inverted by 1, and passes through transistor T138 to output the phase φ
Also gate 6-. Transistors T135 and T138
The 0 connection between 0 and 0 is inverted to provide signal φ5■. The connection between transistors T136 and T137 is inverted to provide signal φ6. Signals QR and DBR are combined in exactly the same manner as described for signals IR and DBH to provide signals φ5Q and φ6Q as shown. Signals IR and QR are shown with equalization circuitry to be described, and signal DBR is the output of clock recovery loop circuit 0, described below.

Figures 42A and 42B are simple circuits illustrating the generation of other control signals used in the clock recovery loop to be described.

Figures 43A and 43B are combined as shown to provide a schematic diagram of a clock recovery loop that recovers all of the clock signals used during transmission from the transmitted data. As mentioned above, accurate recovery of clock 0 is essential for good data discrimination.

From Figure 39A and Figure 39B, D base band signal engineer C
O and □IC9 are received by a low pass filter VC consisting of operational amplifier 541 and its associated circuitry. The signal ■co is the signal φ5 for charging the capacitor 0158.
Switched by engineer.

Signal φ6 is routed from the capacitor of the transistor switch to ground. In the same way, signal engineer 09ii
It is dated in through a transistor switch by a signal φ5Q that charges capacitor c154. Signal φ6Q turns on a transistor switch connected to capacitor C157 and ground. Each capacitor c1
57 and 0158! l') The other terminals are both connected to one terminal of V, capacitor C1597,), at which point the low-pass filter is common to both CO and IC9. Signal φ5 gates a transistor switch between the single terminal of capacitor 015987 and the negative input of operational amplifier 541. The signal φ6 is the 1 of the capacitor 0159.
Gate switch from two terminals to ground. The first low-pass filter O output of the arithmetic unit 11 width unit 541 is (No. BUM
This is Engineering N. The signal S[JMIN involves 2 υ parallel paths, one through the integrator circuit and the other through the integrator circuit O side path.

The latter path is in particular passed through the transistor switch to ground by the signal φC at one terminal of the capacitor 0167, and from that one terminal by the signal φD through the transistor switch.

Signal S (JM IJ) is dated into the integrator circuit by signal P58 which charges capacitor 0161. Both sides of capacitor 0161 are selectively grounded by signal 'P68. Switch in. The output of this integrator is the output of operational amplifier 542υ. When signal EDT is high, indicating that no energy is detected, it gates the transistors across operational amplifier 5427. and make it unusable. The signal F LOT is the capacitor 0167 mentioned above which adds the two signals and provides the signal S[JMOT.
K [to charge the connected capacitor 0165, f
It is switched by the g number φC.

The contribution circuit is relatively slow with respect to the total phase clock roof 0 that the transmitted clock recovers.

If the output of operational amplifier 542 becomes railed, ie, if the output is equal to any one of its outputs, the phase-locked loop will not operate. In the circuit explained in this section, the 0 output section S from the operational amplifier 541
By providing UM_N and summing it with the output signal F_LOT, the low pass filter ignores the integrator output even when the integrator is off. In the preferred embodiment, an analog divider that divides the output by 5 is provided at the output VC of operational amplifier 542, so that the output of the low pass filter can ignore the output of the integrator. In this case, the phase-locked loop should lock. The integrator circuit then freely adjusts itself at a relatively low speed to reduce the D of the low-pass filter.
The C output is reduced to 01, allowing the loop to run freely without losing lock in the absence of an input signal. The divide-by-quintuple circuit is the first order filter that receives the operational amplifier 5420 output and includes operational amplifier 543 and associated circuitry. The capacitors are selected to divide the gain of the first order filter to be 115.

A voltage reference VCRL 2 (in the preferred embodiment minus 1 pol Q for the system reference) is applied to the transistor switch as shown through gates φC and φD and along with capacitor C170; Operational amplifiers 544 and 545 as well as input signal S [JMOT]
, comparator 546, flip-flop f FF 195 and associated capacitors and transistor switches as shown.

The voltage controlled oscillator (VCO) of this invention is a collection integrator VC.
0, i.e. oscillation 0. On any given cycle, half of the circuit integrates towards the limit voltage, while the other half lets its integrating capacitor completely idle, waiting for the next cycle. do. This is flip flop 0
FF195, that is, the clock input is connected to the comparator 54.
Toggle flip 0 received from output signal CL 15 of 6
-Achieved by flop. Flip Flotso F'
F1950q output is connected to transistors T144 and T14
Connected to 1Q date. Flip 0/Flop F
'FI 95'7vQ=Output is connected to transistors T145 and T1400. Transistor T141 is connected across operational amplifier 545 and its feedback capacitor 0167. Transistor T14
0 is the operational amplifier 544 and its feedback capacitor 016
Connected to both ends of 6Q. Therefore, if flip-flop FF195 is set and Q is high, then
Transistor T144 is turned on and transistor T141 is also turned on. Transistor T141? By turning on, operational amplifier 545 is removed from the circuit. Therefore, operational amplifier 544 and its associated components provide VCO 2. The output of operational amplifier 544 passes through transistor T144 to the positive input of comparator 546. The negative input of comparator 546 is the voltage reference VORL_3 (which in the preferred embodiment is minus 6 volts). Operational amplifier 544
The output of will slope downward and when it reaches 25 volts,
The output of the comparator toggles seven lip-flop FF195 so that Q goes high, in which case transistor T14
5 is turned on like transistor T140. When transistor T140 is dated on, operational amplifier 544 is removed from the circuit. Arithmetic amplifier lRa 545 enters the circuit and its output is connected to transistor T145.
It is connected to a comparator 546 via the . The operation is repeated as described above.

This dual integrator CO provides extremely fast VCO operation, which would otherwise be limited by the speed of the operational amplifier. By immediately starting the ramps of other operational amplifiers,
The f-times delays are eliminated, resulting in extremely high speed OVOO.

Illustrated tD You fx AND NoRr-to 547.5
48 and 549 are output signals CK1 and CN3.
Provides 8XCK2- and 16X0K2. Signal HLF
SPD and signal HLFSPD- are connected to each circuit 547-54.
9 inputs. Signal C! from comparator 546! L16 is inverted and added to gate 549.

Clip 0 flop FF1950Q output clocks toggle flip flop Fi96, which provides signal CL 8 on the SotsuQ output and flip flop Fi96.
Clock flop F'F197'. Clip flop FF 197 provides signal OL4 at its Q output and clocks clip clocks I'F 19 B and F'F 200. Flip Flop Fp
198U provides an OQ ratio output OL2 and clocks flip-flop FF 199. The Q output of clip flop F195 provides circuit 5480 power. Flip-flop FF196(7)Q output provides circuit 4580 power. Flip 70 Tsubu F
ioQ output and flip clock FF from F198
The 200 karariQ-output provides the circuit 5470 input as shown. Q of clip flop 1”F 200
The output is the signal DBR which is inverted to become the signal OL-. These 0 signals are used in the equalization circuit to be described, as shown in the figure.

Figures 44A-44N are simple logic circuits illustrating the timing and generation of the categorizing signals used in the equal f-hi circuit to be described. Figure 44A shows clip 0
- Clock FF 201 QK large input is connected, and the equalization signal EQ is inverted and connected to its J input. OQ ratio output and Q from clip clock FF201
-The output is connected to the input of the flip-flop 1'F 202 OJ and! and provide signals CIE and 0IE-, respectively. Clip 0 flop 202'1
') Q output is flip 70 tube F'F203.7) J
Input VC is connected to provide signal c2g4. Flip
Flop FF2037)Q output provides signal 03K.

Signal QEQ is connected to the clip-flop FF204ox input, inverted and connected to its J input. Flip Flop FF 204! 7) Q and Q-
The output is a flip-flop FF205.

J and are connected to the inputs of the signals 5100 and 5100, respectively.
and 5100-. flip flop FF
20517) Q output 1rJ-Flip flop FF
206oJ input to provide signal 5200. Flip-flop FF2 (1617) Q output provides signal 5300.

Figure 44B shows signals φE and φIE-1, φ2E and φ
'I E -V) indicates occurrence. Input 1st gear CL16 and 0
L16- are 1qOR/7'''-to566 and 5, respectively.
67. The outputs of each NOR gate 566 and 567 are inverted four times and cross-coupled together.

After four times of inversion, the signals φIE and φ2E are each NO.
Provided by R gates 566 and 567.

In FIG. 440, 1. IORkey-1-561-5
64 have six inputs, all combined CL2, CL4, CL8 and their 0 inverses, providing output signals S21.822.823, S24, respectively. moreover,
Signal T4 is provided by inverted signal 824.

4-person power NOR Dart 567 has inputs 0L-1OL2, CL
4, with cLB, output signal T5 and inverted T5
- provide.

FIG. 44D shows IS as input to booRr-to 568
No. CL2- and OL are shown, but this υ-frame is connected to the output T.
6 and inverted T6-, the C signals 0L2- and CL- are connected to the NOR gate 56 with the output signal T7.
Provides 9 inputs.

N0R))""-T5F1 signal OL, 0L2-1C! L
4-1CL8-1OL16- is received. Its input is signal φ12, which provides an input to NOR gate 572f7) and is inverted to NOR gate 572f7).
NORr_t 573'7) cross-coupled to 72. The O output from these υNOR gates is signal 8.
12- and S12.

ROR gate 574 receives input signals 0L-1CL2, CL
4, CL8-' (11-receives and provides output signal 829 and is inverted to provide signal T8; NOR key-
Port 575 has input signals OL, φ2E and T4 and provides an output signal S1.

FIG. 44E shows a NAND NOR gate circuit 576, in which input signals 0, Q2F, and Q2 are arranged as shown to provide one input to the NOR gate 577 and its date The other input is T5- and its output signal is Sl.

NOR gate 578 receives signals T4-1Q, E-1 and OL- and provides an output signal S9. It also provides input for NoRpf-) 59001. NOR r-t5γ9 receives signals C, E-1, Q-E- and T5-. Kate 579 is NOR day)
59(I') provides one input. NOR gate 5
80 receives signals CJEXQ2E-1 and T5-, and also provides an NOR input. NO
The R gate 5900 output is inverted to provide signal S3.

NOR gate 581 receives signals T5 and T6;
The output is NOR data 5820 one input and N
oRr-)5830 Provides one input.

The other input of NOR gate 583 is φ1E-, and the other input of NOR gate 583 is φ2E-.

The output of the NOR gate 582 is number S4, and N0
The output of Rr-to 583 is No. 1H S5. N0Rr-
Port 584 receives signals OL and OL2 and provides output signal S6.

In Fig. 44F, there is an AND NOR circuit 585.
receives the signal 5100.5100-1Q2EX
1 input, but the other input of the keyboard is 1-
Provided by No. T5-. NO, R date 586
One output is fza number S8.

NOR gate 587 is an input signal! 9100-1φ1K
-1T5- received, N0R4+- 589 D
Provide input. NOR gate 588 is input 1g No. 5
100, φ2E-1T5- is received and the output is NO
R/7' provides another input. Signal S9 also provides power for one of the NOR gates 589, and the output of the r gate is the inverted signal S9.

NOR gate 591 provides input signal T7B- and output signal S17 to input signal T7B- and φ.

NOR gate 592 connects signals r78- and φ2-
1 and provides an output signal S12. NOR gate 593 receives input signals T8- and φ1E-;
Provides an output signal φ1v.

NOR date 594 receives input signals T8- and φ2E- and provides output signal φE-.

FIG. 44 shows the generation of other signals used in the color matching circuit. NOR date 595 receives input signals TI and 829 and provides output signal T78-, which also
It also provides input for OR Ketoro 01-604. A
ND OR'l''-ts 596-599 receive signals as shown!7), ie, circuits 596 and 59γ receive the combination of signals X, QIF and Q, 2B.

Circuits 598 and 599 receive signals Y, Q1F and Q,
:Receive the lQ combination. The output from circuit 596 is for each N
One input for OR dates 601 and 602 is provided.

NOR date 5977') output is each NOR date 602
and 60! M) Provide one input. The output of circuit 598 provides one input for each NOROR-Toro 03 and 607. 599 circuits output each NOR day) 6
Provides one O input of 04 and 608.

Signal T6- provides the other input of each NORpf-Toro 05-608. The outputs provided from NOR)f''-Toro 01-608 are signals 813-816 and 825-828, respectively.

FIG. 44H shows the generation of signals X and Y and their inverse O, as shown. Circuit 609 receives signals 02B, %c
3E, cL4.0L4- and provides one input of ANDNOR circuit 611. Further inverted, circuit 609 provides AND NOR circuit 61201 power. AND NOR circuit 610 outputs signals S2, S3,
OL4, OL4- is received, and its output is each AND N
OR circuits 611 and 6120 provide one input.

Signals CL8 and OL3- (d circuits 611 and 61
20 each input. The output of circuit 611 is a similar AND
Provides one input for OR circuit 613.

The output of the circuit 612 is a similar AND OR circuit 614.
Provide two inputs. T8-1B29 and Sl provide the other inputs of circuit 613. T8-1S29 and φ
1E- provides the other input of circuit 614. circuit 613
The output of is X- and is the inverted X. circuit 6
The output of 14 is Y- and inverted Y.

These D control signals are generated to serve as timing, dating and general control functions in equalization circuits as described below.

FIG. 45 is a schematic diagram of an adaptive equalization circuit used in this invention. Its use is particularly advantageous because it significantly reduces the noise cross-coupled between the transmit and receive channels of telephone line transmissions. Ideally, ■
The channel is represented mathematically by one cosine term with one constant. The Q channel is represented by one sine term with one zero constant. However, due to cross-coupling, there is a mixture of different sines and cosines, or theoretically an infinite number. This adaptive isoelectric constant has these O large unnecessary constants! 7) Effectively remove 4 pieces.

The 0 circuits for engineering CO and engineering C9 are the same. Therefore, the explanation will be limited to engineering CO only. The output CO is switched in by the signal S1 and stored in the t1 capacitor 0178, which is then fed into the comparator 621 and its associated circuitry, ie, the integrator circuit.

It is clipped by a comparator 622, the output of which is the signal IR, which is close to a digital signal, the squared one and the analog signal I
It is kicked out as EQ. Signal EQ is one input to the flip-flip FF 20 of FIG. 44A, and generates signals 0il-03E and C-E-. These O signals are also used to generate other timing signals O such as S2, S3, X, Y, etc. It will be appreciated that X and Y are used to generate signals 813 and 814, 821-824, S25 and 826, in turn. The switches turned on by these various signals are
Determine the sign of the false 9 constant to be accumulated (S13 and 514) and the length of time accumulated. When signal generator EQ is gated out to flip-flop F'F201 via signal 812, the summing stage is terminated. next,
The analog output RBQ, the output of comparator 621, is fed back and is inverted or not inverted by signals 813 and 814. This is the learning stage. It's the beginning. fM number 821-824 is sequential, capacitor 0170-
C! The error constant is stored in 173. These O capacitors are relatively large compared to other capacitors in the system. This is a capacitor with the correct sign (!170
- terminating the learning phase with various error voltages accumulated on
It is added together with Q. In the preferred embodiment, VRQ is 2 volts below the system standard of 5.5 volts.

This υ sum is integrated and sent out as a digital signal R.

As this process is repeated, the false 9 signal becomes smaller until the values set on capacitors a170-a173 are no longer the same and the system adaptively equalizes itself.

Between the learning phase and the addition phase, the signals φ1E and φ2E
together with capacitor c174 provide an interim signal VC○N which enters the circuit shown in FIG.

As indicated above, the Q channel is processed in a manner consistent with that described for the T channel. Signals IR and QR both pass through comparators 622 and 624.
812-, respectively, are held in sample-hold circuits as shown, and are dated out by signal 812-.

Signal 530id gates a transistor switch across each of the three capacitors c170-a17.

If either signal VAD or EDT- is high,
Signal 830 is high. That is, if no energy is detected within the receiver, the storage capacitor is shorted out. Also, in VAD mode, capacitor equalization is not used. He was shorted out.

FIG. 46 shows a signal VCO that serves as an input to an integrator circuit including operational amplifier 626 and bypasses the integrator circuit.
Indicates engineering N. The circuit shown here is very similar to the circuit described in Figure 43A. Signal VC○ 1 inch is signal φ
2) is input to the integrator vcr-) and stored in the capacitor 0178. It is noted that signal EDT- activates a switch across operational amplifier 626 such that the integrator is disabled if no energy is detected.

The output of the operational amplifier 626 is connected by the signal .phi.2, which is the signal VCO output in the main path.

These two O signals are summed and entered into a first order filter consisting of operational amplifier 627 and associated circuitry. amplifier 627
0 output is signal FV engineering 1. I, which is the error signal that is the voltage that is digitized and enters the analog-to-digital converter in FIG. 37D.

The first receiving buffer 23 basically operates in the opposite manner to the above-mentioned O transmitting buffer 110. One major difference is that during transmission, there is no stop bit 0 added to the receive buffer and no adjustment is required. Only when the stop bit is removed does the receive buffer need to compensate for actions such as those taken at the transmit end. Therefore, there is no additional logic in the receive buffer to remove the stop bit.

First, referring to FIG. 47, a combinational circuit 700 is shown in a block O shape. Phase decode logic circuit 701 receives signal IR
1 TE R-1 QRN QR- is received. Phase decoding logic circuit 7012) outputs from flip-flops 704 and 705
and subtraction logic 702 [present] input. In the transmit encoder section 12, an adder was used that added the current phase shift to the forward phase shift (Figure 7D).

In receive mode, the current phase shift must be subtracted from the previous zero phase shift. Signals DPI and D which are subtraction logic O outputs
P2 proceeds to logic circuit 703. Output is No. 18 RCDOU
It is T.

FIG. 48 shows the five-way component described in FIG. 47. It is recognized that the details of FIG. 48 υ are very similar to the details of the transmission function O shown in FIG. 7D.

Figure 49 shows the receiver 1d except for the illuminated circuit 700.
FIG. 2 is a block diagram of a buffer. υ signal R from circuit 700
ODOUT is shown as one input to scrambler 650 and RDL counter 655.

FIG. 50 is a slightly more detailed diagram of circuits 650 and 6551' further showing exclusive OR circuits 651, 652 and 653.

Details of these circuits are shown by combining FIGS. 51c, 51D, and 51E as shown. 1
Scrambler 650 consisting of 7 flip-flops
is shown, stages 14 and 17 are combined in the same manner as the transmit circuit shown in FIG. Of course, in the case of the receiver, the scrambled data is sent to circuit 650
! 7) Not scrambled by actuation.

PDL counter 655 is similar to PDL counter 208 shown in FIG. 7A. Case (7) was also used; this is a simple reversal of the action taken at the transmitter.

Of particular note is the signal RODOUT of FIG. 51D that is applied to exclusive OR circuit 652 shown in FIG. 51E. Exclusive-OR circuit 652 provides one input to exclusive-OR circuit 653 along with signal F_XR from PDL counter 655. The 0 output from the exclusive OR circuit 653 provides the output signal SCMO[JT ANDNOR) f'''-Toro 5417).

This signal sets flip-flop 330,
Cono output HAND NORM+-) 656 O1-O
It is an input. The output of NAND)f''-) 657 provides the inverted and direct inputs of circuit 656.A
ND date 6570 input is inverted S/A.

and BELT, /RV. The output signal from circuit 656 is RCVD, ie, the output from receive buffer 23 to terminal 5. The circuit described can be configured to use all receive buffers 23, such as all synchronous transmissions, when the conditions are right.
Allow a side road. However, any protocol that does not require scrambling and stop bit removal may bypass the receive buffer through this described circuit.

In protocols where the stop bit is removed, it is necessary in the receive filter 23 to reinsert the stop bit so that the message is understood. The stop bit is originally removed because the chain from the digital device source to the modem transmitter is faster than the telephone line O transmission speed and therefore the stop bit needs to be removed to cause the signal to be sent. As shown, the stop bit must be reinserted at the receiving end. Virtually all of the receive buffer 230 remaining circuitry, which has not been previously described, is relegated to the ζ stop bit insertion procedure. The signal 50M0UT from the output of circuit 654 is input directly to the character buffer 690 input shown in FIG. FF 3 Q 7 !7) Serves as the 0 special purpose O first stage for character buffer registers.

Signal SC Kyu, 40 [JT AND NOR date 692
, the other input comes from the flip-flip FF307QQ output, and the signals LS and LS
- comes from the stop unknown detection logic 740. circuit 69
The 20 output is connected to the J input of flip-flip FF 309, and is inverted and connected to its OK input. The clip-flop 309 is the first 70-bit flip-flop among the 11 D-type flip-flops forming a register with the flip-flop 311, which is the 11th flip-flop.

Character counter 765 counts incoming bits to know when a character is finished. The length of the character is determined by the signals C1 and C2 shown in Figure 51D,
This is set to a value equal to the signals C1 and C2 at the beginning of the transmission. NOR Ketoro 94 to O character buffer 6
The clock signal for 90 is inverted and the signal BIT CL
K-, which is a single input to character counter 765'').

The character counter 765 is a flip-flop FF 32.
1 to FF' 324 and PLA Y 66. The O output from the PLA 766 is inverted to provide a pair of cross-coupled 1qoR/7-”-)
This becomes the D input, which arranges the input register and presets the flip-flops vy 321-pb 374. Character buffer 690, flip 0, flop 30
The signal TB1- from the Q- output of 9 and the signal BREAK from the stop unknown detection logic 740 are connected to the signal BIT CL
Both OCK and Gc counter γ65Q input.

Signals c1b and C2 provide inputs to PLA 766 to control flip-flops FF321-FF324Q counts that indicate when a particular character length is obtained.

When the completed character is displayed, the output signal (B(OKEN) from the character counter 165 is output from the unknown stop detection logic 740 ovfliff0.
Provides clock operation for flip FF 314 and FF 315.

Once a complete character is placed in character buffer 690,
Stop unknown detection logic 740 checks to determine if there is a stop unknown bit.

So υ is clip-flop FF 314 and F
p31! M') Initiated by clock operation.

7 rip-flop FF 3 D 9 Q Q output, i.e. signal TB1, is clipped to 7' FF31jl
') is added to the J input, and its negation is added to the input from Q-. When the end of character is indicated, flip-flop Fl" 314 is set if TBl, which represents the stop bit, is high. If TBl is low, it becomes 71J tube flop FF 314tdo;
It will be displayed that it is not a stop bit.

To determine that the Q absence is actually a warpage and not a data break, we also need to examine the end of the next zero character. At the end of the next letter, the contents of flip-flop FF 314 are clip-flop FF 3.
15, NOR date 744 is flipped 70
It receives the Q-output from FF 314 and the Q-output from flip-flop FF 315. If the stop unknown bit actually exists (then the flip-flop F'
QQ-output and flip-flop FF from F314
The Q outputs from 315 and 44 are all 0, and the output from NCR door 44 is high. Is that a signal?
JODCLK paid by K, clock counter 6
70 and sets flip-flop FF 312 as shown in FIG. When it's 0, the ADDB Engineering T becomes high. Signal ADDBIT provides one input to NOR gate 694f7) and it
The other input is the signal MODOLK-. i shown before
The output of )n, NOR, -) 694 clocks flip-0 flops FF 309-FF 311.

Signal ADDBIT is the NOR key of character buffer 690.
) 6911) Provide one D input. N0R) f-toro 93 outputs signal B [JF
Drive high as indicated by OUT-.

Also, the signal M from the output of flip-flop FF 313 is high, resulting in the cross-coupled NOR signal shown in FIG. 51a.

Signal B[TFO[J'r- together with NAND key 8-
The signal 5HPULSE (short pulse enable) goes high after passing through the trol 97. This enables the short pulse counter 680 and indicates a short pulse of 1.
Clock counter 610 is input to provide pulses. 17) Signal 5HOWEN-output goes high from cross-coupled NAND date 742 of stop missing detection logic 740 and flips short pulse counter 680.
Preset flops FF316 to FF319.

Also, when the cross-coupled NANA key) 741 fl of the stop unknown detection logic 740 should add a stop flyer, the signal LS is made high. Signal LS is character buffer 69
7 rip-flop FF 307 Q output to circuit 6
Key to 92. Flip flop P゛F307
acts as a special stage of the character buffer in which the stop bit is inserted in case of 8 Atsushi. flip flop FF 3
07 and FF' 308 are λ·l0DC! LK (C
Thus, while the flip-flops in character buffer 690 are gated by MODOLK so that flip-flops FF' 307 and F3 (18) do not move when the stop bit is added. Note that it is disabled by ADDBIT.

FF 308 is used as a special final stage of the buffer register. Is clock counter 670 cross-coupled? l0R)
7″′-Drawer 2, Flip-7o knob FF 301-
Consists of FF 303, FF 304 and FF 305, and PLA 571. Normally, the flip-flops 71''FF301-FF303 are free-running.

When short counting is enabled, the PLA causes a flip-flop reset after a specified count. There is a reset after 7 counts in normal mode and 6 counts in overspeed mode.

A stop bit counter 660C counts the stop bits and is shown in detail in FIG. 51B.

It is a mirror image of character counter 765 with slightly different inputs. It is one from counter 765, signal TB 1
one from, and a signal beep) C! 1 from LK-]
The output from the zero counter 660 serving each input is a cross-coupled NOX counter 96 f, I'r; +-J
- Set by M.

FIG. 52 shows an input run of characters with an unknown stop bit at time T1. A stop bit of size 3/47) is inserted at the output. This figure shows the '/8 pulse step <3/4
0 indicates an overspeed protocol such that pulses are applied
At time T2, the stop bit has been shortened as shown in the output waveform. At time T3 it is shortened again as shown and at time T4 it is shortened again so that the input and output signals are now in phase.

To summarize the receive buffer O operation, FIG. 47 shows a single digital column signal RC! 2 shows the reconfiguration of DOUT.

FIG. 49 is a block diagram of the remaining part of the reception filter. Scrambler 650 and PDL counter 655 reverse the operation of their transmit buffer counterparts. In the case of transmission where the receive buffer is used, the scrambler output is 1 to 40M.
Go to 0UT ij character buffer 690. The character rebits are counted by counter 765 depending on the state of control signals C1 and 02. At the end of a character, stop unknown detection logic 740 determines whether the stop bit is unknown. If the stop bit is clearly unknown,
The next υ character is read into the character buffer and the presence or absence of the stop bit D is detected again. If it is not unknown, then 0 before
The estimated mixed stop pulse from the detection is actually a stop unknown pulse, not a break during transmission. A pulse will not sink unless it is inserted by the interaction of the short pulse counters 670. A short pulse is inserted at the end of the first character υ in a special flip-flop D character buffer designed for that purpose. The stop bit must be shortened so as to obtain an incoming pulse train υ in phase with the incoming pulse train that is changed by enriching it. The stop bit must be narrowed as shown in FIG. The total number of narrowed stop bits is determined by the particular transmission protocol. In the 52nd example, the total number of stop bits is four.

The precise circuitry and operational details are as detailed above. The operation will be briefly described below. Starting from FIG.

The transmission buffer 11 is a circuit for synchronously transmitting variable speed asynchronous data. In the case of O-synchronous transmission from terminal 5 to terminal 7, the transmission buffer is not used.

Each character, consisting of 8-11 bits, is preceded by one start bit and followed by one or two stop bits in the most widely accepted protocols. The bits of each character are transmitted at a fairly narrow data rate, but the character rate can vary widely.

In normal 1200 BPS Q operation, the buffer sends it over the telephone line at a constant 1180 BPS.
It is designed to accept data from a digital source 5 at a rate of -1240 BPS.

- If the constant PS is faster than the BPS rate of the digital data source, a stop bit must be added. If it is slower, the stop bit must be removed.

As soon as the start bit occurs, the circuit starts counting bits - and as it receives valley bits, it synchronizes the bits with the send f5 data clock 16. The transmit buffer 11 uses the scrambler used in D to ensure that the transmitted carrier is often sufficiently phase shifted for the receiving modem to remain locked. If the source data is sent directly, a specific 0 regular bit butter 7 (eg, alternating mark space data) may result in a carrier wave transmission with a 0°D phase shift.After this transmission, 2 - After 6 milliseconds, the receiving modem loosens its lock, making it impossible to demodulate the data.The actual pattern that produces a constant carrier using a scrambler is extremely complex, and the probability of transmitting it by accident is significantly reduced.

Also included is an RDL counter 208 shown in FIG. 7A (not shown in FIG. 2). A test O remote loop back operation can be initiated with a number of consecutive signals. The RDL counter counts in 128 turns, and if such count is achieved i'L, the next O bit is inserted into the RDL loop to avoid locking.

As mentioned above, stop bits are added or removed through the circuitry previously detailed.

The modified digital data passes to a transmitter with an encoder, modulator and transmit filter. The encoder converts the data to be transmitted IH into phase shift information to be used by the modulator.

As a standard, the baud rate is 600 when the data transfer rate is approximately 1200 nps. This is accomplished by two bits providing information for the 4-phase PSK transmission. Two bits are required for each change in phase 0.

The twin-bit encoder is completely data independent. For any particular bit pair, the encoder must be signaled about the particular protocol in use. when fc
Once that is known, the circuit generates the appropriate phase shift information. This circuit is shown in FIG. 7B and provides the output signals N1 and DIN'1 and their inverses.

These 7) signals are the first to provide a suitable locking signal.
Two figures are input. The next circuit is the transmit modulator. As shown in detail in FIGS. 16A and 16B, the output signal PSK ll''j is a modulated analog output signal.

The signal PEIKOUT is then filtered by a transmit filter, which includes a voiceband filter that rejects out-of-band signals, and an equalization filter that predistorts the signal to count phase and amplitude distortions in the telephone line. It is configured. This filter actually consists of two parts. A signal TXPA is generated.

FIG. 1 shows the signal ROVA received by the modem receiver.
shows. The input filter acts as an anonymous filter and prevents high frequency signals from entering the demodulator. The details and continuous manual filter are shown in Figure 26 and Figure 29A-2.
Shown in Figure 9E.

These O filters are designed to compensate for telephone line O distortion. They do not compensate for crosstalk between the transmit and receive lines.

The reception AGC 19 is an automatic gain control circuit that adjusts the gain as described in detail.

The carrier number circuit 20 and clock recovery circuit 21 have been described in detail and provide the necessary data and accurate locking for the receive decoder 22.

The receive decoder 22 includes an isoelectric device as described in FIG. 45 which essentially eliminates crosstalk not excluded by the incoming filter. The output of the receive decoder 22Q is the two-bit code received by the receive buffer 23 and recombined to provide a pulsed binary sequence. If the sequence is a sequence in a protocol that does not require the stop bit to be removed, then
If in the receive buffer, non-scramble is essentially bypassed. If the transmission remains synchronous, the receive buffer is bypassed. In other cases, a stop bit is added and the duration is made shorter to preserve the frequency.

Finally, digital data receiver 7 receives the demodulated digital data.

The operation described is, of course, highly dependent on the filter used. The z-domain transfer functions of these filters D are given below: QIICf511
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Anyone skilled in the art may depart from the preferred embodiments set forth herein without departing from the spirit of the invention. are possible, but are limited only by the scope of the claims.

[Brief explanation of drawings]

Fig. 1 is a block diagram of this invention 0 bidirectional digital data transmission cylinder 0, Fig. 2 is a block diagram of this invention 0 transmission buffer, and Figs. 6A to 6C are transmission buffer f/).
DTE and SOT clock generation circuit, start/stop counter, character bit counter, input sampling circuit, stop bit detection circuit, up/down counter and FI
A schematic diagram of the FO circuit, Figure 4 is a data bit extraction circuit diagram, Figure 5 is a transmission buffer stop bit insertion/deletion control circuit diagram, and Figure 6 is a transmission buffer modem selection circuit diagram. Figures 7A and 7B are diagrams of the scrambler and double-bit generator circuit of the transmission buffer, Figure 8 is a diagram of the signal generator circuit used in the transmitter, and Figure 9 is a diagram of the control signal for the up/down counter. Generation circuit diagram 0, 10th
Figure 1 is a schematic diagram showing the generation of timing signals for the transmitter.
Figure 1 is a schematic diagram showing the timing signals for the transmitter and Q channel timing; Figure 12 is a schematic diagram showing the data-induced timing signal generation to modulate the transmitter and Q channels; Figure 16 is the input square diagram. 14 is a diagram showing the transmitter timing signals; FIG. 15 is a diagram showing the signals used for carrier wave generation; FIG. 16A and FIG. 16B is a schematic diagram of a transmit modulator, FIG. 17 is a schematic diagram of a switching circuit for switching capacitance into and out of the circuit, and FIG. 18 is a schematic diagram of a transmitter gain compensation filter 7). Figure 19 is a schematic diagram of the transmitter phase compensation filter, Figure 20 is a diagram of waveforms at various points inside the transmitter, Figures 21 to 251!
XI+ is a diagram of a timing signal generation circuit used in a modem receiver, FIG. 26 is a schematic diagram of a continuous filter for receiving a PSK signal with a sampled low-pass filter with a block diagram of a PSK receiving filter, FIGS. Figure 27B shows the signal generation circuit O that controls the gain of the PSK reception filter.
Schematic diagram, FIG. 28 is a schematic diagram of energy detection signal generation O,
FIGS. 29A to 291B are schematic diagrams of receiving filters,
FIG. 60 is a block diagram of automatic gain control and related circuits;
31A to 310 are schematic diagrams of specific AGO circuit 0,
Fig. 32 is a block diagram of a digital voltage controlled oscillator used in the carrier recovery loop, Figs.
From Figure A to Figure 36D, 'Heavy pressure control oscillator circuit and circuit 47) 'I'ra generation cr> at 1lsh
Figures 37A to 37D are schematic diagrams of the A/D converter and the υ signal generation O.
Figure 8B is a schematic diagram of the count control circuit; Figures 39A and 8Z are schematic diagrams of the phase shift circuit; Figure 40 is a schematic diagram of the buffer filter; Schematic diagrams 3, 43A and 4 showing timing signal O generation (for clock recovery loop)
Figure 3B is a schematic diagram of the clock recovery Lubri, Figures 44A to 44H are schematic diagrams of timing signal generation for the adaptive equalizer, Figure 45 is a schematic diagram of the adaptive equalizer, and Figure 46 is A().
Schematic diagram of input signal generation for the 0 circuit, Figure 47 shows the basic band/
Block diagram of digital conversion, Fig. 48 is a schematic diagram of basic band/digital conversion, Fig. 49 is a block diagram of 7 receiving pants, Fig. 50 is a block diagram of scrambler and data luzo counter D, from Fig. 51A. FIG. 51E is a schematic diagram of the receive buffer O, and FIG. 52 is a schematic diagram of the input waveform with the 1ψ stop bit removed and the corresponding output waveform with the stop bit added. Description of main codes: 5 - terminal device; 11 - transmission buffer; 12 - transmission encoder; 13 - transmission analog circuit; 14 - transmission equalization circuit; 16
- Transmission clock; 17 - Reception clock; 18 - Reception filter; 19 - Reception AGOi2〇 - Carrier recovery circuit; 21
- Clock recovery circuit; 22 - Reception decoder; 23 - Reception buffer 11 C Fig /4 ig15 125 to C?・1. Il￥6Z″61” Straw Akebono = 1 Steam 1: ]: Memil” EE IE
+= に; 1 day; ■408558 @August 16, 1982 ΦUnited States (US) @408559 @August 16, 1982 ■United States (US) ■408578 0 Inventor William A. Severin Texas, USA State Hyuston Postwick Co.) 7222 Procedural amendment (method) % formula % 1. Indication of the case Patent Application No. 148187 of 1988 2. Name of the invention Bidirectional digital data communication device Relationship with Nor1 - Applicant (] Sanmeisho Name Texas Instruments (Name)
Incorporated 4, Agent 5, Date of amendment order Showa (Year 1/Month 2nd 6) Number of inventions increased by amendment Copywriting of specification (no change in content) Procedural amendment (method) 1982 Mr. Commissioner of the Japan Patent Office, February S, 1958 Special Request No. 148187
No. 2, Title of the invention 3, Relationship with the person making the amendment 11+ cases, 1'1 Applicant 4, Agent 5, Date of amendment order f'' November 29, 1981 6, Inventions increased by amendment Number 7, Supplementary "1'1' of the target drawing of F:" + (Contents; no change) 8,
Contents of the amendment As shown in the attached sheet

Claims (9)

[Claims] (1) generating a digital signal and transmitting a PSK modulated signal representing it at a first carrier frequency over a first transmission line;
A bidirectional digital data communication device that receives a PSK modulated signal at a second carrier frequency via a second transmission line and further converts it into a digital signal representing it, comprising: (a) a digital data generation and reception device; (b)
PSK 1M connected and corresponding to receive digital data from the digital data generating/receiving device
(C) a PBK modem transmission encoder for encoding the digital data into a first format for conversion to a signal; (d) a PSK modem transmit modulator for phase modulating a first carrier frequency according to a first format to provide a PSK signal; (e) a PSK modem receiver and demodulator for demodulating the PSK signal at the second carrier frequency for conversion to a corresponding digital signal; and (e) connected to receive the second format for encoding the second format into a corresponding digital signal. and a PsK modem receiving and encoding device connected to transmit a corresponding digital signal to the digital data generating and receiving device. (2) A patented data communication device characterized in that the demodulator includes a clock recovery device that supplies a sampling signal from the demodulated PSK signal. (3) A bidirectional digital data communication device according to claim 2, wherein the digital data generation and reception device includes a data terminal device. (4) A bidirectional digital data communication device according to any one of Patent Nos. 1 to 3, wherein the sampling analog signal processing circuit includes a switching capacitor circuit. (5) fabricated on a single semiconductor chip for transmitting and receiving PSK signals derived from digital signals provided at first and second carrier frequencies by first and second transmission lines, respectively; an integrated circuit PEIK modem comprising: (a) a digital signal for conversion to a corresponding PSK signal;
(b) a transmission encoder for encoding the data in a first format;
(C) a transmit modulator coupled to the transmission line for phase modulating the first carrier frequency according to the first format to provide a corresponding PEIK signal; a receiver demodulator for providing a PSK signal and demodulating the PSK signal from the second transmission line for conversion into a corresponding digital signal; (d) connected to receive the second format and converting the second format into a digital signal; The modem characterized in that it includes: a reception encoding device for encoding; (6) A modem according to claim 5, characterized in that the demodulation device includes a clock recovery device that supplies a sampled signal from the demodulated PSK signal. (7) In the modem according to claim 5, the demodulation device is connected to a low-pass filter device that receives an input voltage signal, and to receive an output from the low-pass filter device and integrate the signal. a parallel path device connected to the output of the low pass filter device 141 and in parallel with the integrator, and a gain connected to receive the output from the integrator and to sum the outputs of the low pass filter path. a phase adjustment device, the gain adjustment device having a gain adjusted to a value where the output of the low pass filter exceeds the output of the gain adjustment device; and a voltage controlled oscillator device connected to receive the summation output. 3. A modem as described above, comprising: a fixed loop; and a receiving encoding device connected to receive the second format and encoding the second format into a corresponding digital signal. (8) In the modem according to claim 5, the demodulator includes an input device that receives an input voltage signal, a first integrator connected to the input device, and a second integrator connected to the input device. an integrator and a comparator having one input connected to the outputs of the first and second integrator and another input connected to the limiting voltage; is connected to the second integral divider and is responsive to the output of the comparator to switch the first fJ divider into the circuit and switch out the second integrator when the second integral output reaches a critical voltage; an integral voltage controlled oscillator including a switch device with the reverse also true; and a receiving encoding device connected to receive the second format and encoding the second format into a corresponding digital signal. said modem. 9. The modem of claim 8, wherein the switching device includes a flip-flop clocked by the output of the comparator. {10} Further combining first and second switches controlled by the output of one of the flip-seven loops, the first switch selectively connecting the output of the first integrator to the input of the comparator, and the second switch selectively connecting the output of the first integrator to the input of the comparator. 10. The modem according to claim 9, wherein the second product device is selectively short-circuited from the circuit. (l l) A modem according to claim 5, wherein the transmit modulator comprises a plurality of selectable capacitors connected in parallel and connected to receive the first type provided to the switched capacitor circuit. and at least one filter, and a first filter to provide the corresponding PSK signal.
phase modulating the first carrier frequency according to a format; and the receiving demodulator having at least one filter with a plurality of selectable capacitors connected in parallel applied to the switched capacitor circuit, each modulating and demodulating device a corresponding digital signal, each switch device connected to the filter having said switch device including a device for selecting all of at least one capacitor connected to the filter and a device for setting the stray capacitance of any capacitor not selected to D; a second PSK signal to be converted into a second format;
The modem described above demodulates a PEtK signal at a carrier frequency. Patent No. 51 to 11, wherein the O3 sampling analog signal processing circuit includes a switching capacitor circuit.