JPS59112338A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten a retrieving time and to reduce the load on a CPU by adding a self-retrieving function to each memory. CONSTITUTION:When a retrieving terminal inversion REF signal is ''1'', normal operation is executed and an address ADD is supplied from an external device to an address buffer 12. When the inversion REF is ''0'', a controlling circuit 17 supplies the output of an address counter 21 to the buffer 12. A comparator circuit 22 compares data read out from a memory cell array 11 with previously stored retrieving data. When both data coincide with each other, the coincidence is informed to the controlling circuit 17. Consequently, the controlling circuit 17 stops the address counter 21, and transfers the value of the address counter 21 to the CPU through an address bus 23, the circuit 22, and a terminal I/O, to wait the succeeding instruction from the CPU. If the data to be retrieved has been previously stored in the circuit 22, retrieving operation will be executed automatically only by setting up inversion REF=0.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor memory device used in a large converter or the like.

(2) Prior Art and Problems Generally, large converters are equipped with a large number of semiconductor storage devices (hereinafter simply referred to as memories) as main memory. Searching for data from such a large number of memories has conventionally been carried out by a CPU (Central Processing Unit) reading data from each memory and comparing this data point by point with the search data. However, in this case, the search time becomes considerably long, and the
There is a problem that the load on the cPU also increases.

(3) Purpose of the Invention The purpose of the present invention is to:
By adding a self-search function to each memory, the purpose is to shorten the search time and reduce the load on the CPU.

(4) Structure of the Invention In order to achieve the above-mentioned object, the present invention includes a memory cell section, an address buffer section, and an address for decoding the output of the address buffer section to select the memory cell section. A semiconductor memory device comprising a decoder section and a control section for controlling each of the sections, a search terminal connected to the control section, a storage means for storing search data, an automatic search address generation means, and a comparison means for comparing the search data of the storage means and the data read from the memory cell section, and when the potential of the search terminal is set to the search level, the control section automatically generates a search address. There is provided a semiconductor memory device characterized in that the output of the address buffer section is switched to the address buffer section, thereby comparing read data from the memory cell section with the search data.

(5) Embodiments of the Invention The present invention will be described below in comparison with a conventional example with reference to the drawings.

FIG. 1 is a block circuit diagram showing a conventional conbeater system using memory. In FIG. 1, a memory system 1 includes, for example, 8×8 (=64) memories Mll.
,M,2. M, 1. M22. ..., and these are controlled by one CPU 2. 3 indicates an address bus, and 4 indicates a data bus.

In addition to this, there is a control signal line between the CPU 2 and the memory, but it is omitted in the drawing because it is not necessary for this explanation.

For example, if each memory has a configuration of 8 words x 8 bits, the entire memory system 2 has (8 words x 8 bits) x 64 = 512 words x 8 bits. Therefore, the time TRF,F for reading and searching all the data in the memory system 2 word by word is TR,F=5
It can be expressed as 12KX teye (however, toyo is the cycle time). In this case, the cycle time t. yQ is at most 200 ng. Therefore, TR #105m11 (
1) (5), which requires a considerable amount of search time, and the CPU2
It can be seen that the burden will also increase.

FIG. 2 is a block circuit diagram showing one embodiment of the memory according to the present invention. In FIG. 2, elements 11 to 17 and external control signal line terminals RAS and CAS.

wE has conventionally existed, and elements 21, 22, 23 and search terminal RIDF are added according to the present invention.

That is, 11 is a memory cell array, 12 is an address buffer, 13 is a row decoder, 14 is a column decoder,
15 is an I10 gate, 16 is an I10 buffer, and 17 is a control circuit for controlling these.

Further, according to the present invention, an address counter 21 increments or decrements an address, a data latch 22 for storing search data, and a data latch for storing the search data and read data from the memory cell array 11. 23 is an address bus provided in (4) for sending out the address of the address buffer 12 from the I10 terminal.

When RIIEF="1#", normal operation is performed. That is, the control circuit 17 outputs signals RAS and CAS.

A read or write operation is executed based on wg, and in this case, address ADD is supplied to address buffer 12 from the outside.

On the other hand, when RgF=''0#, the control circuit 1
7 transfers the output of the address counter 21 to the address buffer 1.
2. Further, in the circuit 22, a comparison is performed between the data read from the memory cell array 11 and the search data stored in advance, and when the two match, the control circuit 17 is notified of this fact. Then, the control circuit 17 further stops the address counter 21 and transfers the value to the address bus 23, circuit 22, I10.
It is transferred to the CPU 2 via the terminal and waits for the next instruction from the CPU 2.

Note that the address counter 21 is sequentially incremented or decremented by a clock from a clock generation circuit (not shown) when iF="O".

In this way, in the memory of FIG. 2, if the data to be searched is stored in the circuit 22 in advance, moe f="0"
The search operation will be performed automatically.

FIG. 3 is a block circuit diagram showing a converter system equipped with the memory shown in FIG. 2. That is, compared to FIG. 1, only a search signal line 24 is added.

In this way, each memory Ml(, Mt(, M21'
, M, , '... are automatically and simultaneously searched, the search time TREF for the entire memory system 2 is
'p'=BKxt #1.64m5 (2
) RKF e70, which is 1 compared to equation (1) in the conventional type shown in Figure 1.
．． 64/105=1.5%), which makes it very short.

Furthermore, the CPU 2 is freed from this short period of time, and the burden on the CPU 2 is therefore greatly reduced.

(6) As described in detail, according to the present invention, the search time can be shortened and the burden on the CPH can also be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram showing a computer system using a conventional memory, Fig. 2 is a block circuit diagram showing an embodiment of the memory according to the present invention, and Fig. 3 is a computer system using the memory shown in Fig. 2. FIG. 2 is a block circuit diagram showing the system. 1: Memory system, 2: CPU, 3 Near address bus,
4: Data path, 21 Near address counter, 22: Data latch computer, 23 Near address path, 24:
Search signal line, REF: Search terminal, Ml, , M1
! ,...t M11' r M12',... memory. Patent applicant Fujitsu Ltd. Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate 1) Yukio Patent attorney Akira Yamaguchi

Claims (1)

[Claims] 1. Memory cell section, address buffer section. In a semiconductor memory device comprising an address decoder section for decoding an output of the address buffer section and selecting the memory cell section, and a control section for controlling each of the sections, a search device connected to the control section; terminal, a storage means for storing search data, automatic search address generation means, and. Comparison means is provided for comparing the search data of the storage means and the data read from the memory cell section, and when the potential of the search terminal is set to the search level, the control section controls the output of the search address automatic generation means. A semiconductor memory device characterized in that the address buffer section is switched to the address buffer section, thereby comparing read data from the memory cell section with the search data.