JPS59104887A - Video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain an excellent reproducing signal by synchronizing a readout clock synchronized with a write clock signal applied to a delay element of a time axis expanding circuit and applied to the delay element to a luminance signal. CONSTITUTION:The reproduced Y signal 55 is inputted to a (2H+alpha) delay circuit 57, where the phase is delayed by (2H+alpha). A part of the delayed signal is inputted to a horizontal synchronizing separating device 58, where an H signal 65 is separated. This signal 65 is inputted to a clock generating circuit 60 and a signal 67 synchronized with the Y signal 62 is outputted. Taking signals compressing the time axis of chroma signals I, Q as respectively i, q, a reproduced (i+q) signal is inputted to a time axis expanding device 59 from an input terminal 56 and controlled by the signal 67. The reproduced (i+q) signal is expanded by readout with a clock signal 55 synchronized with the reproduced Y signal, and the I signal 63, the Q signal 64 are outputted without any time difference with the reproduced Y signal 62.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal recording and reproducing device, which is small, lightweight, and can obtain high-quality reproduced video signals, and is particularly suitable for news gathering (ENG) and program production. It can be used in the field of magnetic recording and reproducing devices for commercial use (RFP).

Conventional configurations and their problems At present, the mainstream magnetic recording and reproducing apparatus (hereinafter referred to as VTR) is a helical scan type in which a rotating head forms video tracks diagonally on a tape. In particular, home VTRs are becoming smaller and more dense. For example, in a VH3 type VTR, a video signal is recorded obliquely onto a 5-inch wide tape using two video heads arranged at 180° to each other on a rotating cylinder having a diameter of 62 mm. In addition, broadcasting V
TR3 /, - Portable VT for news gathering even by smell (ENG)
In R, small size and light weight were strongly desired, and inch U standard VTR was adopted.
is also making considerable inroads. ENG VTRs are required to be small and lightweight, and because they are used for broadcasting, high image quality is required. 'A inch U standard VTR has a cylinder diameter of 11
Since the tape width is 0 mm and the tape width is % inch, there is a limit to miniaturization.In addition, as a recording method for video signals, the luminance signal is converted into a frequency modulated wave, the low frequency is removed, and the low frequency is converted to the carrier. Since a method of superimposing color signals is used, the bands of the luminance signal and color signal are limited, and the image quality is not necessarily sufficient for broadcasting. FIG. 1 shows the recording pattern of an NTSC 2% inch U standard VTR. In FIG. 1, Tw, TP, and Ts represent video track width, video track pitch, and space, respectively;
6μm, Tp=137t1m, TB=52μm
It is.

The present invention takes the above points into consideration and provides a device that is small, lightweight, and capable of producing high-quality reproduced images. According to the present invention, high-quality images can be obtained even with a cylinder diameter and cassette of the same size as a VH8 system VTR, and the VTR can be made smaller and lighter than a conventional ENG VTR.

FIG. 2 is a plan view of the head arrangement on a cylinder used in the present invention, FIG. 3 is a front view of the head, FIG. 4 is a diagram showing an example of a recording pattern by the head, and FIG. 6 is a diagram showing the head. Block diagram of an embodiment of the recording method by
The figure shows a waveform diagram of the main parts in FIG. 6, and the recording method according to FIG. 6 will be explained.

In FIGS. 2 and 3, A, A/and B.

B' represents two sets of heads arranged at the same height and 18oO on the cylinder circumference. Also, A and A in Figure 4
', B, B/ are respectively A, A', B,
B' represents the trajectory written by the head. In Figures 3 and 4, TA and TB are A (A') and B, respectively.
(B/) represents the track width of the head, TP represents the track pitch, and Ts represents the space. Now the diameter of the cylinder is 9
Number of revolutions.

In Figure 3! and the value of y, the tape speed of TA, TB, and Ts, and the angle formed by the tape and the recording trajectory5 +,
- If determined precisely, the head arrangement as shown in FIGS. 2 and 3 can produce a trajectory as shown in FIG. 4. - For example, it is possible to construct a VTR that has a cylinder with a diameter comparable to that of a VH8 system VTR and is capable of recording approximately 20 minutes with a VHS central.

One method for recording and reproducing color video signals with the recording and reproducing apparatus described above is to record the luminance signal (
There is a method of recording color signals (frequency modulation) using a B (B/) head. In this way, the track width of the luminance signal can be increased, and since the color signal is not superimposed, the band can be widened, and a reproduced image with high S/N and high resolution can be obtained. Furthermore, since the baseband signals (eg, I signal and Q signal) can be frequency-modulated and recorded as color signals, it is possible to obtain a reproduced signal with a wide band and high S/N. The present invention thus provides a device that is small, lightweight, and obtains high quality images. In the above example, it is constructed with a cylinder having the same diameter as a VH8 system VTR, and it is possible to record approximately 20 minutes on a VHS cassette, making it possible to construct an ENG VTR that is smaller, lighter, and of higher quality than the conventional one.

The recording method shown in FIG. 6 will be explained below in accordance with FIGS. 4 to 6. In Fig. 5, 1 is a Y signal (luminance signal) input terminal, 2 is an I signal input terminal, 3 is a Q signal input terminal, 4 is a time axis compressor, 6 and 6 are frequency modulators, and 7 and 8 are recording Amplifiers, 9 and 10 are video heads, 11.12 are regenerative amplifiers, 13° and 14 are frequency demodulators, 15 is a time axis expander,
16 is a Y signal output terminal, 17 is an engineering signal output terminal, and 18 is a Q signal output terminal.

Still, in Fig. 6, 1, 2.3 are the input Y
Waveforms of signals, engineering signals, and Q signals (for convenience, the waveforms of I and Q signals are also
A horizontal synchronization signal is added. ) 19 is time axis compressor 4
These are the waveforms of the output signals indicated by the respective numbers in FIG. The Y signal applied to the Y signal input terminal 1 is modulated by a frequency modulator 6, amplified by a recording amplifier 7, and then
The head 9 records the information on the tape. Y signal is about 4 hours
In order to record and reproduce this signal with good performance,
The modulation frequency 71-wave number shift is set to, for example, 4.4 to 6 stones.

■Signal input terminal 2. The I signal and Q signal applied to the Q signal input terminal 3 are converted into waveforms 19 in FIG. 6 by the time base compressor 4.
The signals are compressed on the time axis and synthesized such that the first half of one line (1H) is the engineering signal, and the second half is the Q signal. This signal is modulated by a frequency modulator 6, amplified by a recording amplifier 8, and then recorded on a tape by a head 10. ■The signal is about 1
．． The 5JQ signal has a band of approximately 0.51%, and the signal obtained by compressing the time axis of each signal to % has a band of approximately 1 ratio in the I signal part (denoted as I) and 3 in the JQ signal part (denoted as Q). However, since it is almost sufficient for a signal to have a bandwidth for one warehouse, one signal can be used for two cities. The frequency shift of this composite signal is set to, for example, 3.5 to 6 stones. The tape pattern in which the Y signal and color signal are recorded by the two pairs of heads having the above-described structure is as shown in FIG. In FIG. 4, A and A/ are the recording loci of the Y signal, and B and B' are the recording trajectories of the color signal. As shown in Figure 4, for the Y signal, the track width is larger than that of the conventional VH8VTR, and for the color signal, the band is about 2 hours, so the S
/N can be played well. During reproduction, the Y signal reproduced from the head 9 is amplified by a regenerative amplifier 11, modulated by a frequency demodulator 13, and a reproduced Y signal is obtained at an output terminal 16. On the other hand, the color signal reproduced from the head 1o is amplified by a regenerative amplifier 12, demodulated by a frequency demodulator 14, and then expanded by a time axis expander 16 and separated into the original I signal and Q signal. Reconstruction signal on 17.18.

A Q signal is obtained.

Next, the time axis compressor 41 and time axis expander 16 will be explained. 8 and 9 are specific examples of a time axis compressor and a time axis expander, respectively, and FIG. 7 is a specific example of a time axis expander.

A specific example of the switch (SW) signal and clock signal generator for FIG. 9, and FIG. 10 shows the waveforms and signal order of each part of FIGS. 7 to 9. In these figures, the same numbers as in FIG. 5 represent the same things. In Figure 7,
21 is a horizontal drive signal (HD) input terminal, 22 is a PLL circuit, 23 is a switch (SW) signal generator, 24 is a frequency divider, 25 is a gate 9/- gate, 26.27 is an SW signal output terminal, 28 .29 is a clock signal output terminal, which is connected to the same numbered part in FIGS. 8 and 9. In FIGS. 8 and 9, 30 to 34 are switch circuits, and 36 to 42 are delay elements to which signals are transferred in accordance with a clock, such as a COD.

The numbers on the left side of FIG. 10 represent the waveforms and signal sequences at the same numbered positions in FIGS. 7-9. ■1. I2...
are I signal lines 1, 2 . ... signal, Ql,
Q2... is the line 1, 2, . . . of the Q signal.・・・・・・
・Represents the signal of 11. I2. Ql, Q2...
・Things with a minus sign above them are in a compressed state, 41
142 +91192 . . . with a minus sign at the bottom indicates an expanded state. Also, tA+Q1
Those with an A added, such as A..., represent the signals in the first half of the line, and those with B added, such as ■tB+01B, represent the signals in the second half of the line. C0D36
When the number of stages of ~42 is n and the clock frequency is fc, the delay time is n/fc. Therefore, if the horizontal scanning frequency is fH and the clock frequency is n fH, the COD delay time is n/nfH - 1/fH, which is 1H.
(Hh horizontal scanning time) 1ol ゛If the clock frequency is 2nfH, the COD delay time is n/2nfH=1/2fH-0,
It will be 5H. In FIG. 7, the HD signal applied to the terminal 21 is guided to the PLL circuit 22, where a continuous signal with a frequency of 2fH is obtained, and further, a continuous signal with a frequency of nj'H is obtained from the period divider 24. On the other hand, the HD signal is also led to the SW signal generator, and the SW signal shown as 26.27 in FIG. 10 is obtained at the terminal 26.27. This sw multiplied signal, the frequency nfH and 2nfH signals mentioned above are controlled by the gate 25, and a lock signal as shown as 28.29 in FIG. 10 is obtained at the terminal 28.29. Switch 30 in FIGS. 8 and 9
~34 are controlled by the SW signals 26 and 27, and are connected to the a side when the SW signal is at a low level, and to the b side when the SW signal is at a high level. In FIG. 8, the Q signal applied to terminal 3 is CC
D36. Guided by CCD38. The CCD 36 is driven by two clock signals.

For example, if the frequency of the clock 28 on line 3 is 2nfH, the Q signal applied to the CCD 3e (see FIG. 10, 45.
In part 03 of 3), the first half (Q3A) is delayed by 0.5H and output. Center of Q3 (border between Q3A and 03B)
From the time when the signal is output to the CCD 36, the clock 2
Since the frequency of 8 becomes nfH, the 03B section is written at a clock frequency of 2nfH, and is read out at nfH, so that the time axis is expanded twice and outputted to line 4 as Q3B. Since Q4 is written with a clock of frequency nfH and read out with a clock of frequency 2nfH, the time axis is compressed to % and output as 04 in the first half of line 6. Thereafter, by repeating this process, a signal 46 is obtained at the output of the CCD 36. Signal 46 and I signal 2 applied to terminal 2 are switched by switch 30 to obtain signal 43 at its output.

Here, switch 3o is controlled by SW signal 26, and lines 3, 6 . . . . to the b terminal (signal 46), lines 2, 4 . . . . is connected to the a terminal (signal 2). The signal 43 applied to the C0D 35 is delayed, compressed, and expanded in the same manner as described above, and a signal 44 is obtained at its output. In exactly the same way, CCD37. CCD38.
Switch 31 provides signal 48 at the output of CCD 37. At this time, the switch 31 is controlled by the SW signal 27, and the lines 3, 6 . ...... then terminal a (signal 2)
, line 4, . . . are connected to the b terminal (signal 50).

Signal 44. Signal 48 is directed to switch 32 and terminal 19
A signal 19 is obtained. At this time, the switch 32 is controlled by the SW signal 27 and operates in the same way as the switch 31. In this way, a signal is obtained at the terminal 19 in which the I signal is time-compressed to % in the first half of one line, and the Q signal is time-compressed to % in the second half (FIG. 6, 19 and FIG. 10, 19). In FIG. 9, during reproduction, the time axis compressed signal applied to the terminal 2o (FIG. 10, 20, same as FIG. 1, 19) is transmitted to the CCD 40,
Guided by CCD42. CCD 40 has a clock of 28,
The CCD 41 is controlled by a clock 29, and signals 61. A signal 53 is obtained. These signals are transmitted to CCD39. The signals are guided to a CCD 41 and controlled by respective outputs 29. Signals 52 and 54 are led to a switch 33 controlled by a 2.13 two-switch signal 26, and a reproduced I signal 17 is obtained at its output terminal 17. Further, the signal 51 and the signal 63 are guided to a switch 34 which is also controlled by the switch signal 26, and a reproduced Q signal 18 is obtained at its output terminal 18. At this time, signal 18. signal 19
is delayed by two lines compared to the original state, but this can be compensated for by delaying the Y signal by two lines.

In this way, high quality reproduced color signals can be obtained. - However, in the above explanation, since a head with a force structure as shown in Figs. 2 and 3 is used, due to variations in the value of Even during recording and reproduction, a time difference may occur between the reproduced Y signal and the reproduced color signal. The timing of the reproduced Y signal and color signal at this time is shown in FIG. In FIG. 11, 16 is a reproduced Y signal, 2o is a reproduced compressed color signal, and 21
-1 is an HD signal during playback created from the playback signal of the horizontal synchronization signal added to the color signal, and 174 -1.18-1 is the playback I expanded based on the HD signal 21-1. signal and Q signal, 21-2 is an HD signal created from the horizontal synchronization signal in the reproduced Y signal, 1
7-Regarding 18-2 are reproduced I and Q signals respectively expanded based on the HD signal 21-2. In this way, the reproduced Y signal and I signal.

A time difference will occur between the Q signals. It is assumed that the HD signal during compression is handled at the same timing as the horizontal synchronizing signal in the Y signal and the horizontal synchronizing signal added to the color signal.

OBJECT OF THE INVENTION The present invention corrects the above-mentioned time difference between the Y signal and the chrominance signal, and obtains a compact, lightweight, and high-quality reproduced video signal, especially a good reproduced signal in which the timings of the luminance signal and the chrominance signal match. The purpose of this is to provide a device that can do this.

Structure of the Invention The present invention is a video signal recording and reproducing device that uses a clock synchronized with the reproduction I+Q signal when writing and a clock synchronized with the output Y signal when reading as a clock for operating a time axis expander. , it is possible to expand the compressed I+Q signal and at the same time match the timing of the expanded I, Q signals and the reproduced Y signal.

DESCRIPTION OF THE EMBODIMENTS FIG. 12 shows a block diagram of a time axis expansion device in one embodiment of the reproduction system of the present invention.

66 is a reproduced Y signal, 66 is a reproduced I10 signal (time axis compressed signal), 57 is a 2H+a delay line, 68 is a horizontal synchronizing signal separator, 69 is a time axis expander, 6o is a clock generator 61 is a horizontal synchronizing signal separator, 62 is 2H+α
Delayed Y signal, 63 is a time-axis expanded engineering signal output terminal, 64 is a time-axis expanded Q signal output terminal, 66 is a horizontal synchronization signal separated from the reproduced Y signal, 66 is a reproduced I signal
A horizontal synchronizing signal 67 separated from the signal 10 is a clock for operating the time axis expander.

First, the reproduced Y signal 66 is input to a 2H+α delay circuit 67 and delayed by 2H+α. As shown in Figure 10, when compressed and expanded, the color signal changes from the Y signal to 2H.
The delay is unavoidable, and the reason why the delay is further delayed by α is because if the color signal lags behind the Y signal, it cannot be corrected.

Next, a part of this delayed signal is sent to the terminal 62 as a reproduced Y signal.
A portion thereof is input to a horizontal synchronizing signal separator 68, where a horizontal synchronizing signal 66 is separated. This horizontal synchronization signal 66 is input to the clock generator 6o, and a first clock signal (n: integer, number of stages of COD) having a frequency of "fH-Y" is synchronized with the reproduced output Y signal 62.

fH-y: indicates the horizontal frequency synchronized with the output Y signal. )
is output.

Still, a part of the reproduced I+Q signal 66 is input to the time axis expander 69, and the signal 63. It is output as a Q signal 64,
A portion is input to a horizontal synchronizing signal separator 61, where a horizontal synchronizing signal 66 is separated. This horizontal synchronizing signal 66 is input to the clock generator 6o, and a second clock signal of frequency 2"f) (-Y) synchronized with the reproduced I+Q signal (n is the number of CCD stages, fH-C is the horizontal synchronized with the I+Q signal ) is output.

17. , ``When inputting the output 67 of the clock generator 6o to the time axis expander 59 as a clock signal and inputting the reproduced I+Q signal to the time axis expander 69, the above-mentioned When reading using the second clock signal, the I+Q signal 66 is expanded by reading with the first clock signal synchronized with the reproduced Y signal 66, and the I signal 6
3. A Q signal 64 is obtained.

The thus expanded reproduced I signal 63. It is assumed that the Q signal 64 has no time difference with the reproduced Y signal 62.

This will be described in detail later.

FIG. 13 shows a block diagram of the clock generator.

66 is a horizontal synchronization signal of frequency fH-Y synchronized with the Y signal, 66 is a horizontal synchronization signal of frequency fH-C synchronized with the I+Q signal, and 67-1 to 67-8 are clocks for operating the time axis expander. , 68. 69°70.71,72,
73, 74.75 are SW multiplied signals 76.79 are SW signal generators, 77 is the first clock 8 with frequency "fH-Y"
PLL for generating o, 78 has frequencies 2n, 7'
92 is a gate for generating the clock 81 of the second-C 8 .

The 14th shows the SW double signal timing synchronized with the IQ signal. 66 is a horizontal synchronization signal synchronized with the I+Q signal, 72
．． 73 indicates the timing for writing the I signal.

FIG. 15 shows the SW double signal timing synchronized with the Y signal. 66 is a horizontal synchronization signal synchronized with the Y signal, 68 to 71
indicates the read timing.

FIG. 16 shows the timing of the clock input to the time axis expander. 65 is a horizontal synchronizing signal of frequency fH-Y synchronized with the output Y signal, 66 is a horizontal synchronizing signal of frequency fH-C synchronized with the I10 signal, and 63.64 is the expanded I, Q signal of 11°I2・・・・・・、Ql
, Q2. ...is the line! 1, 2.・・・・・・
...is shown.

67-1 shows the clock and timing for writing I3 and reading I2, and 67-2 writes I3 and reads I2. 67-3 shows the clock to read I4 and its timing, 67-3 shows the clock to write I4 and its timing, 67-4 shows I4
The clock and timing for writing and reading part 4 are shown below. 67-6 indicates the clock to write Q2 and read Q2 and its timing, 67-6 indicates the clock to write Q3 and read Q3 and its timing, and 67-7 indicates the clock to write Q4 and read Q4 and its timing. Indicates timing, 67-8 writes Q6,
The clock for reading Q6 and its timing are shown.

The configuration of the clock generator will be explained using FIG. 13. A horizontal synchronizing signal 65 of frequency fH-Y is supplied to the clock generator 6o.
When inputted, the first clock signal of frequency "fH-Y" is generated by the PLL 77, and when the horizontal synchronization signal 66 is inputted to the SW signal generator 76, the first clock signal 68. is synchronized with the Y signal shown in FIG. The SW multiplied signal of 69°70.71 is output. Also, when the horizontal synchronizing signal 66 of the frequency wave fH-C is input, the second clock signal 81 of the frequency 2 n f H-c is generated in the PLL 78. When the horizontal synchronizing signal 66 is input to the SW signal generator, SW multiplied signals of 72, 73, and 74.75 are output in synchronization with the I+Q signal shown in FIG. 1
6 Figure 67-1. 67-2. 67-3.67-4.
67-5. 67-6, 67-7. A clock shown at 67-8 is output and input to the time axis expander 59.

FIG. 17 is a block diagram showing the configuration of the time axis expander. 66 is an input terminal for I+Q signals, and 82 to 89 are variable delay elements COD. 67-1 to 67-8 are COD
This is the clock input terminal for operating the . 93-1
00 are the outputs of C0D82-89, respectively. 90.
91 is a gate for obtaining output signals I and Q;
63 and 64 are output terminals for I and Q signals.

I+Q signal 56 is input to each C0D 82-89. The COD is composed of n stages, and is delayed by 1H with a clock of frequency "fH-Y" and delayed by 0.5H with a clock of frequency 2n f H-c.
When writing with a clock of n'H-Y and reading with a clock of frequency n'H-Y, the time axis is expanded twice. Therefore, by inputting the clocks shown at 67-1 to 67-8 to the respective C0Ds 82 to 89, signals whose time axes have been expanded are output from 93 to 1o◯ and input to the gates 90 and 91.

An I signal is output to the terminal 63 by switching the SW signals 6B, 69, 70, and 90.

A Q signal is output to the terminal 64 by switching the gate 91 using the sw signals 68, 69, 70, and 71.

The principle of matching the timing of the color signal to the timing of the Y signal at the same time as time axis expansion will be explained in detail using FIGS. 16 and 17.

The operation of COD will be explained once again. When n stages of COD are driven with a clock having a frequency of nfH, the time required for one stage of charges to move is 1/nfH7, resulting in n stages and a delay time of 1H. Similarly, if the CCD is driven with a clock having a frequency of 2 n fH, the delay time of o and esH will be 2 times.

Assume that the timings of the Y signal and the color signal are different from each other as shown in FIG. 16 at 65 and 66.

As shown in FIG. 17, when the CCD 52 is operated with a clock 67-1, as can be seen from the timing of FIG. 16 67-1, the frequency is 2 n f while the signals of
The CCD 82 is driven by the second clock of Hc, and I2 is written into the CCD 82. Next, when a signal is output from the CCD 82, the first
clock. However, the frequency "fH-Y
The first clock is synchronized with the Y signal, and when driven by the second clock having a frequency of 2nf, the delay time is -C02 times. Therefore, the output 9 of CCD82
3 is an I2 signal synchronized with the I2 signal.

Similarly, C0D83,84.85 is clocked at 67-
2. 67-3. When driven with 67-4, the angle is 94°95.
I3 in 96. I4. I5 signal is output. Input these outputs 93, 94, 95.96 to Goo) 90 and switch
When the signals 68, 69, 70, and 71 are switched to 23, the I signal is output to the terminal 63.

Well, if you operate C0D86 with clock 67-5, Q2 will synchronize with Y2 signal in the same way as the engineering signal.
It is output to 97 as two signals.

Similarly, C0D87, 88.89 is clocked 67-6.
, 98°99.1 when driven with 67-7, 67-8
00 to 03. Q4. Q6 signal is output.

These outputs 97.98, 99, 100 are input to the gate 91, and the SW signals 68. 69. 70. When switched at 71, a Q signal is output to terminal 64.

As described above, according to the present invention, a clock synchronized with the I+Q signal is used during writing, and a clock synchronized with the reproduced output Y signal is used during reading, thereby expanding the compressed color signal (I+Q) and simultaneously The timing can be matched with the luminance signal.

Furthermore, for the 2H+α delay of the Y signal, an ultrasonic delay line or CO
Using any fixed analog delay line such as D), A/D
, it can be digitally delayed using D/A, but if you use a variable delay line to delay 2H+α,
The time axis of the Y signal can be corrected, and since the color signal is also synchronized with the Y signal, the time axis of the color signal can be corrected at the same time as the time axis of the Y signal.

Effects of the Invention By using the present invention, it is possible to expand a compressed I+Q signal and at the same time match the timings of the expanded I, Q signals and Y signal, thereby obtaining a good reproduced signal. be.

Furthermore, it becomes very easy to miniaturize and simplify the circuit.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the recording pattern of a conventional VTR, Fig. 2 is a plan view showing the head arrangement of the video signal recording and reproducing device used in the present invention, Fig. 3 is a front view of the main parts, and Fig. 4 is a diagram showing the recording pattern of a conventional VTR. A diagram showing an example of a recording pattern by the head, FIG. 6 is a block diagram of the sixth worst recording pattern by the head, and FIG. FIG. 9 shows the waveforms and signal order of each part, and FIG. 11 shows FIGS. 6 and 7. FIGS. 8 and 9 are waveform diagrams of various parts showing the timing of the reproduced signal, FIG. 12 is a block diagram showing an overview of a video signal recording device according to an embodiment of the present invention, and FIG. 13 is a clock generation diagram of the main parts. Figure 14 is a diagram showing the timing of the clock switching signal synchronized with the I+Q signal, Figure 15 is a diagram showing the timing of the clock switching signal synchronized with the Y signal, and Figure 16 is a diagram showing the timing of the clock switching signal synchronized with the Y signal. FIG. 17 is a block diagram showing an example of a time axis expander. 69...Time axis extender, 60...Clock generator, 58.61...Horizontal synchronization signal separator,
77°78...PLL circuit, 76.79...
...SW signal generator, 90,91.92...
Gate circuit, 82°83, 84. 85. 86.
87. 88. 89...CCD. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 6
Figure 8 Figure 9 Figure 7 Figure 13 Figure 14 Figure 16 Figure 17 Figure 8?

Claims (2)

[Claims] (1) Out of the three signal components that form a video signal, one component A is compressed on the time axis by a pair of heads, and the other two components B and C are compressed in fixed period units, resulting in two time-compressed components. B and C are recorded alternately as one signal (B+C) using another pair of heads, and during playback, the (B10) signal is output on the time axis in units of a fixed period using a delay element operated by a clock. When expanding to obtain the original A, B, and C signals, the read clock supplied to the delay element is synchronized with the write clock (B+C) signal supplied to the delay element of the time axis expansion circuit to the reproduced A signal. A video signal recording and reproducing device characterized in that the timings of reproduction A, B, and C signals are made to match by synchronization. (2) Of the luminance signal and two color signal components that form the video signal, the luminance signal is recorded by a pair of heads, and the two color signal components are compressed on the time axis in units of a fixed period and converted into one signal. 2. The video signal recording and reproducing apparatus according to claim 1, wherein recording is performed using a pair of heads.