JPS59104814A - Phase separating circuit - Google Patents

Phase separating circuit

Info

Publication number
JPS59104814A
JPS59104814A JP21532682A JP21532682A JPS59104814A JP S59104814 A JPS59104814 A JP S59104814A JP 21532682 A JP21532682 A JP 21532682A JP 21532682 A JP21532682 A JP 21532682A JP S59104814 A JPS59104814 A JP S59104814A
Authority
JP
Japan
Prior art keywords
phase
circuit
input
input signal
separation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21532682A
Other languages
Japanese (ja)
Inventor
Masaki Ichihara
正貴 市原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP21532682A priority Critical patent/JPS59104814A/en
Publication of JPS59104814A publication Critical patent/JPS59104814A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/16Networks for phase shifting
    • H03H11/22Networks for phase shifting providing two or more phase shifted output signals, e.g. n-phase output

Landscapes

  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To simplify the titled circuit and to reduce number of components by forming two phase shifters by a dual phase shift circuit using only one operational amplifier. CONSTITUTION:Variable resistors R17, R21 constitute an input separating circuit separating an input signal IN. Resistors R19, R20 consititute a gain setting circuit dividing the input signal IN and setting the gain of operational amplifiers 6, 7. The gain setting circuit is connected in common to eacg in-phase input terminal (non-inverting input terminal)+ of the operational amplifiers 6, 7. Thus, a prescribed phase difference is obtained at a broad frequency band around the center frequency. Thus, the circuit is simplified and the number of components is reduced.

Description

【発明の詳細な説明】 本発明は、位相分離回路に関し、特に、演算増幅器によ
る能動型移相器を用いて入力信号を同−振幅一定位相差
の2つの出力信号に分離する位相分離回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase separation circuit, and more particularly to a phase separation circuit that separates an input signal into two output signals having the same amplitude and a constant phase difference using an active phase shifter using an operational amplifier. .

従来、この種の位相分離回路では、@1の方法として、
第1図に示す様に、入力信号を分離し、−力を適当な移
相器に通すことにより、一定の位相差を生成する方式が
ある。この方式は回路が簡単で部品点数が少くて済むが
、移相器の移相量が周波数によって変化するために、広
周波数帯域に渡って一定位相差を得ることができない。
Conventionally, in this type of phase separation circuit, as method @1,
As shown in FIG. 1, there is a method of generating a constant phase difference by separating the input signals and passing the -power through a suitable phase shifter. Although this method has a simple circuit and requires fewer parts, it is not possible to obtain a constant phase difference over a wide frequency band because the amount of phase shift of the phase shifter changes depending on the frequency.

例えば、第1図の回路では、几a=4R4、R1=Rg
冨焦C1=C2=Cとすると、出力OU’l” lの入
力に対する伝達関数は、 で表わされ、これより出力0UTI 、0UT2間の位
相差2は、 −z 4 xRc f ’ ”’ −218’ 「シV斤・−−−−−−−−−
−−−−−−−−−(2)となる、ここで、fは信号の
周波数である。この式から明らかな様に、位相差劇は周
波数によって大きく変化するために、入力信号の周波数
を狭い範囲に限定しなければならない。又、演算増幅器
自身の位相回りがあるために、移相量の調整が難かしい
For example, in the circuit of FIG. 1, a=4R4, R1=Rg
When the focus C1=C2=C, the transfer function for the input of the output OU'l''l is expressed as follows, and from this, the phase difference 2 between the outputs 0UTI and 0UT2 is -z 4 xRc f'''' - 218' ``Shi V cat・------------
----------(2) where f is the frequency of the signal. As is clear from this equation, the phase difference greatly changes depending on the frequency, so the frequency of the input signal must be limited to a narrow range. Furthermore, since there is a phase shift of the operational amplifier itself, it is difficult to adjust the amount of phase shift.

以上の欠点を改善した第2の方法とし−C1第2図に示
す様に、分岐した入力信号をそれぞれ独立した移相器に
通す方法がある。この方式では移相器を多段の移相回路
を用いて構成しておシ、両移相器が互いに移相量の変動
を相殺し合うことによって、出力間の位相差を広い周波
数帯域で#丘は一定にしている。
A second method that improves the above drawbacks is a method in which the branched input signals are passed through independent phase shifters, as shown in FIG. In this method, the phase shifter is configured using a multi-stage phase shift circuit, and both phase shifters cancel out the fluctuations in the amount of phase shift, thereby reducing the phase difference between the outputs over a wide frequency band. The hill remains constant.

第2図に示した構成の動作特性を第3図(a)、(b)
に示すと出力0UTI、0UT2の入力INに対する位
相が1231SOmの様に、周波数に対する変化はあっ
ても(第3図(a) ) 、その差6戸は広い周波数範
囲Bでほぼ一定にする事が出来る(第3図(b))。
Figures 3(a) and (b) show the operating characteristics of the configuration shown in Figure 2.
As shown in Figure 3, the phase of the outputs 0UTI and 0UT2 relative to the input IN is 1231SOm, so even though there is a change in frequency (Figure 3 (a)), the difference can be kept almost constant over a wide frequency range B. It is possible (Fig. 3(b)).

例えば、第2図の回路において出力間の位相差ダを約9
06にする場合について検討するに、この場心用波数、
と設定すると、出力0UT1.0UT2の伝達関数Hz
(s) 、H寓(3)はそれぞれ、となシ、出力間の位
相差ダは、 但し、X1=fx/fo 、 X=f/f。
For example, in the circuit shown in Figure 2, the phase difference between the outputs is approximately 9
Considering the case where it is set to 06, this field wave number,
When set, the transfer function Hz of output 0UT1.0UT2
(s), H (3) are respectively, and the phase difference between the outputs is as follows. However, X1=fx/fo, X=f/f.

となる。この数値計算例を第5図に示す、第5図は、k
=0.29、b=51.95fo、fl=o、59fo
、fx’ =1.6Bfo。
becomes. An example of this numerical calculation is shown in Figure 5.
=0.29, b=51.95fo, fl=o, 59fo
, fx' = 1.6Bfo.

b’=0.14 ” %とじた場合の位相差ダと周波数
fとの関係を示したものである。これにより、出力間の
位相差ダは約+fOから3foの広い周波数範囲でほぼ
一定の値(中90°)となることがわかる。
This shows the relationship between the phase difference DA and the frequency f when b'=0.14''%.As a result, the phase difference DA between the outputs is almost constant over a wide frequency range from approximately +fO to 3FO. It can be seen that the value is (90° in the middle).

しかしながら、この方式では、多数の演算増幅器を使用
するために、回路が複雑になり、又、高い周波数では、
演算増幅器自身の位相回りによる誤差が累加するために
、設計通りの位相差を得ることが困難である。更に、2
つの移相器が完全に分離しているために、抵抗器の誤差
等によって各出力のレベルにばらつきが生じるといった
欠点があった。
However, this method uses a large number of operational amplifiers, which makes the circuit complicated, and at high frequencies,
Since errors due to the phase of the operational amplifier itself accumulate, it is difficult to obtain a designed phase difference. Furthermore, 2
Since the two phase shifters are completely separated, there is a drawback that the level of each output varies due to errors in the resistors.

本発明は従来方式による上記欠点を解消する為になされ
たものであり、従って本発明の目的は、前記の@2の方
法を改め、各移相器をただ1つの演算増幅器を用いた2
次移相回路とすることによシ、回路を簡単化し、部品点
数を削減した新規な位相分離回路を提供することにある
The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional method, and therefore, an object of the present invention is to modify the method @2 and replace each phase shifter with a single operational amplifier.
The object of the present invention is to provide a new phase separation circuit which has a simplified circuit and a reduced number of parts by using a second phase shift circuit.

本発明の他の目的は、2つの移相器の演算増幅器の同相
入力端子を互いに共有させることにより、出力間のレベ
ル差が抵抗器等の誤差に影響されることなく、零とする
ことを可能にした新規な位相分離回路を提供することに
ある。
Another object of the present invention is to make it possible to reduce the level difference between the outputs to zero without being affected by errors in resistors, etc. by sharing the common-mode input terminals of the operational amplifiers of the two phase shifters. The object of the present invention is to provide a novel phase separation circuit that makes it possible.

上記薄目的を達成する為に、本発明に係る位相分離回路
は、入力信号を分離する入力分離回路と、該入力分離回
路に接続され前記入力信号に対して第1の位相関係を侍
るように第1の演算増幅器を用いた能動型2次移相回路
で構成された第1の移相器と、前記入力分離回路に接続
され前記入力信号に対して第2の位相関係を得るように
第2の演算増幅器を用いた能動型2次移相回路で構成さ
れた第2の移相器と、前記第1及び第2の演算増幅器の
各同相入力端子が共通に接続された利得設定回路とを具
備して構成される。
In order to achieve the above object, a phase separation circuit according to the present invention includes an input separation circuit that separates input signals, and an input separation circuit that is connected to the input separation circuit and has a first phase relationship with respect to the input signal. a first phase shifter configured with an active quadratic phase shifter using a first operational amplifier; a second phase shifter configured with an active second-order phase shift circuit using two operational amplifiers; and a gain setting circuit to which common-mode input terminals of the first and second operational amplifiers are commonly connected. It is equipped with:

次に本発明をその好ましい一実施例について図面を参照
しながら詳細に説明する。
Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

第4図は本発明の一実施例を示す回路構成図である。図
において、参照符号INは入力信号、0UT1.0UT
2は出力信号をそれぞれ示す、参照番号6及び7はそれ
ぞれ演算増幅器を示している。可変抵抗器&y及びR1
1は入力信号INを分離する入力分離回路を構成してい
る。抵抗器Rxo及びRsoは入力信号INを分圧し、
演算増幅器6及び7の利得を設定する利得設定回路を構
成している。抵抗器Rx e 、Rgoにより構成され
た利得設定回路は、図示の如く、演算増幅器6及び7の
各同相入力精子(非反転入力端子)十に共通に接続され
ている。
FIG. 4 is a circuit configuration diagram showing an embodiment of the present invention. In the figure, reference symbol IN is an input signal, 0UT1.0UT
Reference numerals 2 and 7 respectively indicate output signals and operational amplifiers. Variable resistor &y and R1
1 constitutes an input separation circuit that separates the input signal IN. Resistors Rxo and Rso divide the input signal IN,
It constitutes a gain setting circuit that sets the gains of operational amplifiers 6 and 7. A gain setting circuit constituted by resistors Rx e and Rgo is commonly connected to each in-phase input terminal (non-inverting input terminal) of the operational amplifiers 6 and 7, as shown.

Rho    G =”’TCX’;;V = ’ TTG  となる時、
f =f11fa=k”fxk:任意の正数と設定する
と、出力0UTI 、0UT2 の入力信号に対する伝
達関数)(1(s)、HべS)は、 Hl(8)=G″唱1ψW −、、−一一−−−−−−
−−−−−−−−−一(6)(+2π )(+2π(a
) (S−2πfz’)(8−2π”′)−−−−−−−−
−−−−−−−−<7))(g(s)=G−42.rl
+2g ”)となる、これは、演算増幅器の利得Gを除
けば、前記第2図に示した回路の伝達関数と同型であり
、故に、本回路においても、中心周波数(=(o周辺の
広い周波数帯域で、第2図の回路と同様の一定位相差グ
が得られる。
When Rho G = “'TCX’;; V = 'TTG,
f=f11fa=k"fxk: When set to any positive number, the transfer function for input signals of outputs 0UTI and 0UT2) (1(s), HbeS) is Hl(8)=G"1ψW-, , -11------
−−−−−−−−−1(6)(+2π )(+2π(a
) (S-2πfz') (8-2π"')----------------------
----------<7)) (g(s)=G-42.rl
+2g''), which is the same type as the transfer function of the circuit shown in Figure 2 above, except for the gain G of the operational amplifier. A constant phase difference similar to the circuit of FIG. 2 is obtained in the frequency band.

一力、本発明の回路では、各移相器の演算増幅器が、同
相入力端子を共有しているために、出力0UTI、0U
T2のレベルは共に抵抗器R19、R諺Oのみによって
決定される。よって、抵抗器の誤差に関係な(・出力0
UTl、0UT2は同じレベルになる。
First, in the circuit of the present invention, since the operational amplifiers of each phase shifter share the common-mode input terminal, the outputs are 0UTI and 0U.
Both levels of T2 are determined solely by resistor R19. Therefore, it is related to the error of the resistor (・output 0
UTl and 0UT2 are at the same level.

以上で説明した様に、本発明では、2つの移相器を演算
増幅器をただ1つだけ用いた能動型2次移相回路で構成
することにより、部品点数を削減し、演算増幅器自身の
位相口りによる位相誤差を最小限に押えた。
As explained above, in the present invention, by configuring the two phase shifters with active quadratic phase shift circuits using only one operational amplifier, the number of parts can be reduced and the phase of the operational amplifier itself can be reduced. The phase error caused by the mouth is kept to a minimum.

さらに各演算増幅器の同相入力端子を共有することによ
り、出力間のレベル差が生じなくなり、出力レベルの調
整が容易になった。
Furthermore, by sharing the common-mode input terminal of each operational amplifier, there is no difference in level between the outputs, making it easier to adjust the output level.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来方式による位相分離回路図、第
3図は位相分離回路の原理を示すグラフ、第4図は本発
明に係る位相分離回路の一実施例を示した回路構成図、
第5図は位相分離回路の位相特性を具体的に計算したグ
ラフである。 1.2.3.4.5.6.7・・・演算増幅器、Rx、
Ra、−a@@m@m@”・・・抵抗器、Cz、C寓い
、、、、1.、Cx1・・・コンデンサ、0UTI 、
0UT2−・・各位相分離回路の出力、IN・−・各位
相分離回路の入力特許出願人   日本電気株式会社 代 理 人   弁理士 熊谷雄太部
1 and 2 are phase separation circuit diagrams according to the conventional method, FIG. 3 is a graph showing the principle of the phase separation circuit, and FIG. 4 is a circuit configuration diagram showing an embodiment of the phase separation circuit according to the present invention. ,
FIG. 5 is a graph in which the phase characteristics of the phase separation circuit are specifically calculated. 1.2.3.4.5.6.7...Operation amplifier, Rx,
Ra, -a@@m@m@”...Resistor, Cz, C example,,,1.,Cx1...Capacitor, 0UTI,
0UT2--Output of each phase separation circuit, IN--Input of each phase separation circuit Patent applicant: NEC Corporation Representative, Patent attorney Yutabe Kumagai

Claims (1)

【特許請求の範囲】[Claims] 入力信号を分離する入力分離回路と、該入力分離回路に
接続され前記入力信号に対して第1の位相関係を得るよ
うに第1の演算増幅器を用いた能動型2次移相回路で構
成された@1の移相器と、前記入力分離回路に接続され
前記入力信号に対して第2の位相関係を得るように第2
の演算増幅器を用いた能動型2次移相回路で構成された
第2の移相器と、前記第1及び第2の演算増幅器の各同
相入力端子が共通に接続された利得設定回路とを具備す
ることを特徴とした位相分離回路。
an active quadratic phase shift circuit connected to the input separation circuit and using a first operational amplifier so as to obtain a first phase relationship with respect to the input signal; a second phase shifter connected to the input separation circuit and configured to obtain a second phase relationship with respect to the input signal;
a second phase shifter configured with an active secondary phase shift circuit using an operational amplifier; and a gain setting circuit to which common-mode input terminals of the first and second operational amplifiers are commonly connected. A phase separation circuit characterized by comprising:
JP21532682A 1982-12-07 1982-12-07 Phase separating circuit Pending JPS59104814A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21532682A JPS59104814A (en) 1982-12-07 1982-12-07 Phase separating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21532682A JPS59104814A (en) 1982-12-07 1982-12-07 Phase separating circuit

Publications (1)

Publication Number Publication Date
JPS59104814A true JPS59104814A (en) 1984-06-16

Family

ID=16670442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21532682A Pending JPS59104814A (en) 1982-12-07 1982-12-07 Phase separating circuit

Country Status (1)

Country Link
JP (1) JPS59104814A (en)

Similar Documents

Publication Publication Date Title
KR100341231B1 (en) Phase shifter
JP2005328260A (en) Band pass filter
EP0756780B1 (en) Improvements in or relating to communications receivers
US4525677A (en) Differential amplifier having high common-mode rejection ratio
US4275357A (en) Active filter
JPS63500839A (en) Balanced variable reactance generation circuit and its generation method
JPS59104814A (en) Phase separating circuit
JPS63191408A (en) Filter
US4158184A (en) Electrical filter networks
JPH0326012A (en) Phase shifter
JPS6031368B2 (en) band wave generator
US4456885A (en) Filter circuit suitable for being fabricated into integrated circuit
JPH03192904A (en) Variable frequency oscillator circuit
JPS61170113A (en) Second order active phase equalizer
JPS62183209A (en) Band pass filter
JP2016225882A (en) High frequency filter circuit and high frequency mixer
GB2030806A (en) Receiver front end arrangement
US3158817A (en) Frequency responsive apparatus with dual output filter
JPS606134B2 (en) RC active bundle direct filter
JPS6326104A (en) Variable phase frequency conversion circuit
SU799107A1 (en) Active rc-filter
JPH02222308A (en) Signal processor
JPH0998067A (en) 90-degree phase shifter
JPH0322644A (en) Pilot signal eliminating system
JPS62272608A (en) Phase shifting device