JPS59104795A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decide the use of a redundant function with a simple test by measuring the current flowing between the 1st input terminal and an earth terminal after applying the voltage higher than the threshold voltage of field effect transistor MOST of the 1st insulated gate type. CONSTITUTION:When the redundant function is ued due to the existence of a defective bit, one of normal decoders is replaced with a spare decoder 13a, for example, and activated. Thus an END signal is delivered from an END signal generating drum 15, and therefore the 2nd MOST11 is turned on. Then the use of the redundant function is decided by impressing the voltage of about 5V to the 1st input terminal 7. At the same time, the voltage, e.g., 10V is impressed to the 2nd input terminal 8 in order to turn on the 1st MOST10. As a result, both 1st and 2nd MOST10 and 11 are turned on when the redundant function 7 and a ground terminal 9 is through the MOST10 and 11.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to, for example, an insulated gate field effect transistor (
(hereinafter referred to as MO8T) is the basic element of the memory cell,
The present invention relates to a semiconductor memory device with a redundancy function that replaces a defective bit with a spare memory cell when a defective bit exists.

[Prior art]

FIG. 1 is a block diagram showing a conventional semiconductor memory device with a redundancy function. In the figure, (1) is a memory cell array in which memory cells are arranged in a matrix, and (2) is a memory cell array in which memory cells are arranged in a matrix.
) is a row decoder that receives address input signals (Ao) to (Am-1) and obtains two row selection signals, and (3) receives address input signals (Am) to (An) and obtains 2N row selection signals. (
However, (4) is a column decoder that obtains a column selection signal (n-m=N), and an output terminal (4) that outputs a read output signal Q.
4a) and an input terminal (4a) to which the data input signal is input.
b) serving as an output buffer for the data signal read from the memory cell at the intersection of the selected row and column and serving as an input buffer for writing write data D to the selected memory cell;
(5) is a spare memory cell row with spare memory cells;
(6) is a spare row decoder corresponding to this spare memory cell row (5).

Although other signals necessary for the functions of this semiconductor memory device with redundant function are not shown in the figure, they are of course provided.

Next, the operation of the semiconductor memory device with redundancy function having the above configuration will be explained. First, memory cell array (1)
If, for example, one bit or one row of defective bits exists due to a manufacturing defect in the memory, and this defective bit is detected during a memory wafer test, the selected row is inactivated and activated by the selection signal. replace the defective row decoder with a spare row connected to it, and eliminate the defect.
As a method of inactivating this defective bit and activating the spare decoder, there are methods of cutting the built-in fuse electrically or with laser light, and methods of reducing the resistance of high-resistance fuses with laser light. However, since both methods are carried out inside the memory device, it is not possible to determine whether the memory uses the redundant function after being packaged. Therefore, recently, as a method to determine whether the memory is using the redundant function even after being stored in the package, the input terminal (4b) to which the memory data input signal is input is set to a high voltage and the address signal is input. However, a method of checking the read output signal Q has been proposed. That is, the memory cells corresponding to the address signals that cause the read output signal Q to be at a low level use the redundancy function, while the memory cells that correspond to the address signals that cause the read output signal Q to be at a high level use the spare bits. It is determined that the

However, conventional semiconductor memory devices with a redundancy function have a drawback that it is impossible to determine whether the memory device uses the redundancy function without using a complicated test.

[Summary of the invention]

Accordingly, the present invention provides a semiconductor memory device with a redundancy function that includes a built-in semiconductor circuit that allows a simple test to determine whether or not the memory device uses the redundancy function.

To achieve this purpose, the present invention provides a first insulator whose drain is connected to a first input terminal, whose gate is connected to a second input terminal, and whose threshold voltage is higher than the maximum insulation rating of the memory. An NWD (@signal generation circuit and a drain connected to the first
a second insulated gate field effect transistor connected to the source of the insulated gate field effect transistor, whose gate is connected to the output terminal of the NED signal generation circuit, and whose source is connected to the ground terminal; A desired voltage is applied to the first input terminal, and a voltage higher than the threshold voltage of the first insulated gate field effect transistor is applied to the second input terminal, so that the first input terminal and the ground terminal are connected. By measuring the current flowing during this period, it is possible to determine whether or not the redundant function is to be used, and will be described in detail below using examples.

[Embodiments of the invention]

FIG. 2 is a circuit diagram showing an embodiment of a semiconductor circuit built into a semiconductor memory device according to the present invention.

In the figure, (7) is the first input signal to which the data input signal is input.
An input terminal, (8) is a second input terminal into which a read/write control signal is input, (9) is a ground terminal with a ground potential Vss,
In (10), the threshold value is set higher than the absolute maximum rating of the memory. For example, in a normal memory, the power supply voltage used is 5. Since the absolute maximum rating is generally 7 for Ov, the threshold voltage of IMO8T%aυ with a threshold voltage of IOV is lower than the threshold voltage of this first MO8T<101, The threshold value of a transistor (not shown) inside the circuit may be the same as that of a second M at the same level.
08T% (12+ is the third M08T1 (13a) to (1) that amplifies the input data signal input to the first input terminal (7)
3n) is a preliminary decoder, and (14) is this preliminary decoder (
The NOR logic of the decoder output signals of 13a) to (13n)), NED (Normal Element]) cs
It is a NOR circuit that outputs the ``able'' signal.

Note that a9 is the preliminary decoder (13a) to (13n)
This is a NED signal generation circuit that outputs the NED signal generated inside the chip.The NED signal generation circuit 09 is composed of a NED signal generator and a NOR circuit.In order to operate this NED signal generation circuit 09, the memory circuit's RAS, CAJ, and address signals must be input normally. Therefore, it is appropriate that the signals input to the first input terminal (8) and the second input terminal (8) are a data input signal and a read/write control signal, respectively. In addition, in the case of a normal memory, a protection circuit (not shown) is provided between the first input terminal (7) and the ground terminal (9) in order to avoid destruction of the internal circuit due to a large surge voltage applied to the input signal. However, the current flowing between the signal terminal and ground through this protection circuit (not shown) is so small that it can be ignored when the voltage applied to the first input terminal (7) is about twice the maximum rating.

Next, the operation of the semiconductor circuit built into the semiconductor memory device having the above configuration will be explained. First, when the redundancy function is used due to the presence of a defective bit, one of the normal decoders is replaced with a backup decoder (13a), for example, and this backup decoder (13a) is activated. Therefore, N
A NED signal is output from the ED signal generation circuit θ9. Therefore, the second M08T01) is turned on. On the other hand, if the redundancy function is not used, the NED signal generation circuit 0
Since the NBD signal is not output from the phrase, the second M08T (1
1) remains off.

Next, when determining whether or not the redundancy function is used, apply a voltage of about 5V to the first input terminal (7) and apply a voltage of about 5V to the second input terminal (8) to the extent that the first M08TQOl is in the on state. For example, a voltage of 10 V is applied, and this first
M08T(1(l) is turned on. Therefore, when the redundant function is used, both the first M08T(11 and second M08T(lυ) are turned on, so the first input terminal (7) and the ground terminal (9) 1st MO between
8TflO) Tei style flows through Oyohi No. 2 M08TQυ. On the other hand, when the redundancy function is not used, the second M08Tαυ is off, so the first input terminal (7)
No current flows between the ground terminal (9) and the ground terminal (9).

In this way, by applying a relatively high voltage to the second input terminal (8), the presence or absence of current flowing between the first input terminal (7) and the ground terminal (9) is tested. It can be determined whether the redundant function is used.

In the above embodiment, a case was explained in which a data input signal is input to the first input terminal (7) and a read/write control signal is input to the second input terminal (8). Input the light control signal to the second input terminal (
Of course, a data input signal may be input to 8).

〔Effect of the invention〕

As described in detail above, according to the semiconductor memory device according to the present invention, it is possible to determine whether or not spare bits are used by simply adding a simple semiconductor circuit, so that the device can be made inexpensive, and It has the advantage of being easy to test and highly accurate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional semiconductor memory device with a redundant function, and FIG. 2 is a circuit diagram showing an embodiment of a semiconductor circuit built into the semiconductor memory device according to the present invention. (1)...Memory Lua 1/I, (2)...Line decoder, t31-@--Yu11 decoder, (4)・0
Fist/Banfa circuit, (51'-... spare memory cell row,
(6)...Spare row decoder, (7) Life/Fist/1st
Human power terminal, (8)・Fist・・Second input terminal, (9J@・・
- Ground terminal, (10)...First insulated gate field effect transistor, Ov...Second insulated gate field effect transistor, az...Fist, Third insulated gate field effect transistor, (13a )〜(13n)・・・・・
Preliminary decoder, a4J...977 circuit, (15...Fist/NED signal generation circuit. In the diagram, the same reference numerals indicate the same or Buddhist priest parts. f-1 Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1 , Indication of the case Japanese Patent Application No. 57-214969 2, Name of the invention Semiconductor memory device 3, Person making the amendment Relationship to the case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name <601) Mitsubishi Electric Co., Ltd. Representative: Hitoshi Katayama, Part 4, Agent Address: 5, Mitsubishi Electric Co., Ltd., 2-2-3 Marunouchi, Chiyoda-ku, Tokyo, Column 6, Detailed Description of the Invention in the Specification Subject to Amendment, Amendment "dτj" on page 7, line 11 of the description of contents is corrected to [cAsJ. that's all

Claims (2)

[Claims] (1) The drain is connected to the first input terminal, and the gate is connected to the second input terminal.
a first insulated gate field effect transistor connected to the input terminal, whose threshold voltage is higher than the maximum insulation rating of the memory, and a NED signal that outputs a NED signal by performing NOR logic of the decode signal of the preliminary decoder; a second insulated gate electric field having a drain connected to the source of the first insulated gate field effect transistor, a gate connected to the output terminal of the NED signal generating circuit, and a source connected to the ground terminal; an effect transistor, and applies a desired voltage to the first input terminal and applies a voltage higher than the threshold voltage of the first insulated gate field effect transistor to the second input terminal. A semiconductor memory device characterized in that it is possible to determine whether or not a redundant function is to be used by measuring a current flowing between a first input terminal and a ground terminal. (2) A data input signal (or read/write control signal) is applied to the first input terminal, and a read/write control signal (or data input signal) is applied to the second input terminal. A semiconductor memory device according to scope 1.